KR101523678B1 - Programming method of nonvolatile memory device - Google Patents

Abstract

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device programming method.

A programming method for a non-volatile memory device in accordance with the present invention includes driving a first word line to a first local voltage, Driving with a local voltage; And driving the first word line to a third local voltage lower than the second local voltage after the second word line is driven to the second local voltage.

According to the present invention, self-boosting efficiency is increased during a program operation to prevent non-selected memory cells from being programmed.

Description

[0001] PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE [0002]

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device programming method.

There is a growing demand for semiconductor memory devices that can be electrically erased and programmed without requiring refresh for data retention. It is also required to increase the storage capacity of the semiconductor memory device. Flash memory devices provide large storage capacity without refreshing. Flash memory devices are widely used in electronic devices (e.g., portable electronic devices) where power can be suddenly shut off, since they retain data even when the power is turned off.

A flash memory device, well known as a flash EEPROM (electrically erasable programmable read only memory), includes a memory cell array comprised of floating gate transistors. The memory cell array is divided into a plurality of memory blocks. A plurality of bit lines are arranged in parallel in the plurality of memory blocks. Each memory block is provided with a plurality of strings (or "NAND STRING") corresponding to bit lines, respectively.

Each string includes a string select transistor (SST) and a ground select transistor (GST), and a plurality of floating gate transistors are connected in series between the string select transistor and the ground select transistor Lt; / RTI > Each floating gate transistor shares an adjacent floating gate transistor with a source-drain terminal.

And, each string is arranged so that a plurality of word lines cross each other. Control gates of a plurality of floating gate transistors are commonly connected to each word line.

In order to program the memory cells composed of floating gate transistors, first, the memory cells are erased so as to have a predetermined threshold voltage (for example, -3 V). Thereafter, a high voltage (for example, 20 V) is applied to the word line connected to the selected memory cell for a predetermined time to execute a program for the selected memory cell. The threshold voltage of the selected memory cell for the correct program operation is increased and the threshold voltages of the unselected memory cells must not be changed.

However, the program voltage applied to the selected word line is applied not only to the selected memory cell but also to the unselected memory cell connected to the selected word line. As a result, a problem may arise in which unselected memory cells connected to the selected word line are programmed. An unintended program of a non-selected memory cell connected to a selected word line is called a " program disturb. &Quot;

It is an object of the present invention to provide a nonvolatile memory device having improved reliability by reducing a program disturb and a program method thereof.

A programming method for a non-volatile memory device in accordance with the present invention includes driving a first word line to a first local voltage, Driving with a local voltage; And driving the first word line to a third local voltage lower than the second local voltage after the second word line is driven to the second local voltage.

As an embodiment, the method further comprises driving the selected word line to a program voltage after driving the first word line to the third local voltage. And the cell transistor connected to the first word line is turned off by the application of the third local voltage.

In another embodiment, one or more non-selected word lines located between the second word line and the selected word line are driven to a higher pass voltage than the second local voltage before the selected word line is driven to the program voltage . Driving the second word line to a fourth local voltage higher than the second local voltage after driving the second word line to the second local voltage.

A programming method for a non-volatile memory device in accordance with the present invention includes driving a first word line to a first local voltage, Driving a third word line to a third local voltage and driving a fourth word line between the third word line and the selected word line to a fourth local voltage lower than the third local voltage; Driving the first word line to a fifth local voltage lower than the second local voltage after the second word line is driven to the second local voltage and driving the fourth word line to the fourth local voltage Driving the third word line to a sixth local voltage lower than the fourth local voltage; And driving the selected word line to a program voltage after the first word line is driven to the fifth local voltage and after the third word line is driven to the sixth local voltage, Line is located between the second word line and the fourth word line.

In an embodiment, the cell transistor connected to the first word line is turned off by application of the fifth local voltage, and the cell transistor connected to the third word line is turned off by application of the sixth local voltage.

As another example, one or more non-selected word lines located between the second word line and the selected word line may be driven to a higher pass voltage than the second local voltage before the selected word line is driven to the program voltage And driving one or more non-selected word lines located between the fourth word line and the selected word line to the pass voltage higher than the fourth local voltage.

According to the present invention, self-boosting efficiency is increased during a program operation to prevent non-selected memory cells from being programmed.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

A non-volatile memory device is used below as an example to describe the features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein, and the present invention may also be embodied or applied in other embodiments. In addition, the detailed description can be modified or changed in accordance with aspects and applications without departing from the scope of the invention, technical idea and other objects.

One of the techniques for preventing program disturb is a program inhibition method using a self-boosting scheme. A method for inhibiting a program using a self-boosting scheme is disclosed in U.S. Pat. Patent No. No. 5,677,873 entitled " METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN " Patent No. No. 5,991,202, entitled " METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MMEORY ", incorporated herein by reference.

In a program inhibition method using a self-boosting scheme, a ground path is cut off by applying a voltage of 0V to the gate of a ground select transistor. A voltage of 0V is applied to the selected bit line, and a power supply voltage Vcc is applied to the non-selected bit line as a program inhibition voltage.

At the same time, after the source of the string selection transistor is charged (Vcc-Vth, Vth is the threshold voltage of the string selection transistor) by applying the power supply voltage Vcc to the gate of the string selection transistor, the string selection transistor is substantially cut off , Shut-off).

The channel voltage of the program inhibited cell transistor is then boosted by applying the program voltage Vpgm to the selected word line and applying the pass voltage Vpass to the unselected word lines. This prevents FN tunneling between the floating gate and the channel, resulting in the program inhibited cell transistor being held in its initial erased state.

Another technique is to inhibit a program using a local self-boosting scheme. A method for inhibiting a program using a local self-boosting scheme is disclosed in U.S. Pat. Patent No. No. 5,715,194 entitled " BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY " Patent No. No. 6,061,270, titled " METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL ", and is included as a reference.

In a program inhibition method using a local self-boosting scheme, a voltage of 0V is applied to two unselected word lines adjacent to a selected word line. Then, after the pass voltage (Vpass, for example, 10V) is applied to the other unselected word lines, the program voltage Vpgm is applied to the selected word line.

Under these bias conditions, the channel of the self-boosted cell transistor is limited to the selected word line and the channel boosting voltage of the program inhibited cell transistor is increased compared to the program inhibition method using the self-boosting scheme. Therefore, there is no F-N tunneling between the floating gate and the channel of the program inhibited cell transistor, so that the program inhibited cell transistor is kept in the initial erased state.

1 is a block diagram illustrating a non-volatile memory device in accordance with the present invention. Referring to FIG. 1, a nonvolatile memory device 100 according to the present invention includes a memory cell array 110, a control logic circuit 120, a voltage generator 130, a row decoder 140, a page buffer 150, And a column decoder 160.

Although not shown in the figure, the memory cell array 110 is comprised of memory cells arranged in a matrix of rows (or word lines) and columns (or bit lines). The memory cells may be arranged to have a NAND or NOR structure. In the NAND architecture, each memory cell string includes transistors connected in series.

The control logic circuit 120 is configured to control the overall operation of the non-volatile memory device 100. As an example, control logic circuit 120 controls a series of operations related to program operation. For example, the control logic circuit 120 may be a state machine storing a program sequence. However, it should be apparent to those skilled in the art that the control logic circuit 120 is not limited to what is disclosed herein. For example, the control logic circuit 120 may be configured to control the erase, read, etc. operations of the non-volatile memory device 100.

The voltage generator 130 is controlled by the control logic circuit 120 and includes a selected word line, an unselected word line, a string select line SSL, a ground select line GSL, And generates voltages applied to a common source line (CSL). The voltage generator 130 may generate the program voltage Vpgm, the pass voltage Vpass, the read voltage Vread, the verify read voltage Vvfy, and the like.

The row decoder 140 is controlled by the control logic circuit 120 and is responsive to a row address to select selected and unselected word lines, a string select line SSL, a ground select line GSL, And the common source line CSL, respectively.

The row decoder 140 drives the lines using the voltages generated by the voltage generator 130. For example, during a program operation, the row decoder 140 may apply a program voltage Vpgm to a selected word line and apply a pass voltage Vpass to a non-selected word line.

The page buffer 150 operates as a sense amplifier or as a write driver. In a read operation, the page buffer 150 reads data from the memory cell array 110. Specifically, the page buffer 150 senses the bit line voltage and distinguishes the data according to the level of the bit line voltage. The separated data is stored in the page buffer 150.

In operation of the program, the page buffer 150 drives the bit lines to the power supply voltage Vcc or the ground voltage (0V), respectively, according to the data input through the column decoder 160. [ For example, a ground voltage will be applied to a bit line connected to a memory cell to be programmed, and a power supply voltage will be applied to a bit line connected to a memory cell not to be programmed. The principle in which the page buffer 150 operates as a sense amplifier or a write driver is well known to those skilled in the art, so that a description thereof will be omitted for the sake of brevity.

The column decoder 160, in response to a column address, reads the latched data into the page buffer 150 or passes the data to the page buffer 150. For example, the column decoder 160 may receive data from an external device (e.g., a host, etc.) and latch the input data in the page buffer 150 during a program operation.

2 is a detailed view of the memory cell array shown in FIG. Referring to FIG. 2, the memory cell array 110 includes a plurality of word lines WL1 to WLm, a plurality of bit lines BL1 to BLn, and a plurality of memory cells M1 to Mm. The word lines (WL1 to WLm) of the memory cell array (110) are connected to the row decoder (140).

The row decoder 140 is connected to the string selection line SSL, the word lines WL1 to WLm, the ground selection line GSL, and the common source line CSL. In this embodiment, the common source line CSL is driven by the row decoder 140, but it is needless to say that it may be driven by another device as needed. The row decoder 140 will select one or more of the plurality of word lines corresponding to the row address not shown.

The bit lines BL1 to BLn of the memory cell array 110 are connected to the page buffer 150. [ The page buffer 150 drives the bit lines BL1 to BLn. As an example, during a program operation, the page buffer 150 will apply a ground voltage (0 V) to the selected bit line and a program inhibit voltage Vcc to the unselected bit line.

3 is a diagram for explaining a programming method of a nonvolatile memory device according to the first embodiment of the present invention. Referring to Fig. 3, the case where the memory cell MC1 is exemplarily programmed and the memory cell MC2 is not programmed will be described. The memory cell MC1 is connected to the selected word line WL28 and the selected bit line BL1. The memory cell MC2 is connected to the selected word line WL28 and the non-selected bit line BL2.

When the memory cell MC1 is programmed, the memory cell MC2 should not be programmed. To prevent the memory cell MC2 from being programmed, the program inhibit voltage Vcc is applied to the non-selected bit line BL2.

In the present invention, a local self-boosting scheme is applied. In the program inhibition method using the local self-boosting scheme according to the present invention, a pass voltage Vpass is applied to unselected word lines WL26 and WL27 adjacent to the selected word line WL28.

The third local voltage and the second local voltage are applied to the unselected word lines WL24 and WL25 adjacent to the non-selected word lines WL26 and WL27, respectively. The magnitude of the second local voltage is greater than the third local voltage. For example, a voltage of 4V may be applied to the word line WL25 and a voltage of 2V may be applied to the word line WL24.

Under the aforementioned bias condition, the transistor MC3 connected to the unselected word line WL24 by the third local voltage is turned off. Thus, the channel is separated based on the transistor MC3. As the channel is separated, the boosting efficiency of the channel voltage is improved.

Also, the channel voltage is prevented from abruptly changing by applying the pass voltage to the unselected word lines WL26 and WL27 and applying the second local voltage to the unselected word line WL25. That is, by placing a gap between the selected word line WL28 and the word line WL25, problems due to abrupt boosting of the channel voltage can be prevented.

For example, when the channel voltage rises sharply, a problem such as a BTBT (Band To Band Tunneling) phenomenon may occur in the transistor MC3 for isolating the channel. The BTBT phenomenon must be avoided because it will program unselected transistors. The bias condition according to the present invention will be described in detail with reference to FIG. 4 to be described later.

However, the scope of the present invention is not limited to the above-described bias condition. For example, there may be no space between the selected word line WL28 and the word line WL25, or a plurality of word lines may be included between the selected word line WL28 and the word line WL25. Even in this case, the boosting efficiency is improved because the channel is separated.

4 is a timing chart for explaining a voltage applying method in a program operation according to the present invention. Referring to FIG. 4, the program operation according to the present invention is divided into steps t1 to t5. Step t1 is an initialization step, in which a ground voltage (0 V) is applied to each of the lines.

In step t2, the unselected word lines (Other WLs) and the selected word line (WL28) are driven with the pass voltage (Vpass). The non-selected word line (Other WLs) and the selected word line (WL28) will be turned on by the application of the pass voltage (Vpass). The second local voltage Vlocal2, which is lower than the pass voltage Vpass, is applied to the word line WL25.

A first local voltage Vlocal1 is applied to the word line WL24. As the word lines WL24 and WL25 are driven to the first local voltage Vlocal1 and the second local voltage Vlocal2, respectively, electrons in the channel will move. This will be described in detail with reference to FIG. 5 to be described later.

In step t3, the third local voltage Vlocal3 is applied to the word line WL24. Depending on the application of the third local voltage Vlocal3, the transistor connected to the word line WL24 will be turned off. Thus, the channel will be disconnected.

In step t4, the selected word line WL28 is driven by the program voltage Vpgm. The application of the program voltage Vpgm will increase the channel voltage. The memory cell MC2 unselected by the increased channel voltage will not be programmed. Step t5 is a recovery step, in which each line is driven to ground voltage (0V).

5 is a diagram for explaining the distribution of electrons in the channel in the period from t1 to t3 in Fig. 5 (a) shows the distribution of electrons in the channel in the t1 section. Referring to FIG. 5 (a), when no voltage is applied to the word lines WL24 and WL25, electrons in the channel are arranged at a constant density.

5 (b) shows the electron distribution in the channel in the t2 section. Referring to FIG. 5B, when a relatively high first local voltage Vlocal1 is applied to the word line WL24 and a second local voltage Vlocal2 which is relatively low is applied to the word line WL25, Are moved in the direction of the word line WL24. Thus, the channel of the transistor connected to the word line WL25 has a low electron density, and the channel of the transistor connected to the word line WL24 has a high electron density.

FIG. 5 (c) shows the electron distribution in the channel at the time t3. Referring to FIG. 5 (c), as the third local voltage Vlocal3 is applied to the word line WL24, the transistor is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel of the transistor connected to the word line WL25 is lowered.

When the electron density of the channel is low, the boosting efficiency of the channel voltage is increased. In the present invention, the self-boosting efficiency is increased by lowering the electron density of the channel corresponding to the selected word line.

6 is a diagram for explaining channel separation in the programming method according to the present invention. Referring to FIG. 6, the channel is separated as the transistor MC3 is turned off. e, the channel corresponding to the selected word line has a low electron density and the channel corresponding to the selected word line has a high electron density. . Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

7 is a diagram for explaining a programming method of a nonvolatile memory device according to the second embodiment of the present invention. Referring to Fig. 7, a case where the memory cell MC1 is exemplarily programmed and the memory cell MC2 is not programmed will be described. The memory cell MC1 is connected to the selected word line WL26 and the selected bit line BL1. The memory cell MC2 is connected to the selected word line WL26 and the non-selected bit line BL2.

When the memory cell MC1 is programmed, the memory cell MC2 should not be programmed. To prevent the memory cell MC2 from being programmed, the program inhibit voltage Vcc is applied to the non-selected bit line BL2.

In this embodiment, a local self-boosting scheme is applied. In the program inhibition method using the local self-boosting scheme according to the present invention, a pass voltage Vpass is applied to unselected word lines WL24 and WL25 adjacent to the selected word line WL26. The fifth local voltage Vlocal5 and the second local voltage Vlocal2 are applied to the unselected word lines WL22 and WL23 adjacent to the non-selected word lines WL24 and WL25, respectively. The magnitude of the second local voltage Vlocal2 is greater than the fifth local voltage Vlocal5. For example, a voltage of 4V may be applied to the word line WL23 and a voltage of 2V may be applied to the word line WL22.

The pass voltage Vpass is applied to the non-selected word lines WL27 and WL28 adjacent to the selected word line WL26. The fourth local voltage Vlocal4 and the sixth local voltage Vlocal6 are applied to the non-selected word lines WL29 and WL30 adjacent to the non-selected word lines WL27 and WL28, respectively. The magnitude of the fourth local voltage Vlocal4 is greater than the sixth local voltage Vlocal6. For example, a voltage of 4V may be applied to the word line WL29 and a voltage of 2V may be applied to the word line WL30.

Under the above-described bias condition, the transistor MC3 connected to the unselected word line by the fifth local voltage Vlocal5 is turned off. Thus, the channel is separated based on the transistor MC3. In addition, the transistor MC4 connected to the unselected word line by the sixth local voltage Vlocal6 is turned off. Thus, the channel is separated based on the transistor MC4.

In this embodiment, the pass voltage Vpass is applied to the unselected word lines and the second local voltage Vlocal2 and the fourth local voltage Vlocal4 are applied to the unselected word lines WL23 and WL29, So that the channel voltage is prevented from being abruptly changed. That is, by placing a gap between the selected word line WL26 and the word lines WL23 and WL29, problems due to abrupt boosting of the channel voltage can be prevented.

However, the scope of the present invention is not limited to the above-described bias condition. For example, there may be no gap between the selected word line WL26 and the word lines WL23 and WL29, or a plurality of word lines may be included between the selected word line WL26 and the word lines WL23 and WL29 have. Even in this case, the boosting efficiency is improved because the channel is separated.

8 is a timing chart for explaining a voltage applying method in a program operation according to the present invention. Referring to FIG. 8, the program operation is divided into steps t1 to t5. Step t1 is an initialization step, in which a ground voltage (0 V) is applied to each word line.

In the step t2, the unselected word lines Other WLs and the selected word line WL26 are driven with the pass voltage Vpass. By the application of the pass voltage Vpass, the transistors connected to the unselected word lines Other WLs and the selected word line WL26, respectively, will be turned on. The second local voltage Vlocal2 is applied to the word line WL23 and the fourth local voltage Vlocal4 is applied to the word line WL29.

The first local voltage Vlocal1 is applied to the word line WL22 and the third local voltage Vlocal3 is applied to the word line WL30. As the word lines WL22 and WL30 are respectively driven to the first local voltage Vlocal1 and the third local voltage Vlocal3, electrons in the channel will move. This will be described in detail with reference to FIG. 9 to be described later.

In step t3, the fifth local voltage Vlocal5 is applied to the word line WL22 and the sixth local voltage Vlocal6 is applied to the word line WL30. The transistor connected to the word line WL22 will be turned off according to the application of the fifth local voltage Vlocal5. Further, the transistor connected to the word line WL30 will be turned off according to the application of the sixth local voltage Vlocal6. Thus, the channel will be disconnected.

In step t4, the selected word line WL26 is driven by the program voltage Vpgm. The application of the program voltage Vpgm will increase the channel voltage. The memory cell MC3 not selected by the increased channel voltage will not be programmed. Step t5 is a recovery step, in which each line is driven to ground voltage (0V).

FIG. 9 is a diagram for explaining the distribution of electrons in the channel in the period from t1 to t3 in FIG. 8; FIG. Fig. 9 (a) shows the distribution of electrons in the channel in the section t1 in Fig. Referring to FIG. 9A, when no voltage is applied to the word lines WL22, WL23, WL29 and WL30, electrons in the channel are arranged at a constant density.

FIG. 9 (b) shows the distribution of electrons in the channel in the t2 section of FIG. Referring to FIG. 9 (b), a first local voltage Vlocal1 and a third local voltage Vlocal3, which are relatively high, are applied to the word lines WL22 and WL30, respectively.

As the second local voltage Vlocal1, which is relatively low, is applied to the word line WL23, the electrons move in the word line WL22 direction. Further, as the relatively low fourth local voltage Vlocal4 is applied to the word line WL29, the electrons move in the direction of the word line WL30. Thus, the channel of the transistors connected to the word lines WL23 and WL29 has a low electron density, and the channel of the transistors connected to the word lines WL22 and WL30 has a high electron density.

FIG. 9 (c) shows the electron distribution in the channel in the section t3 in FIG. Referring to FIG. 9 (c), as the fifth local voltage Vlocal5 is applied, the transistor connected to the word line WL22 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel of the transistor connected to the word line WL22 is lowered. In addition, as the sixth local voltage Vlocal6 is applied, the transistors connected to the word line WL30 are turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel of the transistor connected to the word line WL30 is lowered.

As the channel's electron density decreases, the boosting efficiency of the channel voltage increases. In the present invention, the self-boosting efficiency is increased by lowering the electron density of the channel corresponding to the selected word line.

10 is a diagram for explaining channel separation in the program method according to the present invention. Referring to FIG. 10, the channels are separated as the transistors MC3 and MC4 are turned off. In addition, the channel including the word line WL26 selected by the movement of the electrons described above has a low electron density, and the channel not including the selected word line WL26 has a high electron density, . Since the electron density of the channel including the selected word line WL26 is low, the boosting efficiency is improved.

11 is a timing chart for explaining a voltage applying method in a program operation according to the third embodiment of the present invention. Referring to FIG. 11, the program operation is divided into steps t1 to t5. Step t1 is an initialization step, in which a ground voltage (0 V) is applied to each of the lines.

In the step t2, the unselected word lines Other WLs and the selected word line WL26 are driven with the pass voltage Vpass. By the application of the pass voltage Vpass, the transistors connected to the unselected word lines Other WLs and the selected word line WL26, respectively, will be turned on. And the second local voltage Vlocal2 is applied to the word lines WL23 and WL29.

A first local voltage Vlocal1 higher than the second local voltage Vlocal2 is applied to the word lines WL22 and WL30. Electrons in the channel will move as the word lines WL22 and WL30, WL23 and WL29 are driven to the first local voltage Vlocal1 and the second local voltage Vlocal2, respectively.

In step t3, the third local voltage Vlocal3 is applied to the word lines WL22 and WL30. Depending on the application of the third local voltage Vlocal3, the transistors connected to the word lines WL22 and WL30 will be turned off. Thus, the channel will be disconnected. Further, a fourth local voltage Vlocal4 higher than the second local voltage Vlocal2 is applied to the word lines WL23 and WL29. The boosting efficiency of the channel will be improved according to the application of the fourth local voltage Vlocal4.

In step t4, the selected word line WL26 is driven by the program voltage Vpgm. The application of the program voltage Vpgm will increase the channel voltage. The memory cell MC2 unselected by the increased channel voltage will not be programmed. Step t5 is a recovery step, in which each line is driven to ground voltage (0V).

12 is a block diagram that schematically illustrates a computing system 200 including a non-volatile memory device in accordance with the present invention. 12, a computing system 200 includes a processor 210, a memory controller 220, input devices 230, output devices 240, a non-volatile memory device 250, 260). In the figure, a solid line indicates a system bus through which data or commands are transferred.

The memory controller 220 and the nonvolatile memory device 250 can constitute a memory card. The processor 210, the input devices 230, the output devices 240, and the main memory 260 may constitute a host using the memory card as a storage device.

The computing system 200 according to the present invention receives data from the outside through the input devices 230 (keyboard, camera, etc.). The input data may be a command by a user, or may be multimedia data such as image data by a camera or the like. The input data is stored in the non-volatile memory device 250 or the main memory 260. [

The processing result by the processor 210 is stored in the nonvolatile memory device 250 or the main memory 260. [ The output devices 240 output the data stored in the non-volatile memory device 250 or the main storage device 260. The output devices 240 output the digital data in a human-sensible form. For example, the output device 240 may include a display or a speaker. The programming method according to the present invention will be applied to the nonvolatile memory device 250. [ As the reliability of the non-volatile memory device 250 is improved, the reliability of the computing system 200 will also be improved accordingly.

The non-volatile memory device 250, and / or the memory controller 220 may be implemented using various types of packages. For example, the non-volatile memory device 250 and / or the controller 220 may be implemented as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline ), A Wafer-Level Processed Stack Package (WSP), and the like.

It will be apparent to those skilled in the art that a power supply is required to supply the power required for operation of the computing system 200, although it is not shown in the figures. In addition, when the computing system 200 is a mobile device, a battery for supplying operation power of the computing system 200 may be further required.

13 is a block diagram briefly showing a configuration of an SSD system including a nonvolatile memory device according to the present invention. Referring to FIG. 13, the SSD system 300 includes an SSD controller 310 and nonvolatile memory devices 320 to 323.

The nonvolatile memory device according to the present invention can also be applied to a solid state drive (SSD). SSD products, which are expected to replace hard disk drives (HDDs) in recent years, are getting attention in the next generation memory market. An SSD is a data storage device that uses memory chips, such as flash memory, to store data instead of a rotating disk used in a typical hard disk drive. SSDs are faster than mechanical moving hard disk drives, are more resistant to external shocks, and have lower power consumption.

Referring again to FIG. 13, the central processing unit 311 receives a command from the host and determines whether to store the data from the host in the nonvolatile memory device or read the stored data in the nonvolatile memory device and transmit the data to the host Respectively.

The ATA interface 312 exchanges data with the host side under the control of the central processing unit 311 described above. The ATA interface 312 fetches commands and addresses from the host side and transfers them to the central processing unit 311 via the CPU bus. Data input from the host via the ATA interface 312 or data to be transmitted to the host is transferred through the SRAM cache 313 without passing through the CPU bus under the control of the central processing unit 311. [ The ATA interface 212 includes a serial ATA (S-ATA) standard and a parallel ATA (P-ATA) standard.

The SRAM cache 313 temporarily stores movement data between the host and the nonvolatile memory devices 320 to 323. The SRAM cache 313 is also used to store a program to be operated by the central processing unit 311. [ The SRAM cache 313 can be regarded as a kind of buffer memory, and it is not necessarily configured as an SRAM. The flash interface 314 exchanges data with nonvolatile memories used as storage devices. The flash interface 314 may be configured to support NAND flash memory, One-NAND flash memory, or multi-level flash memory.

The semiconductor memory system according to the present invention can be used as a portable storage device. Therefore, it can be used as a storage device of MP3, digital camera, PDA, e-Book. It can also be used as a storage device such as a digital TV or a computer.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 is a block diagram illustrating a non-volatile memory device in accordance with the present invention.

2 is a detailed view of the memory cell array shown in FIG.

3 is a diagram for explaining a programming method of a nonvolatile memory device according to the first embodiment of the present invention.

4 is a timing chart for explaining a voltage applying method in a program operation according to the present invention.

5 is a diagram for explaining the distribution of electrons in the channel in the period from t1 to t3 in Fig.

6 is a diagram for explaining channel separation in the programming method according to the present invention.

7 is a diagram for explaining a programming method of a nonvolatile memory device according to the second embodiment of the present invention.

8 is a timing chart for explaining a voltage applying method in a program operation according to the present invention.

FIG. 9 is a diagram for explaining the distribution of electrons in the channel in the period from t1 to t3 in FIG. 8; FIG.

10 is a diagram for explaining channel separation in the program method according to the present invention.

11 is a timing chart for explaining a voltage application method in a program operation according to the third embodiment of the present invention.

12 is a block diagram that schematically illustrates a computing system 200 including a non-volatile memory device in accordance with the present invention.

13 is a block diagram briefly showing a configuration of an SSD system including a nonvolatile memory device according to the present invention.

Claims (8)

A program method for a nonvolatile memory device, Driving a first word line to a first local voltage and driving a second word line between the first word line and a selected word line to a second local voltage lower than the first local voltage; And And driving the first word line to a third local voltage lower than the second local voltage after the second word line is driven to the second local voltage. The method according to claim 1, And driving the selected word line to a program voltage after driving the first word line to the third local voltage. The method according to claim 1, And the cell transistor connected to the first word line is turned off by the application of the third local voltage. The method according to claim 1, Driving one or more non-selected word lines located between the second word line and the selected word line to a pass voltage higher than the second local voltage before the selected word line is driven to a program voltage How to program. The method according to claim 1, And driving the second word line to a fourth local voltage higher than the second local voltage after driving the second word line to the second local voltage. A program method for a nonvolatile memory device, Driving a first word line to a first local voltage, driving a second word line between the first word line and a selected word line to a second local voltage lower than the first local voltage, Driving at a third local voltage a fourth word line between the third word line and the selected word line to a fourth local voltage lower than the third local voltage; Driving the first word line to a fifth local voltage lower than the second local voltage after the second word line is driven to the second local voltage and driving the fourth word line to the fourth local voltage Driving the third word line to a sixth local voltage lower than the fourth local voltage; And Driving the selected word line to a program voltage after the first word line is driven to the fifth local voltage and after the third word line is driven to the sixth local voltage, Wherein the selected word line is located between the second word line and the fourth word line. The method according to claim 6, The cell transistor connected to the first word line is turned off by the application of the fifth local voltage and the cell transistor connected to the third word line is turned off by application of the sixth local voltage. Way. The method according to claim 6, Driving one or more non-selected word lines located between the second word line and the selected word line to a pass voltage higher than the second local voltage before the selected word line is driven to a program voltage, Driving one or more non-selected word lines located between the line and the selected word line to the pass voltage higher than the fourth local voltage.

Images