KR20100113735A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20100113735A
KR20100113735A KR1020090032187A KR20090032187A KR20100113735A KR 20100113735 A KR20100113735 A KR 20100113735A KR 1020090032187 A KR1020090032187 A KR 1020090032187A KR 20090032187 A KR20090032187 A KR 20090032187A KR 20100113735 A KR20100113735 A KR 20100113735A
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KR
South Korea
Prior art keywords
device isolation
gate
forming
trench
film
Prior art date
Application number
KR1020090032187A
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Korean (ko)
Inventor
김민수
양홍선
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090032187A priority Critical patent/KR20100113735A/en
Publication of KR20100113735A publication Critical patent/KR20100113735A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678—Beam shaping, e.g. using a mask
    • H01L21/0268—Shape of mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention is to provide a method for manufacturing a semiconductor device for preventing a short between the gate electrode and the source / drain, the present invention is to separate the device in the device isolation region of the substrate having an active region and device isolation region Forming a trench for forming a device, forming a first insulating film for device isolation in a device isolation trench, forming a trench in the first insulating film for device isolation with an etching barrier using a mask pattern covering a gate predetermined region; Forming an etch stop film on the trench surface, embedding a second insulating film for device isolation in the trench, etching the first insulating film for device isolation in the gate predetermined region, and protruding the active region in the form of a fin; It provides a method for manufacturing a semiconductor device comprising the step of forming a gate in the gate predetermined region.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device using a three-dimensional gate process.

As semiconductor devices become highly integrated, planar gate processes that form gates on planar active regions reduce the gate channel length and increase the implant doping concentration. Junction leakage occurs due to an increase in the electric field, making it difficult to secure refresh characteristics of the device.

To overcome this limitation, a three-dimensional gate process has been introduced that forms gates on three-dimensional active regions.

In the three-dimensional gate process, a recess gate process of recessing an active region of a region where a gate is to be formed and forming a gate thereon, and recessing the device isolation layer to form an active region in a fin form A fin gate process that protrudes and forms a gate thereon, and a saddle gate process that combines a recess gate process and a fin gate process are used.

By using the three-dimensional gate process, the gate channel length can be increased, and the ion implantation doping concentration can be reduced, thereby greatly improving the refresh characteristics of the device.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art to which a three-dimensional gate process is applied will be described with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and show a case in which DRAM is manufactured using a saddle gate process.

1A to 1E, (a) shows a cross-sectional view cut in the direction perpendicular to the gate line, and (B) shows a cross-sectional view cut in the gate line direction.

As shown in FIG. 1A, a trench for device isolation is formed in the substrate 10 and an oxide film is embedded in the trench for device isolation to form a trench device isolation film 11. As a result, the active region 10A is defined.

Subsequently, a mask pattern 12 that opens a portion where a gate is to be formed (hereinafter, referred to as a “gate predetermined region”) is formed. The space CD W1 between the mask patterns 12 is the same as the gate CD formed thereafter.

Then, the recess 13A is formed by etching the active region 10A of the substrate 10 using the mask pattern 12 as an etch barrier.

When the active region 10A is etched, the device isolation layer 11 exposed by the mask pattern 12 is also etched to form a recess 13B in the device isolation layer 11.

As shown in FIG. 1B, the device isolation layer 11 is etched using the mask pattern 12 as an etch barrier to form a saddle type fin 14.

During the etching process, the etch selectivity between the oxide film and the silicon film is as high as possible so that only the device isolation film 11 made of the oxide film is selectively etched. This is because the mask pattern 12 has a structure in which not only the device isolation layer 11 but also the substrate 10 of the active region 10A is opened, thereby etching only the device isolation layer 11 while minimizing the etching of the substrate 10. to be.

During the etching process for forming the saddle-shaped fins 14, the device isolation layer 11 is etched not only in a direction perpendicular to the main surface of the substrate 10 but also in a horizontal direction. The top CD (Top Critical Dimension, W2) of the recess 13B formed is larger than the space CD W1 between the mask patterns 12 (W2 > W1).

As shown in FIG. 1C, the mask pattern 12 is removed, the gate insulating film 15 is formed along the surface curvature on the resultant, and then the polysilicon film 16 is formed as the gate electrode material on the gate insulating film 15. ) And the barrier metal film 17 and the metal film or silicide film 18 are laminated.

Next, the gate hard mask film 19 and the photoresist pattern 20 covering the gate predetermined region are laminated on the metal film or the silicide film 18.

As shown in FIG. 1D, the gate hard mask film 19, the metal film or the silicide film 18, the barrier metal film 17, the polysilicon film 16, and the gate insulating film using the photoresist pattern 20 as a mask. The gate 15 is formed by etching (15).

Then, the remaining photoresist pattern 20 is removed, gate spacers 21 are formed on both sides of the gate G, and then the source / drain is formed in the active region 10A of the substrate 10 on both sides of the gate G. (Not shown) is formed.

As shown in FIG. 1E, a conductive film is filled in the space between the gates G to which the insulating film spacer 21 is attached to form a contact 22 connected to the source / drain.

However, the above-described conventional technology has a problem in that the source / drain and the gate G are shorted.

More specifically, in the process illustrated in FIG. 1B, a recess 13B is formed in the device isolation film 11 as the device isolation film 11 is etched not only in the direction perpendicular to the main surface of the substrate 10 but also in the horizontal direction. Top CD W2 becomes larger than gate G CD W1 (W2 > W1). As a result, as shown in FIG. 1E, the gate G filled in the recess 13B and the adjacent contact 22 are electrically connected, and the gate G and the source / drain are shorted through the contact 22. ) Will cause a defect.

Meanwhile, in order to overcome limitations due to integration and improve gate performance, the height of the saddle-type fin 14 must be increased by increasing the etching thickness D of the device isolation layer 11 in the process of FIG. 1B. However, when the etching thickness D of the device isolation layer 11 is increased, the gate G and the source / drain may be shorted as described above. Thus, the etching thickness D of the device isolation layer 11 may be lower than a predetermined level. As a result, it is difficult to secure the gate performance because the height of the saddle-shaped fin 14 cannot be increased.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device for preventing a short between a gate and a source / drain.

Another object of the present invention is to provide a method of manufacturing a semiconductor device for improving the gate performance.

According to an aspect of the present invention, there is provided a device isolation trench in the device isolation region of a substrate having an active region and a device isolation region, and a device isolation agent in the device isolation trench. Forming an insulating film, forming a trench in the first insulating film for device isolation using an mask barrier covering a gate predetermined region, forming an etch stop film on the trench surface, and forming a trench in the trench Filling the second insulating layer for device isolation, etching the first insulating layer for the device isolation region to protrude the active region in the form of a fin, and forming a gate in the gate predetermined region; It provides a method of manufacturing a semiconductor device comprising.

According to the present invention, since the etch stop layer is formed on the device isolation layer below the gate edge and the horizontal etching is suppressed by the etch stop layer during the device isolation film etching process for forming the saddle fin, the top CD of the recess formed in the device isolation film Is not increased. Therefore, the gate filled in the recess formed in the device isolation layer and the adjacent contact are not electrically connected, thereby preventing the source / drain connected to the gate and the contact from being shorted.

In addition, since the horizontal etching of the device isolation layer which causes the short between the gate and the source / drain is suppressed, the etching thickness of the device isolation layer may be increased. Therefore, it is possible to increase the height of the saddle fin to overcome the limitations of integration and to improve gate performance.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A through 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and show a case in which DRAM is manufactured using a saddle gate process.

2A to 2J, (a) shows a cross section cut in the direction perpendicular to the gate line, and (B) shows a cross section cut in the gate line direction.

As shown in FIG. 2A, an isolation region trench is formed in the substrate 30 to define the active region 30A. Subsequently, the first insulating layer 31 for device isolation is formed on the entire surface including the device isolation trench. An oxide film may be used as the first insulating film 31 for element isolation.

The device isolation first insulating layer 31 is formed to a sufficient thickness so as to fill the device isolation trench and to be stacked on the surface of the substrate 30 of the active region 10A by a predetermined thickness or more.

Subsequently, a planarization process may be further performed to planarize the first insulating layer 31 for device isolation. As a planarization process, a chemical mechanical polishing process may be used.

As shown in FIG. 2B, the first mask pattern 32 covering the gate predetermined region is formed on the first insulating layer 31 for device isolation.

As the first mask pattern 32, a structure in which a pad insulating film, a hard mask film, and a photoresist film are stacked may be used. The CD W1 of the first mask pattern 31 is the same as the gate CD formed thereafter.

Then, the trench 33 is formed by etching the first insulating layer 31 for device isolation using the first mask pattern 32 as an etch barrier.

When the trench 33 is etched, the etch selectivity between the insulating film and the silicon film is as high as possible to selectively etch only the first insulating film 31 for device isolation. This is because the first mask pattern 32 has a structure in which not only the first insulating layer 31 for device isolation but also the substrate 30 in the active region 30A is opened, thereby minimizing etching of the substrate 30. This is to etch only the first insulating film 31.

As shown in FIG. 2C, the first mask pattern 32 is removed and the etch stop layer 34 is formed along the surface curvature on the resultant.

As the etch stop layer 34, a material having an etch selectivity with a first insulating layer 31 for device isolation is used. For example, a nitride film may be used as the etch stop film 34.

As shown in FIG. 2D, the second insulating layer 35 for device isolation is formed on the entire surface including the trench 24. An oxide film may be used as the second insulating film 35 for device isolation.

The second insulating layer 35 for device isolation is formed to a sufficient thickness to fill the trench 33 and to be stacked over a predetermined thickness on the active region 10A.

As illustrated in FIG. 2E, the second and first insulating layers 35 and 31 and the etch stop layer 34, which are formed outside the device isolation trench, are removed.

For this purpose, the planarization process may be performed to expose the substrate 10 of the active region 10A. As the planarization process, a chemical mechanical polishing process may be used.

As shown in FIG. 2F, a second mask pattern 36 is formed on the resultant to open the gate predetermined region.

As the second mask pattern 36, a structure in which a pad insulating film, a hard mask film, and a photoresist film are stacked may be used. The space CD W1 between the second mask patterns 36 is the same as the gate CD formed thereafter.

Then, the recess 37A is formed by etching the active region 30A of the substrate 30 using the second mask pattern 36 as an etch barrier.

During the etching process, the first insulating layer 31 for device isolation exposed by the second mask pattern 36 is also etched to form a recess 37B in the first insulating layer 31 for device isolation.

As shown in FIG. 2G, the saddle-shaped fin 38 is formed by etching the first insulating layer 31 for device isolation using the second mask pattern 36 as an etch barrier. As a result of this process, the depth of the recess 37B formed in the first insulating film 31 for element isolation is further deepened.

During the etching process, the etch selectivity between the first insulating layer 31 and the substrate 30 for device isolation is as high as possible to selectively etch only the first insulating layer 31 for device isolation. This is because the second mask pattern 36 has a structure for opening the substrate 30 of the active region 30A as well as the first insulating layer 31 for device isolation, thereby minimizing etching of the substrate 30. This is to etch only the first insulating film 31.

During the etching process, since the etching in the horizontal direction is prevented by the etch stop film 34, the top CD of the recess 37B is not increased. That is, the top CD of the recess 37B is kept at W1 in the same manner as the space CD between the second mask patterns 36.

As shown in FIG. 2H, the second mask pattern 36 is removed and the gate insulating film 39 is formed along the surface curvature on the resultant, and the polysilicon film 40 is formed as the gate electrode material on the gate insulating film 39. ) And the barrier metal film 41 and the metal film or silicide film 42 are laminated.

Next, the gate hard mask film 43 and the photoresist pattern 44 covering the gate predetermined region are stacked on the metal film or the silicide film 42.

The CD of the photoresist pattern 44 is W1, which is the same as the gate CD formed later.

As shown in FIG. 2I, the gate hard mask film 43, the metal film or the silicide film 42, the barrier metal film 41, the polysilicon film 40, and the gate insulating film using the photoresist pattern 44 as a mask. The gate 39 is formed by etching 39.

Then, the remaining photoresist pattern 44 is removed, and gate spacers 45 are formed on both sides of the gate G.

Subsequently, a source / drain (not shown) is formed in the active region 30A of the substrate 30 on both sides of the gate G.

As illustrated in FIG. 2J, a conductive film is embedded in the space between the gates G to which the gate spacers 45 are attached to form a contact 46 connected to the source / drain.

In the present invention as described above, the etch stop layer 34 is formed inside the device isolation structure under the edge of the gate G so that the first insulating film 31 for device isolation during the etching process of the first insulating film 31 for device isolation illustrated in FIG. 2G. Horizontal etching of 31 is prevented.

Therefore, since the top CD of the recess 37B formed in the element isolation first insulating film 31 does not increase, electrical connection is generated between the gate G filled in the recess 37B and the adjacent contact 46. Therefore, the problem of shorting the source / drain connected to the gate G and the contact 46 is prevented.

In addition, during the etching process of the first insulating layer 31 for device isolation shown in FIG. 2G, the horizontal etching of the first insulating layer 31 for device isolation, which causes a short between the gate G and the source / drain, is prevented. The height of the saddle fin 38 may be increased by increasing the etching thickness of the first insulating layer 31 for device isolation. Therefore, it is possible to overcome the limitations of integration and to improve gate performance.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the present invention has been described in the case of applying the saddle gate process, but in addition to the saddle gate process, it is applied to all semiconductor device fabrication processes including etching the device isolation film in the gate predetermined region, such as the pin gate process. It is possible.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A through 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Description of the Related Art

30: substrate

30A: active area

31, 35: first and second insulating film for device isolation

32, 36: first and second mask pattern

33: trench

34: etch stop

37A, 37B: recess

38: Saddle Pin

G: Gate

46: contact

Claims (8)

Forming a device isolation trench in the device isolation region of the substrate having an active region and a device isolation region; Forming a first insulating film for device isolation in the device isolation trench; Forming a trench in the first insulating layer for device isolation using an etching barrier using a mask pattern covering a gate predetermined region; Forming an etch stop layer on the trench surface; Filling a second insulating film for device isolation into the trench; Etching the first insulating layer for device isolation in the gate predetermined region to protrude the active region in the form of a fin; Forming a gate in the gate predetermined area Method of manufacturing a semiconductor device comprising a. The method of claim 1, Before etching the first insulating film for device isolation of the gate predetermined region, And forming a recess by etching the substrate of the active region of the gate predetermined region. The method of claim 1, And forming the device isolation first insulating layer so as to fill the device isolation trench and to be stacked on the substrate in the active region with a predetermined thickness. The method of claim 1, And forming the etch stop layer on the entire surface including the trench. The method of claim 1, And forming the second insulating layer for isolation of the device so as to fill the trench and be stacked on the etch stop layer to a predetermined thickness. The method according to any one of claims 3 to 5, And forming the device isolation second insulating film, and then removing the device isolation second and first insulation films and the etch stop film formed outside the device isolation trench. The method of claim 1, And forming the etching stop film as an insulating film having an etch selectivity with the first insulating film for device isolation. The method of claim 7, wherein A method of manufacturing a semiconductor device, wherein the device isolation first insulating film is formed of an oxide film, and the etch stop film is formed of a nitride film.
KR1020090032187A 2009-04-14 2009-04-14 Method for fabricating semiconductor device KR20100113735A (en)

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