KR20100111009A - Method of operating a non volatile memory device - Google Patents

Method of operating a non volatile memory device Download PDF

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Publication number
KR20100111009A
KR20100111009A KR1020090029357A KR20090029357A KR20100111009A KR 20100111009 A KR20100111009 A KR 20100111009A KR 1020090029357 A KR1020090029357 A KR 1020090029357A KR 20090029357 A KR20090029357 A KR 20090029357A KR 20100111009 A KR20100111009 A KR 20100111009A
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KR
South Korea
Prior art keywords
read
voltage
data
word line
memory device
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Application number
KR1020090029357A
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Korean (ko)
Inventor
강태규
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090029357A priority Critical patent/KR20100111009A/en
Publication of KR20100111009A publication Critical patent/KR20100111009A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

The present invention provides a method for manufacturing a nonvolatile memory device, comprising: providing a nonvolatile memory device including memory cells connected to a plurality of word lines and bit lines; A program step of programming first and second word lines selected according to the instruction set input; A first data reading step of applying a start read voltage included in the instruction set to the first word line, applying a pass voltage to the remaining word lines to perform data reading, and storing the read result; Read whether the read voltage applied to the first word line is the highest read voltage included in the command set, and read out the read set included in the command set until the read voltage applied to the first word line becomes the highest read voltage. A second data reading step of repeating reading the data of the first word line by increasing the read voltage by the step voltage and storing the read data; And determining a threshold voltage distribution using the read data stored in the first and second data reading steps after performing the first and second data reading steps on the second word line. It provides a method of operating the device.

Description

Method of operating a non volatile memory device

The present invention relates to the operation of a nonvolatile memory device with respect to providing the word line voltage during a program operation of the nonvolatile memory device.

There is an increasing demand for nonvolatile memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. A nonvolatile memory device includes a plurality of memory cells connected in series to form a string, and the plurality of strings include a memory cell array.

The threshold voltages of memory cells of the nonvolatile memory device vary according to program states. Ideally, the threshold voltage of each memory cell should have the same threshold voltage according to the state of data to be stored. However, when the actual memory cells are programmed, they are probabilistically distributed in each region by various external environments such as device characteristics and coupling effects of the memory cells.

Computing and understanding this probability distribution allows us to verify that the actual memory device was programmed with the correct threshold voltage after programming.

In addition, the reliability of the data can be improved by setting the data read voltage or the pass voltage having the least error through the threshold voltage distribution verification.

Accordingly, an aspect of the present invention is to provide a method of operating a nonvolatile memory device that provides threshold voltage distribution data by measuring threshold voltage distributions of memory cells connected to one or more selected word lines.

Method of operation of a nonvolatile memory device according to the present invention,

Providing a nonvolatile memory device including memory cells connected to a plurality of word lines and bit lines; A program step of programming first and second word lines selected according to the instruction set input; A first data reading step of applying a start read voltage included in the instruction set to the first word line, applying a pass voltage to the remaining word lines to perform data reading, and storing the read result; Read whether the read voltage applied to the first word line is the highest read voltage included in the command set, and read out the read set included in the command set until the read voltage applied to the first word line becomes the highest read voltage. A second data reading step of repeating reading the data of the first word line by increasing the read voltage by the step voltage and storing the read data; And after performing the first and second data read steps with respect to the second word line, identifying a threshold voltage distribution using the read data stored in the first and second data read steps.

In the program step, the program in the Increment Step Pulse Program (ISPP) method, characterized in that to perform the verification.

When the start pass voltage, the end pass voltage, and the pass step voltage information of the pass voltage are included in the command set, each of the read voltages for performing the data read is applied to the remaining word lines except for the first word line. The data is read out while the pass voltage is changed.

Setting a read voltage at which a data read error does not occur according to the threshold voltage distribution; And using the set read voltage in a subsequent data read operation.

Identifying threshold voltage distributions using data read as the pass voltage is changed; And determining a pass voltage having the least error in data read by the threshold voltage distribution, and setting the pass voltage in a subsequent data read operation.

The method may further include outputting the threshold voltage distribution information, and outputting the threshold voltage distribution information.

The instruction set includes instructions for confirming a threshold voltage distribution, the first and second word line address information, the start read voltage and the highest read voltage and read step voltage information, and the pass voltage information.

As described above, in the method of operating a nonvolatile memory device according to the present invention, a threshold voltage distribution of a memory cell is measured to set a data read voltage or a pass voltage according to an interference degree or a difference. It can increase the reliability.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 illustrates a threshold voltage distribution when programming memory cells capable of storing 3-bit data.

Referring to FIG. 1, a nonvolatile memory device including a multi level cell capable of storing three bits of data in one memory cell includes three logical pages in one physical page. Each logical page may be divided into a Least Significant Bit (LSB) page, a Center Significant Bit (CBS), and a Most Significant Bit (MSB) page.

According to the characteristics of the nonvolatile memory device, the program is performed in units of pages. Therefore, as shown in FIG. 1, the number of threshold voltage distributions of the memory cells increases according to the LSB page, CSB page, and MSB page programs. As shown in FIG. 3, as the program proceeds to the upper page, the interval between the threshold voltage distributions becomes narrower.

As the memory cells are ideally programmed, the width of the threshold voltage distribution becomes narrower. As the width of the threshold voltage distribution becomes narrower, the distance from the adjacent threshold voltage distribution becomes relatively wider, thereby reducing errors when reading data, thereby increasing reliability.

However, as the actual program proceeds, the process of setting the read voltage has an important effect on the reliability of data because the threshold voltage distribution becomes wider and the margin, which is the interval between neighboring threshold voltages, can be narrowed.

Therefore, in the exemplary embodiment of the present invention, the actual threshold voltage distribution is determined using programmed memory cells, and a read voltage or a pass voltage with less error is set according to the read margin.

2 illustrates a nonvolatile memory device according to an embodiment of the present invention.

2, a nonvolatile memory device 200 according to an embodiment of the present invention may include a memory cell array 210, a page buffer unit 220, an X decoder 230, a voltage providing unit 240, and a controller ( 250).

The memory cell array 210 includes memory blocks composed of memory cells capable of storing one or more bits of data. The memory blocks are composed of a plurality of cell strings.

Each of the cell strings may be connected in series with a 0 th to 31 th memory cell C0 to C31 between a drain select transistor (DST) and a source select transistor (SST).

The gate of the drain select transistor is connected to a drain select line (DSL), and the gate of the source select transistor is connected to a source select line (SSL). The gates of the 0th to 31st memory cells C0 to C31 are connected to the 0th to 31st word lines WL0 to WL31, respectively.

A bit line is connected to the drain terminal of the drain select transistor, and a source terminal of the source select transistor is connected to a common source line SL.

The page buffer unit 220 includes page buffers PBs. Each page buffer PB is connected to one or more bit lines. The page buffer PB temporarily stores data to be programmed in a memory cell through a selected bit line, or reads and stores data stored in a memory cell connected to the selected bit line.

The X decoder 230 selects and enables a memory block in the memory cell array 210.

The voltage provider 240 generates and provides an operating voltage for a program, data read or erase operation. The voltage provider 240 includes a program voltage provider 241, a pass voltage provider 242, and a read voltage provider 243. The voltage providing unit 240 of FIG. 2 shows only some components necessary for the embodiment of the present invention.

The controller 250 programs the word lines selected by the test command, checks the threshold voltage of the memory cell while changing the set read voltage or the pass voltage, and controls to set the read voltage or the pass voltage having the least error.

The nonvolatile memory device 200 according to an embodiment of the present invention programs one or more word lines selected by an address input together with a test command. The threshold voltage distributions under various read voltage or pass voltage conditions are checked using the read voltage range and the pass voltage range input to the programmed word line together with the test command. In addition, the threshold voltage distribution is used to set a read voltage or a pass voltage that generates less error so that it can be applied to subsequent operations. The algorithm for this is stored in a storage unit included in the controller 250.

In addition, the read voltage or the pass voltage determined through the test is set as option information and stored in a fuse or a separate storage means, and is loaded when the nonvolatile memory device 200 starts operation and used as option information for operation.

3 is a flowchart illustrating an operation of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, an address and voltage information to be tested together with a test command are input to the nonvolatile memory device 200 according to an embodiment of the present invention in order to check the threshold voltage distribution and set the voltage (S301). .

The address includes address information of a word line for performing a test to confirm a threshold voltage distribution, and the word line includes one or more.

The voltage information includes read voltage range for checking threshold voltage distribution, step voltage size of read voltage, and pass voltage information. If the threshold voltage is to be measured while changing the pass voltage, the pass voltage range is included.

In the description of the embodiment of the present invention, the address information includes only one word line information in the 25th word line WL25. The range of the read voltage included in the voltage information is 0V to 3V, and the step voltage of the read voltage is aV. The pass voltage is fixed at 6V.

In response to the above command, the controller 250 selects the 25 th word line WL25 corresponding to the address information, and performs a program and verification (S303). When the program is performed, the program voltage increases the program voltage by the program step voltage whenever the program pulse is applied from the program start voltage basically set in the nonvolatile memory device 200.

When the program is completed, the operation for checking the threshold voltage starts.

First, 0V is applied to the word line where the program is performed (S305). The pass voltage is applied to the remaining word lines. The data read operation is performed to store the result (S307). Storing the result is to provide the read data stored in the page buffer PB to the controller 250 to store the data state when the read voltage is 0V.

After storing the read result, it is checked whether the voltage of the twenty-fifth word line WL25 that is currently performing the read operation becomes 3V, the highest read voltage Vmax (S309). If the voltage is not 3V, the read voltage is increased by aV, which is the read step voltage (S311), and data reading and result storage are performed (S307).

If the voltage of the 25th word line WL25 becomes 3V while repeating the process of reading data while increasing the read voltage by the read step voltage as described above and storing the result (S309), the read result stored so far is used. Check and analyze the threshold voltage distribution (S313).

The threshold voltage distribution is formed by graphing the number of memory cells programmed for each threshold voltage, and the threshold voltage distribution in step S313 represents only the threshold voltage distribution of the memory cells connected to the 25 th word line WL25.

The number of memory cells in which an error occurs with respect to the read voltage set as a default in the threshold voltage distribution can be checked. In addition, by changing the read voltage, the data error may be adjusted (S315).

The read voltage may be set as follows.

4 shows an example of threshold voltage distribution for explaining an embodiment of the present invention.

Referring to FIG. 4, when data is read from the memory cells having the threshold voltage distribution identified in step S313 using the first voltage R1, the data of the memory cells belonging to the threshold voltage distribution left to the left from the first voltage R1 is read. Is read incorrectly.

Therefore, the read voltage is changed to the second voltage R2 so that there is no data to be read.

On the other hand, the control unit 250 may output the threshold voltage distribution information to the outside by an output command input from the outside (S317) (S319). The threshold voltage distribution may be output to the outside and used for characteristic analysis of the nonvolatile memory device 200.

If there is two word line information in the address information input together with the command, the two word lines are programmed one after another, and the thresholds of the memory cells connected to the two word lines are repeated by performing steps S305 to S306 one by one. Find the voltage distribution.

In another embodiment, after the read voltage is fixedly set, the pass voltage is changed to a predetermined voltage range to read data, and the pass voltage for which the data read error is least generated by the threshold voltage distribution of the read data is set. It may be.

In this way, the actual threshold voltage distribution is confirmed through a test, and then a read voltage or a pass voltage is set to increase reliability in subsequent data reads.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 illustrates a threshold voltage distribution when programming memory cells capable of storing 3-bit data.

2 illustrates a nonvolatile memory device according to an embodiment of the present invention.

3 is a flowchart illustrating an operation of a nonvolatile memory device according to an embodiment of the present invention.

4 shows an example of threshold voltage distribution for explaining an embodiment of the present invention.

* Brief description of the main parts of the drawings *

200: nonvolatile memory device 210: memory cell array

220: page buffer unit 230: X decoder

240: voltage providing unit 250: control unit

Claims (7)

Providing a nonvolatile memory device including memory cells connected to a plurality of word lines and bit lines; A program step of programming first and second word lines selected according to the instruction set input; A first data reading step of applying a start read voltage included in the instruction set to the first word line, applying a pass voltage to the remaining word lines to perform data reading, and storing the read result; Read whether the read voltage applied to the first word line is the highest read voltage included in the command set, and read out the read set included in the command set until the read voltage applied to the first word line becomes the highest read voltage. A second data reading step of repeating reading the data of the first word line by increasing the read voltage by the step voltage and storing the read data; And Confirming a threshold voltage distribution using read data stored in the first and second data reading steps after performing the first and second data reading steps on the second word line. Method of operating a nonvolatile memory device comprising a. The method of claim 1, In the program step, A method of operating a nonvolatile memory device, wherein the program is performed by an incremental step pulse program (ISPP) method and verification is performed. The method of claim 1, When the start pass voltage, the end pass voltage, and the pass step voltage information of the pass voltage are included in the command set, each of the read voltages for performing the data read is applied to the remaining word lines except for the first word line. A method of operating a nonvolatile memory device, comprising: reading data while changing a pass voltage. The method of claim 1, Setting a read voltage at which a data read error does not occur according to the threshold voltage distribution; And Using the set read voltage in a subsequent data read operation. Method of operating a nonvolatile memory device comprising a. The method of claim 3, wherein Identifying threshold voltage distributions using data read as the pass voltage is changed; And Confirming a pass voltage having the least error in data read by the threshold voltage distribution, and setting the pass voltage in a subsequent data read operation Method of operating a nonvolatile memory device comprising a. The method of claim 1, And a step of outputting the threshold voltage distribution information, and outputting the threshold voltage distribution information. The method of claim 1, The instruction set is Command to check threshold voltage distribution, The first and second word line address information, The start read voltage and the highest read voltage and read step voltage information, and The pass voltage information Method of operating a nonvolatile memory device comprising a.
KR1020090029357A 2009-04-06 2009-04-06 Method of operating a non volatile memory device KR20100111009A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9502127B2 (en) 2015-03-17 2016-11-22 Sk Hynix Memory Solutions Inc. System optimization in flash memories

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9502127B2 (en) 2015-03-17 2016-11-22 Sk Hynix Memory Solutions Inc. System optimization in flash memories

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