KR20100111005A - Method of testing a non volatile memory device - Google Patents

Abstract

PURPOSE: A method of testing a non volatile memory device is provided to reduce a test time of deciding a bad block by testing the memory by a block unit. CONSTITUTION: A memory cell array(110) comprises a plurality of cell strings. Strings are connected to the bit line(BL). A page buffer unit(120) comprises a plurality of page buffers(121). An Y decoder(130) provides the input/output path to the page buffer of the page buffer unit. According to the input address, an X decoder(140) selects the word line of the memory cell array.

Description

Method of testing a non volatile memory device

The present invention relates to a block test method for a nonvolatile memory device.

Flash memory, which is a nonvolatile memory, is generally classified into a NAND flash memory and a NOR flash memory. NOR flash memory has a good random access time characteristic because memory cells are independently connected to bit lines and word lines, whereas NAND flash memory has a plurality of memory cells connected in series so that one contact per cell string is provided. Since only requires, it has excellent characteristics in terms of integration degree. Therefore, a NAND structure is mainly used for highly integrated flash memory.

Well known NAND flash memory devices include memory cell arrays, row decoders, and page buffers. The memory cell array includes a plurality of word lines extending along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

In the operation of programming data into a memory cell of a nonvolatile memory device, a verification process for confirming whether a program is programmed is one of important processes. Therefore, reducing the time spent on the verification process is an important issue to reduce the overall program time.

The nonvolatile memory device includes memory blocks including memory cells. In addition, memory cells are connected to word lines and bit lines.

Each of the bit lines is connected to a memory cell string, which is composed of a plurality of memory cells connected in series. Therefore, if one memory cell fails in the cell string, the operation of other memory cells may be affected.

In order to prevent the remaining memory cells connected to the entire cell string due to the failed memory cell from malfunctioning, the reliability of data is deteriorated, so that the cell string to which at least one failed memory cell is connected is replaced with another cell string. This is called repair.

For repair, the nonvolatile memory device has an extra redundancy cell string. However, since the number of redundancy cell strings is limited, repair can no longer be performed when a cell string fails more than a predetermined number for each memory block. In this case, the corresponding memory block is bad-blocked.

In order to bad block the memory block, a test is required to determine the number of cell strings in which a fail has occurred.

Accordingly, an aspect of the present invention is to provide a test method for a nonvolatile memory device capable of shortening a test time for determining a bad block by testing a memory block.

Test method of a nonvolatile memory device according to another aspect of the present invention,

A first read and data input step of reading a first latch of a page buffer of a first page of a selected memory block and receiving comparison data for comparison with the first data to a second latch of the page buffer; Initializing a third latch of the page buffer; A first data comparing step of comparing data stored in the first and second latches and changing data of the first to third latches according to a comparison result; Change the data in the first latch changed by the first data comparing step according to the state of the data programmed in the second page of the selected memory block, and convert the data for comparison with the second page into the second latch. A second read and data input step received; A second data comparing step of comparing data stored in the first and second latches and changing data states of the first to third latches according to the result; And repeatedly performing the second read and data input step and the second data compare step with respect to the remaining pages of the selected memory block.

Counting the number of data that is determined to be failure among data finally stored in the third latch; And bad-blocking the selected memory block when the counting result is equal to or greater than a set number.

When the counting result is less than or equal to the set number, the repair is performed on the bit line determined as the fail.

The first or second data comparing step may include changing data of the first latch according to a data state of the third latch; Changing data in the third latch in accordance with the data state of the second latch; Changing data in the third latch in accordance with the data state of the first latch; Changing the data state of the first latch in accordance with the data state of the second latch; And changing the data of the third latch in accordance with the data state of the first latch.

Test method of a nonvolatile memory device according to another aspect of the present invention,

After initializing the page buffer according to the test command, the first data of the first page of the selected memory block is read into the first latch of the page buffer, and the first comparison data for comparing with the data of the first page is read. A first page test step of fixing fail data to a third latch of a page buffer connected to a first bit line by comparing data of the first and second latches after receiving the second latch of the page buffer; ; After changing the data of the first latch according to the second data state of the second page of the selected memory block and receiving the second comparison data for comparison with the data of the second page, the second latch is input. A second page test step of comparing the data of the first and second latches to fix the fail data to the third latch in a page buffer connected to the second bit line in different cases; And performing the same operation as the second page test step on all pages of the selected memory block, and then determining whether the selected memory block is a bad block using data of the third latch of the page buffer. do.

Determining whether the bad block comprises: counting the number of data that is determined to fail among the data finally stored in the third latch; And bad-blocking the selected memory block when the counting result is equal to or greater than a set number.

When the counting result is less than or equal to the set number, the repair is performed on the bit line determined as the fail.

Comparing data of the first and second latches and fixing fail data to the third latch may include: changing data of the first latch according to a data state of the third latch; Changing data in the third latch in accordance with the data state of the second latch; Changing data in the third latch in accordance with the data state of the first latch; Changing the data state of the first latch in accordance with the data state of the second latch; And changing the data of the third latch in accordance with the data state of the first latch.

As described above, in the test method of a nonvolatile memory device according to the present invention, when testing a memory block, after initializing only the first page, externally input data and read data for each page are performed. The test time can be shortened by testing by the memory block unit by comparing and verifying the test result so that the test result is fixed.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a flash memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a voltage providing unit 150, and a controller 160. And a data input / output unit 170.

The memory cell array 110 includes a plurality of cell strings in which memory cells for data storage are connected in series, and each cell string is connected to a bit line BL. In addition, the gates of the memory cells are connected to the word line WL in a direction orthogonal to the bit line.

The page buffer unit 120 includes a plurality of page buffers 121 connected to bit lines of the memory cell array 110. Each page buffer 121 temporarily stores data to be programmed in a selected memory cell. The data is transferred to a memory cell through a bit line, or data stored in the memory cell is read and stored.

The page buffer includes a plurality of latch circuits, and while the program is executed using one latch circuit, program data may be input to the other latch circuit next.

The Y decoder 130 provides an input / output path to the page buffer 121 of the page buffer unit 120 according to the input address, and the X decoder 140 selects the word line of the memory cell array 110 according to the input address. do.

The voltage providing unit 150 generates an operation voltage to be provided to a word line connected by the X decoder 140 under the control of the controller 160, and the controller 160 outputs a control signal according to an operation command. The voltage providing unit 150 is controlled to provide a pass voltage set according to the data program degree of the memory cell array 110.

The data input / output unit 170 transfers data to be programmed from an IO pad of the nonvolatile memory device 100 to the Y decoder 130 or the data verification unit 180 under the control of the controller 160, and the Y The data output through the decoder 130 is transferred to the IO pad.

The plurality of page buffers 121 included in the page buffer unit 120 have three latches for a LSB (Least Significant Bit) program and a MSB (Most Significant Bit) program.

1B is a detailed circuit diagram of the page buffer.

Referring to FIG. 1B, the page buffer 121 includes a sensing unit 122, a precharge unit 123, a latch unit 124, and a verification unit 128.

The sensing unit 122 senses a voltage of a bit line connected by an input address when data is read. The sensing result of the sensing unit 122 is reflected as the sensing node SO.

The precharge unit 123 precharges the sensing node SO, and the latch unit 124 includes a plurality of latch circuits connected to the sensing node SO to form a memory cell according to the voltage level of the sensing node SO. The stored data is stored in the latch circuit or the data to be programmed is stored in the latch circuit and then transferred to the sensing node SO.

The latch unit 124 includes first to third latch circuit units 125 to 127. The first latch circuit unit 125 is used to temporarily store data for a cache program or to perform intelligent verify (hereinafter referred to as IV). The second latch circuit unit 126 serves as a main latch for a program, and the third latch circuit unit 127 performs a temporary latch operation.

The verification unit 128 is connected between the first and second latch circuit units 125 and 126 to output a verification signal for program verification.

The sensing unit 122 includes a first NMOS transistor N1, and the precharge unit 123 includes a PMOS transistor P. FIG.

The first latch circuit unit 125 includes second to fourth NMOS transistors N2 to N4, and includes first to second inverters IN1 and IN2. The second latch circuit unit 126 includes first to third NMOS transistors N5 to N7 and third and fourth inverters IN3 and IN4.

The third latch circuit unit 127 includes fourth to seventh NMOS transistors N8 to N11 and fifth and sixth inverters IN5 and IN6, and the verification unit includes ninth to eleventh NMOS transistors N13 to N15. It includes. In addition, the latch unit 124 includes an eighth NMOS transistor N12.

The first NMOS transistor N1 is connected between the bit line and the sensing node SO, and the sensing control signal PBSENSE is input to the gate of the first NMOS transistor N1. The first NMOS transistor N1 is turned on or off according to the voltage of the bit line to which it is connected and the voltage level of the sensing control signal PBSENSE. As the first NMOS transistor N1 is turned on or turned off, the voltage level of the sensing node SO is changed to change data stored in the latch unit 124.

The PMOS transistor P is connected between the power supply voltage and the sensing node SO, and the precharge control signal PRECH_N is input to the gate of the PMOS transistor P.

The second NMOS transistor N2 is connected between the sensing node SO and the node QC_N, and the first data transfer signal TRAN is input to the gate of the second NMOS transistor N2.

The first and second inverters IN1 and IN2 are connected in a latch circuit form between the node QC and the node QC_N to form the first latch L1.

The third NMOS transistor N3 is connected between the node QC and the node K1, and the fourth NMOS transistor N4 is connected between the node QC_N and the node K1. The first reset signal CRST and the first set signal CSET are input to the gates of the third and fourth NMOS transistors N3 and N4, respectively.

The fifth NMOS transistor N5 is connected between the sensing node SO and the node QM_N, and the second data transfer signal TRANM is input to the gate of the fifth NMOS transistor N5. The third and fourth inverters IN3 and IN4 are connected between the node QM and the node QM_N in the form of a latch circuit to form the second latch L2.

The sixth NMOS transistor N6 is connected between the node QM and the node K1, and the seventh NMOS transistor N7 is connected between the node QM_N and the node K1. The second reset signal MRST and the second set signal MSET are input to gates of the sixth and seventh NMOS transistors N6 and N7, respectively.

The eighth NMOS transistor N8 is connected between the sensing node SO and the node QT, and the ninth NMOS transistor N9 is connected between the sensing node SO and the node QT_N. The third data transfer inversion signal TRANT_N and the third data transfer signal TRANT are input to gates of the eighth and ninth NMOS transistors N8 and N9, respectively.

The fifth and sixth inverters IN5 and IN6 are connected between the node QT and the node QT_N in a latch circuit form to form the third latch L3.

The tenth NMOS transistor N10 is connected between the node QT and the node K1, and the eleventh NMOS transistor N11 is connected between the node QT_N and the node K1. The third reset signal TRST and the third set signal TSET are input to gates of the tenth and eleventh NMOS transistors N10 and N11, respectively.

The twelfth NMOS transistor N12 is connected between the node K1 and the ground node, and the sensing node SO is connected to the gate of the twelfth NMOS transistor N12.

The thirteenth and fourteenth NMOS transistors N13 and N14 are connected between the node K2 and the verify signal output node nWDo, and the gate of the thirteenth NMOS transistor N13 is connected to the node QC_N, and the fourteenth The page buffer check signal PBCHECK is connected to the gate of the NMOS transistor N14.

The fifteenth NMOS transistor N15 is connected between the ground node and the node K2, and the gate of the fifteenth NMOS transistor N15 is connected to the node QM.

When the page buffer 121 performs a program and verify, an operation of performing intelligent verify is as follows.

2A is a flowchart of an intelligent program verification operation.

Referring to FIG. 2A, a program is executed by inputting data to be programmed into the page buffer 121 as shown in FIG. 1B (S210).

In order to verify the program, data stored in the memory cell is read in the page buffers 121 of the page buffer unit 120 (S230). The read command at this time uses 00H.

In operation S250, data for comparison with the read data is received. In this case, 80H, a command for data input, can be used.

Thereafter, the read data of the step S230 and the input data of the step S250 are compared (S270), and the program state is checked (S290). At this time, command 2FH can be used for data comparison.

The data comparison process will be described in more detail with reference to the page buffer 121 of FIG. 1B.

2B is a flowchart of a data comparison operation of FIG. 2A.

Referring to FIG. 2B, first, data stored in the selected memory cell after the program operation is read into the node QM_N of the second latch L2 (S230). The data to be compared is received by the data input command to the node QC_N of the first latch L1 (S250).

In the description of the second embodiment of the present invention, the data state of the memory cell is '1' or '0', and it can be considered as four cases (A to D) in the case where each data state is a program pass or fail.

That is, in the first case (A), the data to be stored in the actual memory cell is '1' and the data input to the node QM_N of the read result page buffer 121 is '1'. In this case, the result should be a program pass. In the second case (B), the actual data is '1' and the read data is '0'. In this case, the result should be a program fail.

Similarly, the third and fourth (C, D) are pass and fail cases, respectively.

Therefore, the data read in step S230 is '1001' if four cases are displayed at once. The data input in step S250 displays four cases at once to become '1100'.

As described above, the data stored in the first to third latches L1 to L3 of the page buffer 121 for the four cases are shown in the following table.

As shown in Table 1, when the comparison command 2FH is input after the data is input to the first and second latches L1 and L2 (S271), the data of the first latch L1 is first transferred to the third latch L3. Transfer to (S272). To this end, the first data transfer signal TRAN for turning on the second NMOS transistor N2 of the page buffer 121 is input at a high level, and the third reset signal TRST is input at a high level. As a result, as shown in Table 1, the QT_N node is in the '1100' state.

Thereafter, the first latch L1 is reset (S273). At this time, the reset applies the first reset signal CRST after precharging the sensing node SO.

After resetting the first latch L1, the data of the third latch L3 is inputted back into the first latch L1. At this time, the data of the node QT_N of the third latch L3 is inverted to generate the first latch L1. The data is input to the node QC_N of the first latch L1 (S274). To this end, the third data transmission signal TRANT and the first set signal CSET are input. As a result, node QC_N becomes '0011'.

Thereafter, the read data stored in the second latch L2 is input to the first latch L1 (S275). To this end, the second data transmission signal TRANM and the first reset signal CRST are input. When the data of the second latch L2 is input to the first latch L1, the data stored in the first latch L1 is changed from '0011' to '1011'.

The data of the third latch L3 is transferred to the second latch L2 (S276). To this end, a third data transmission signal TRANT and a second set signal MSET are applied. By this operation, the data state of the second latch L2 is changed from '1001' to '0001'.

Next, the data of the second latch L2 is transferred to the first latch L1 (S277). In this case, the second data transmission signal TRANT and the first set signal CSET are applied, and the first latch L1 becomes '10110'.

Finally, the data of the first latch L1 is transferred to the second latch L2 again (S278). In this case, the first data transmission signal TRAN, the second reset signal, and the second set signals MSET and MRST are applied, and the data of the second latch L2 becomes '1010'.

Accordingly, the verification unit 128 may output a verification signal as pass-fail-pass-fail according to the data state of the second latch L2. This is the same as the program pass and fail results of the four cases assumed when the above-described FIG. 2B is described.

That is, intelligent program verification can be performed with only one data reading. The verification result is transmitted to the controller 160, and the controller 160 determines a program pass when a failure occurs in a range capable of error correction.

Meanwhile, according to an embodiment of the present invention, a method of testing whether a memory block is a bad block is as follows.

3 is a flowchart illustrating a memory block test method according to an embodiment of the present invention.

3, the page buffer 121 of FIG. 1B and the following Table 2 will be described together.

Referring to FIGS. 3, 1B, and 2, when a test command is input (S301), data is written to a first page which is a first word line of a memory block selected according to address information input together with the test command. In operation S303, comparison data for comparison with data read in the first page is input (S305).

The data of the first page is read out to the node QM_N. The read data is '1001', and the data of the node QM_N is transferred to the node QC_N. Data to be compared is input to the node QC_N. Accordingly, the node QC_N becomes '1100' and the node QM_N is '1010'.

In operation S307, the node QT of the third latch L3 is initialized. When the node QT is initialized, the data of the node QT becomes '1111'. If node QT is '1111', node QT_N is '0000'. Even when the data of the node QT is transferred to the node QM_N, the data state of the node QM_N does not change to '1010'.

Then, the read data is compared with the input comparison data using the data of the first to third latches L1 to L3, and the state of the first to third latches L1 to L3 is changed according to the result (S309). ).

First, data of the node QC_T is transferred to the node QT.

Node QC_N is in a '1100' state. Therefore, when the first data transmission signal TRAN is applied at a high level, the sensing node SO is in a '1100' state. When the third reset signal TRST is applied at a high level, the node QT becomes '0011'.

The data of the node QM_N is transferred to the node QT.

Node QM_N is in a '1001' state. Therefore, when the second data transmission signal TRANM is applied at a high level, the sensing node SO becomes '1001'. When the third set signal TSET is applied at a high level, the node QT becomes '1011'.

Data of the node QC_N is transferred to the node QM_N.

Node QC_N is '1100', and thus node QM_N is '0001'. The data of the node QM_N is transferred to the node QT so that the node QT becomes '1010'.

As described above, the data of the first page is read and compared, and the result of the comparison is stored in the node QT.

Then, the test for the second page is started again without initializing the page buffer.

For the second page test, first, the second page data is read to the node QM_N (S311), and data to be compared to the node QC_N is input (S313).

Data is transferred between the latches in the same manner as the comparison operation of the first page (S315). At this time, in the data comparison of the first page, there is data initialization of the node QT. From the second page, data comparison is performed by applying the previous state as it is without initializing the data of the node QT.

Then, steps S311 to S319 are repeatedly performed until the last page.

As a result, all pages of the memory block are continuously read and compared with the input data, and the final result is stored in the node QT. Since the result is accumulated and stored in the node QT, if a memory cell of one of the memory cells connected to the bit line fails, the bit line having the fail may be checked using the node QT.

When the test is completed for all the memory blocks, the data stored in the third latch L3 is output (S321). To this end, after initializing the node QM_N to '1', the data of the node QT may be moved and the verification unit 128 may perform pass and fail verification. Alternatively, by passing the data of the node QT to the node QC_N and outputting the counted data, the test apparatus counts fail data (S323) and determines whether the bad block is present (S325).

The bad block determination may be determined by the controller 160 instead of the test apparatus. That is, after the controller 160 transmits the data of the node QT to the node QM_N, a fail check may be performed, and the bad block may be determined by counting the bit line in which the fail has occurred.

The bad block is determined as a bad block when the bit lines fail more than the set number.

The above test in units of memory blocks may be used to determine whether a bad block process or repair can be performed by identifying the number of bit lines to which a failed memory cell is connected.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1A is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

1B is a detailed circuit diagram of the page buffer.

2A is a flowchart of an intelligent program verification operation.

2B is a flowchart of a data comparison operation of FIG. 2A.

3 is a flowchart illustrating a memory block test method according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

100 nonvolatile memory device 110 memory cell array

120: page buffer unit 130: Y decoder

140: X decoder 150: voltage provider

160 control unit 170 data input / output unit

Claims (8)

A first read and data input step of reading a first latch of a page buffer of a first page of a selected memory block and receiving comparison data for comparison with the first data to a second latch of the page buffer; Initializing a third latch of the page buffer; A first data comparing step of comparing data stored in the first and second latches and changing data of the first to third latches according to a comparison result; Change the data in the first latch changed by the first data comparing step according to the state of the data programmed in the second page of the selected memory block, and convert the data for comparison with the second page into the second latch. A second read and data input step received; A second data comparing step of comparing data stored in the first and second latches and changing data states of the first to third latches according to the result; And Repeatedly performing the second read and data input step and the second data compare step with respect to the remaining pages of the selected memory block. Test method of a nonvolatile memory device comprising a. The method of claim 1, Counting the number of data that is determined to be failure among data finally stored in the third latch; And And performing bad block processing on the selected memory block when the counting result is equal to or greater than a set number. The method of claim 1, And if the counting result is less than or equal to the set number, repairing the bit line determined to fail. The method of claim 1, The first or second data comparison step, respectively, Changing data of the first latch in accordance with a data state of the third latch; Changing data in the third latch in accordance with the data state of the second latch; Changing data in the third latch in accordance with the data state of the first latch; Changing the data state of the first latch in accordance with the data state of the second latch; And Changing the data of the third latch in accordance with the data state of the first latch Test method of a nonvolatile memory device comprising a. After initializing the page buffer according to the test command, the first data of the first page of the selected memory block is read into the first latch of the page buffer, and the first comparison data for comparing with the data of the first page is read. A first page test step of fixing fail data to a third latch of a page buffer connected to a first bit line by comparing data of the first and second latches after receiving the second latch of the page buffer; ; After changing the data of the first latch according to the second data state of the second page of the selected memory block and receiving the second comparison data for comparison with the data of the second page, the second latch is input. A second page test step of comparing the data of the first and second latches to fix the fail data to the third latch in a page buffer connected to the second bit line in different cases; And Performing the same operation as the second page test step on all pages of the selected memory block, and then determining whether the selected memory block is a bad block by using data of a third latch of the page buffer Test method of a nonvolatile memory device comprising a. The method of claim 5, Determining whether or not the bad block, Counting the number of data that is determined to be failure among data finally stored in the third latch; And And performing bad block processing on the selected memory block when the counting result is equal to or greater than a set number. The method of claim 6, And if the counting result is less than or equal to the set number, repairing the bit line determined to fail. The method of claim 5, Comparing the data of the first and second latch, and fixing the fail data to the third latch, Changing data of the first latch in accordance with a data state of the third latch; Changing data in the third latch in accordance with the data state of the second latch; Changing data in the third latch in accordance with the data state of the first latch; Changing the data state of the first latch in accordance with the data state of the second latch; And Changing the data of the third latch in accordance with the data state of the first latch Test method of a nonvolatile memory device comprising a.

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