KR20100110130A

KR20100110130A - Thin film transistor array panel

Info

Publication number: KR20100110130A
Application number: KR1020090028545A
Authority: KR
Inventors: 김동규
Original assignee: 삼성전자주식회사
Priority date: 2009-04-02
Filing date: 2009-04-02
Publication date: 2010-10-12

Abstract

PURPOSE: A thin film transistor substrate is provided to improve the aperture ratio by efficiently arrange a pixel electrode, a thin film transistor, and a plurality of data lines. CONSTITUTION: A thin film transistor substrate includes pixels, gate lines, a first data line(121a), a second date line(121b), and a third data line(121c). The pixels respectively include pixel electrodes and transistors and are arranged in a matrix. The gate lines are expanded to correspond to each pixel row and are spaced apart in a row direction. The first data line, the second data line, and the third date line are expanded to correspond to each pixel row and are spaced apart in a line direction.

Description

Thin Film Transistor Boards {THIN FILM TRANSISTOR ARRAY PANEL}

Embodiments of the present invention relate to thin film transistor substrates. More specifically, the present invention relates to a thin film transistor substrate that can be used in various fields in a display field such as a liquid crystal display device.

BACKGROUND ART A liquid crystal display is a flat panel display widely used. The liquid crystal display includes two display panels on which an electric field generating electrode, such as a pixel electrode and a common electrode, is formed, and a liquid crystal layer interposed therebetween. By determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of the incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

The liquid crystal display has a problem in that the response speed is slow because the display is performed by the mechanical operation of the liquid crystal. To solve this problem, a method of increasing the driving frequency has been developed. However, when the driving frequency is increased, the charge charging time of each pixel electrode is shortened.

In order to solve this problem, a method of arranging a plurality of data lines in each pixel column and simultaneously charging a plurality of pixel rows has been developed, but this also has problems such as complicated structure of the pixel and difficulty in connecting the data line and the data driving circuit. .

An embodiment of the present invention provides a thin film transistor substrate that can increase the aperture ratio by facilitating the structural complexity associated with wiring when employing a plurality of data lines and facilitate the connection of the data driving circuit and the data lines.

According to an embodiment of the present invention, each of the thin film transistor substrates includes a pixel electrode and a transistor, and includes a plurality of pixels arranged in a row, a gate line extending corresponding to each pixel row and spaced apart in the column direction. And a first data line, a second data line, and a third data line extending corresponding to each pixel column and spaced apart in the row direction, wherein the first data line and the second data line correspond to the corresponding pixel column. The first data line is positioned on the left side so as to be arranged outside the second data line, the third data line is positioned on the right side of the corresponding pixel column, and the gate lines are classified into one gate line group. The same scan signal is applied.

In a pixel having a transistor connected to a first data line, a transistor may be formed in a region between the first data line and the second data line, and an extension of the pixel electrode may be connected to the transistor across the second data line. The region where the transistor is located may be formed to be refracted in a shape in which the second data line is far from the first data line and then closes again.

The thin film transistor substrate may further include an insulating layer interposed between the extension of the pixel electrode and the second data line in an area where the extension of the pixel electrode crosses the second data line. The source electrode of the transistor may extend from the first data line.

The transistor includes a first transistor and a second transistor, the pixel electrode includes a first pixel electrode and a second pixel electrode, and an extension of the first pixel electrode is connected to a drain electrode of the first transistor across the second data line. The extension portion of the second pixel electrode may be connected to the drain electrode of the second transistor across the second data line.

The thin film transistor substrate crosses the first data line and the second data line and extends across the first pixel electrode, intersects the first storage electrode line, the first data line and the second data line, and is disposed between the first pixel electrode and the second pixel electrode. A first charge sharing extending from and intersecting the first gate line, the first data line, and the second data line connected to the gate electrodes of the first and second transistors and extending between the first pixel electrode and the second pixel electrode; A first charge sharing transistor having a gate line, a gate electrode connected to the first charge sharing gate line, and a source electrode connected to the second pixel electrode, and a first electrode connected between the drain electrode and the first storage electrode line of the first charge sharing transistor; It may further include a 1 down capacitor.

In a pixel having a transistor connected to a second data line, the transistor may be positioned between the second data line and the third data line. The transistor may be located closer to the second data line than the third data line, and an extension of the pixel electrode may be connected to the transistor without crossing the second data line.

The transistor includes a third transistor and a fourth transistor, the pixel electrode includes a third pixel electrode and a fourth pixel electrode, the source electrode of the third transistor and the source electrode of the fourth transistor are connected to the second data line, The drain electrode of the third transistor and the drain electrode of the fourth transistor may be connected to the third pixel electrode and the fourth pixel electrode, respectively.

The thin film transistor substrate may intersect the first data line and the second data line and extend between the second storage electrode line, the first data line, and the second data line, and intersect the third and fourth pixel electrodes. A second charge sharing gate positioned at and intersecting the second gate line, the first data line, and the second data line connected to the gate electrodes of the third transistor and the fourth transistor, and positioned between the third pixel electrode and the fourth pixel electrode. A second charge sharing transistor having a line, a gate electrode connected to the second charge sharing gate line, and a source electrode connected to the fourth pixel electrode, and a second connected between the drain electrode and the second storage electrode line of the second charge sharing transistor. It may further include a down capacitor.

In a pixel having a transistor connected to a third data line, the transistor may be formed in a region between the second data line and the third data line. The transistor may be located closer to the third data line than the second data line, and an extension of the pixel electrode may be connected to the transistor without crossing the second data line.

The transistor includes a fifth transistor and a sixth transistor, the pixel electrode includes a fifth pixel electrode and a sixth pixel electrode, the source electrode of the fifth transistor and the source electrode of the sixth transistor are connected to the third data line, The drain electrode of the fifth transistor and the drain electrode of the sixth transistor may be connected to the fifth pixel electrode and the sixth pixel electrode, respectively.

The thin film transistor substrate may intersect the first and second data lines and extend between the third storage electrode line, the first data line, and the second data line, and extend between the fifth pixel electrode and the sixth pixel electrode. A third charge sharing gate positioned at and intersecting the third gate line, the first data line, and the second data line connected to the gate electrodes of the fifth transistor and the sixth transistor and positioned between the fifth pixel electrode and the sixth pixel electrode; A third charge sharing transistor having a line, a gate electrode connected to the third charge sharing gate line, and a source electrode connected to the sixth pixel electrode, and a third down connected between the drain electrode and the third sustain electrode line of the third charge sharing transistor It may further include a capacitor.

Pixels neighboring in the row direction have opposite polarities, and pixels neighboring in the column direction may have opposite polarities. The pixel includes a first pixel having a first transistor and a second transistor connected to a first data line, a third pixel connected to a second data line, a second pixel having a fourth transistor, and a fifth transistor connected to a third data line. And a third pixel having a sixth transistor, and a region in which the first transistor and the second transistor are positioned in the first pixel may be between the first data line and the second data line. The region in which the first transistor and the second transistor are located may be formed to be refracted in a shape in which the second data line is far from the first data line and then closes again.

An area in which the third transistor and the fourth transistor are positioned in the second pixel is between the second data line and the third data line, and may be located closer to the second data line than the third data line. An area in which the fifth transistor and the sixth transistor are positioned in the third pixel may be between the second data line and the third data line, and may be located closer to the third data line than the second data line.

According to the exemplary embodiment of the present invention, the aperture ratio can be increased by efficiently arranging the pixel electrode, the thin film transistor, and the data line, and the connection between the data line and the data driving circuit can be facilitated.

In addition, by appropriately arranging pixels in the row direction and the column direction, it is possible to prevent vertical stir and vertical cross-talk.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. I) The shape, size, ratio, angle, number, etc. shown in the accompanying drawings may be changed to be rough. ii) Since the drawings are shown with the eyes of the observer, the direction or position for describing the drawings may be variously changed according to the positions of the observers. iii) The same reference numerals may be used for the same parts even if the reference numbers are different. iv) When 'include', 'have', 'consist', etc. are used, other parts may be added unless 'only' is used. v) When described in the singular, the plural may also be interpreted. vi) Even if numerical values, shapes, sizes comparisons, positional relations, etc. are not described as 'about' or 'substantial', they are interpreted to include a normal error range. vii) The terms 'after', 'before', 'following', 'and', 'here', and 'following' are not used to limit the temporal position. viii) The terms 'first', 'second', 'third' and 'fourth' are merely used selectively, interchangeably or repeatedly for convenience of distinction and are not to be interpreted in a limiting sense. ix) where the positional relationship of the two parts is described as 'above', 'upper', 'below', 'beside', etc., one or more other The part may be interposed. x) When parts are connected with '~', they are interpreted to include not only parts but also combinations, but only when parts are connected with 'or'.

1 is a front view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

The thin film transistor substrate according to the exemplary embodiment of the present invention includes a first data line, a second data line, and a third data line. In detail, the first data line and the second data line are disposed on one side of the pixel electrode. The first data line is located outside the second data line. That is, the second data line is located closer to the pixel electrode than the first data line. The third data line is disposed on the other side of the pixel electrode.

In the region “A” of FIG. 1, a pixel electrode is connected to a first data line through a transistor. In the region “B” of FIG. 1, a pixel electrode is connected to a second data line through a transistor. In the region “C” of FIG. 1, a pixel electrode is connected to a third data line through a transistor.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. FIG. 3 is a cross-sectional view taken along the line II-II 'of the region “A” of FIG. 1.

Referring to area “A” of FIG. 1, FIGS. 2 and 3, a first storage electrode line 131a, a first storage electrode 133a, a first lower electrode 134a, and a first gate line on the substrate 110. 121a, a first gate electrode 124a, a second gate electrode 124b, a first charge sharing gate electrode 125a, and a first charge sharing gate line 126a are positioned.

The first storage electrode line 131a, the first gate line 121a, and the first charge sharing gate line 126a are sequentially spaced apart from each other along the first direction. The first storage electrode line 131a, the first gate line 121a, and the first charge sharing gate line 126a extend in a second direction substantially perpendicular to the first direction.

The first storage electrode 133a may be a pair and extend from the first storage electrode line 131a along the first direction. The first lower electrode 134a extends along the second direction from the first sustain electrode 133a.

The first gate electrode 124a and the second gate electrode 124b are integrally formed with the first gate line 121a. An extended portion of the first gate line 121a may be divided to be used as the first gate electrode 124a and the second gate electrode 124b.

The first charge sharing gate electrode 125a is integrally formed with the first charge sharing gate line 126a. An extended portion of the first charge sharing gate line 126a may be used as the first charge sharing gate electrode 125a.

First storage electrode line 131a, first storage electrode 133a, first lower electrode 134a, first gate line 121a, first gate electrode 124a, second gate electrode 124b, and first The gate insulating layer 140 is positioned on the charge sharing gate electrode 125a and the first charge sharing gate line 126a.

The first semiconductor pattern 151a, the second semiconductor pattern 151b, and the first charge sharing semiconductor pattern 152a are formed on the gate insulating layer 140, respectively, for the first gate electrode 124a, the second gate electrode 124b, and the first gate pattern 152a. It is located at a position corresponding to the one charge sharing gate electrode 125a. The first semiconductor pattern 151a and the second semiconductor pattern 151b may be spaced apart from each other.

The first data line 171a and the second data line 171b are disposed on one side of the thin film transistor substrate close to the first semiconductor pattern 151a and the second semiconductor pattern 151b on the gate insulating layer 140. The first data line 171a is positioned outside the second data line 171b.

In detail, the first data line 171a extends in the first direction and is positioned outside the first semiconductor pattern 151a and the second semiconductor pattern 151b. The second data line 171b extends in the first direction and surrounds the first semiconductor pattern 151a and the second semiconductor pattern 151b so as not to intersect the first semiconductor pattern 151a and the second semiconductor pattern 151b. It has a shape to bypass. That is, the second data line 171b is refracted in a shape of moving away from the first data line 171a and approaching again. Therefore, the first semiconductor pattern 151a and the second semiconductor pattern 151b are positioned between the first data line 171a and the second data line 171b.

The third data line 171c is positioned on the gate insulating layer 140 on the opposite side of the first data line 171a and the second data line 171b based on the corresponding pixel column. The third data line 171c extends along the first direction. The first data line 171a and the second data line 171b are positioned at one side with respect to the corresponding pixel column, but only one third data line 171c is positioned at the opposite side.

The first source electrode 153a extends from the first data line 171a and partially overlaps the first semiconductor pattern 151a. The second source electrode 153b extends from the first source electrode 153a and partially overlaps the second semiconductor pattern 151b. The first charge sharing source electrode 154a partially overlaps the first charge sharing semiconductor pattern 152a.

The first drain electrode 155a is spaced apart from the first source electrode 153a on the first semiconductor pattern 151a. The second drain electrode 155b is spaced apart from the second source electrode 153b on the second semiconductor pattern 151b. The first charge sharing drain electrode 156a is spaced apart from the first charge sharing source electrode 154a on the first charge sharing semiconductor pattern 152a.

Here, between the first semiconductor pattern 151a and the first source electrode 153a, between the second semiconductor pattern 151b and the second source electrode 153b, the first charge sharing semiconductor pattern 152a and the first Between the charge sharing source electrode 154a, between the first semiconductor pattern 151a and the first drain electrode 155a, between the second semiconductor pattern 151b and the second drain electrode 155b, and the first charge sharing An ohmic contact layer 160 may be disposed between the semiconductor pattern 152a and the first charge sharing drain electrode 156a to reduce contact resistance.

The first contact region 139a has a shape extending from the first charge sharing source electrode 154a. The first upper electrode 135a extends from the first charge sharing drain electrode 156a and has a shape overlapping with the first lower electrode 134a.

The passivation layer 180 is positioned on the above-described structures. The insulating layer 193 is positioned on the passivation layer 180. According to an embodiment of the present invention, a color filter (not shown) may be positioned between the passivation layer 180 and the insulating layer 193.

In the insulating layer 193 and the passivation layer 180, the first contact hole H1 and the second contact hole H2 exposing the first drain electrode 155a, the second drain electrode 155b, and the first contact region 139a. ) And the first opening P1 are formed.

The first pixel electrode 191a and the second pixel electrode 191b are disposed on the insulating layer 193. The first pixel electrode 191a and the second pixel electrode 191b are formed between the second data line 171b and the third data line 171c, and the first semiconductor pattern 151a and the second semiconductor pattern 151b. Face each other with). The first gate line 121a and the first charge sharing gate line 126a are positioned between the first pixel electrode 191a and the second pixel electrode 191b.

The first pixel electrode 191a includes the extension part a1 integrally. The extension part a1 extends while crossing the second data line 171b and is connected to the first drain electrode 155a through the first contact hole H1. Therefore, the first pixel electrode 191a is electrically connected to the first drain electrode 155a by the extension part a1. As shown in FIG. 2, the passivation layer 180 and the insulating layer 193 between the extension part a1 and the second data line 171b at a portion where the extension part a1 crosses the second data line 171b. ) Is located. Thus, an electric short between the extension a1 and the second data line 171b is prevented.

The second pixel electrode 191b includes the extension part b1 and the protrusion part b2 integrally. The extension part b1 extends while crossing the second data line 171b and is connected to the second drain electrode 155b through the second contact hole H2. Therefore, the second pixel electrode 191b is electrically connected to the second drain electrode 155b by the extension part b1. The protrusion b2 extends and connects with the first contact region 139a through the first opening P1. Therefore, the second pixel electrode 191b is electrically connected to the first contact region 139a by the protrusion b2.

The first gate electrode 124a, the first semiconductor pattern 151a, the first source electrode 153a, and the first drain electrode 155a form a first transistor T1. The second gate electrode 124b, the second semiconductor pattern 151b, the second source electrode 153b, and the second drain electrode 155b form a second transistor T2. The first charge sharing gate electrode 125a, the first charge sharing semiconductor pattern 152a, the first charge sharing source electrode 154a, and the first charge sharing drain electrode 156a form the first charge sharing transistor Tcs1. do. The first lower electrode 134a, the gate insulating layer 140, and the first upper electrode 135a form a first down capacitor C1.

A charge sharing effect may be realized between the second pixel electrode 191b and the first down capacitor C1 by using the first charge sharing transistor Tcs1. Specifically, when the first charge sharing transistor Tcs1 is turned on after the first transistor T1 and the second transistor T2 are turned on, the first pixel electrode 191a and the second pixel electrode are turned on. Part of the charge charged to the second pixel electrode 191b among the charges charged to the same voltage at 191b moves to the first down capacitor C1 so that the voltage of the second pixel electrode 191b is changed to the first pixel electrode 191a. Will be lower than). Accordingly, side visibility may be improved by forming a voltage difference between the first pixel electrode 191a and the second pixel electrode 191b.

As described above, the extension part a1 of the first pixel electrode 191a extends while crossing the second data line 171b and is exposed to the first contact hole H1. It is directly connected to the first drain electrode 155a. In addition, the extension part b1 of the second pixel electrode 191b extends while crossing the second data line 171b to expose the second drain electrode of the second transistor T2 exposed to the second contact hole H2. Is directly connected to 155b. Therefore, the wiring structure can be simplified. In addition, the first transistor T1 and the second transistor T2 are positioned between the first data line 171a and the second data line 171b. Therefore, the aperture ratio can be improved by increasing the space utilization.

Referring to region “B” of FIG. 1, the second charge sharing gate electrode 125b, the second charge sharing semiconductor pattern 152b, the second charge sharing source electrode 154b, and the second charge sharing drain electrode 156b are provided. A second charge sharing transistor Tcs2 including; A second down capacitor C2 including a second lower electrode 134b, a gate insulating layer 140, and a second upper electrode 135b; Second gate line 121b; Second charge sharing gate line 126b; Second storage electrode line 131b; Second sustain electrode 133b; And the second contact region 139b may include the first charge sharing gate electrode 125a, the first charge sharing semiconductor pattern 152a, the first charge sharing source electrode 154a, and the first charge sharing drain of the region “A”, respectively. A first charge sharing transistor Tcs1 including an electrode 156a; A first down capacitor C1 including a first lower electrode 134a, a gate insulating layer 140, and a first upper electrode 135a; First gate line 121a; A first charge sharing gate line 126a; The first storage electrode line 131a; The first sustain electrode 133a; And since the description is substantially the same as the first contact region 139a, repeated description is omitted.

In the region “B”, the second data line 171b extends substantially linearly along the first direction, unlike the region “A”, which has an inwardly curved shape.

Third transistor T3 and fourth gate electrode including third gate electrode 124c, third semiconductor pattern 151c, third source electrode 153c, and third drain electrode 155c in region “B”. The fourth transistor T4 including the 124d, the fourth semiconductor pattern 151d, the fourth source electrode 153d, and the fourth drain electrode 155d may each have a first gate electrode 124a in an “A” region. The first transistor T1 and the second gate electrode 124b including the first semiconductor pattern 151a, the first source electrode 153a, and the first drain electrode 155a, the second semiconductor pattern 151b, It is substantially the same except for the position of the second transistor T2 including the second source electrode 153b and the second drain electrode 155b. Therefore, repeated description is omitted.

Unlike the first transistor T1 and the second transistor T2 in the "A" region, which are formed between the first data line 171a and the second data line 171b, the third transistor (in the "B" region) T3 and the fourth transistor T4 are located inside the corresponding pixel column than the second data line 171b. That is, the third transistor T3 and the fourth transistor T4 in the “B” region have second data than the third data line 171c between the second data line 171b and the third data line 171c. It is located close to the line 171b.

The third source electrode 153c and the fourth source electrode 153d in the region “B” are respectively connected to the first source electrode 153a and the second source electrode 153b in the region “A” except for the data line connected thereto. Substantially the same. Therefore, repeated description is omitted.

Unlike the first source electrode 153a and the second source electrode 153b in the region “A”, which are connected to the first data line 171a, the third source electrode 153c and the fourth source electrode in the region “B” 153d is connected to the second data line 171b.

The third pixel electrode 191c neighboring the second pixel electrode 191b of the region “A” and the fourth pixel electrode 191d neighboring the third pixel electrode 191c are positioned in the “B” region. In detail, the third pixel electrode 191c and the fourth pixel electrode 191d are sequentially positioned along the first direction. The third pixel electrode 191c and the fourth pixel electrode 191d of the “B” region are the first pixel electrode 191a and the second pixel electrode 191d of the “A” region except for the extension parts c1 and d1. Is substantially the same as Therefore, repeated descriptions are excluded.

In the region “A”, the extension part a1 of the first pixel electrode 191a extends while crossing the second data line 171b so that the first drain electrode is formed through the first contact hole H1 of the insulating layer 193. Unlike the connection with 155a, in the region “B”, the extension part c1 of the third pixel electrode 191c extends without crossing the second data line 171b so that the third contact hole of the insulating film 193 ( It is connected to the third drain electrode 155c through H3).

In the region “A”, the extension part b1 of the second pixel electrode 191b extends while crossing the second data line 171b to pass through the second contact hole H2 of the insulating film 193 to pass through the second drain electrode. Unlike the connection with 155b, in the region “B”, the extension part d1 of the fourth pixel electrode 191d extends without crossing the second data line 171b so that the fourth contact hole of the insulating layer 193 ( It is connected to the fourth drain electrode 155d through H4).

Accordingly, in the region “B”, the third transistor T3 and the fourth pixel electrode 191c and the fourth pixel electrode 191d include the third source electrode 153c and the fourth source electrode 153d, respectively. It is connected to the second data line 171b through the transistor T4.

In addition, the protrusion d2 of the fourth pixel electrode 191d illustrated in the region “B” extends to be substantially the same as the protrusion b2 of the second pixel electrode 191b illustrated in the region “A”. It is connected with the second contact region 139b through P2. Therefore, the fourth pixel electrode 191d is electrically connected to the second contact region 139b by the protrusion d2.

Referring to the "C" region of FIG. 1, the first data line 171a, the second data line 171b, and the third data line 171c extend substantially in the same shape as the "B" region. Therefore, further description is omitted.

The third gate line 121c, the third charge sharing gate line 126c, the third storage electrode line 131c, and the third storage electrode 133c in the "C" region may each have a second gate line ("B"). 121b), the second charge sharing gate line 126b, the second storage electrode line 131b, and the second storage electrode 133b are substantially the same. Therefore, further description is omitted.

A third charge including a third charge sharing gate electrode 125c, a third charge sharing semiconductor pattern 152c, a third charge sharing source electrode 154c, and a third charge sharing drain electrode 156c in the “C” region. Shared transistor Tcs3; A third down capacitor C3 including a third lower electrode 134c, a gate insulating layer 140, and a third upper electrode 135c; And the third contact region 139c may include the second charge sharing gate electrode 125b, the second charge sharing semiconductor pattern 152b, the second charge sharing source electrode 154b, and the second portion of the region “B” except for the position. A second charge sharing transistor Tcs2 including a second charge sharing drain electrode 156b; A second down capacitor C2 including a second lower electrode 134b, a gate insulating layer 140, and a second upper electrode 135b; And substantially the same as the second contact region 139b. Therefore, repeated description is omitted.

The third charge sharing transistor Tcs3, the third down capacitor C3, and the third contact region 139c in the “C” region are the second charge sharing transistor Tcs2 and the second down capacitor C2 in the “B” region. ) And the left and right sides of the second contact region 139b are disposed upside down.

The fifth transistor T5 and the sixth gate electrode including the fifth gate electrode 124e, the fifth semiconductor pattern 151e, the fifth source electrode 153e, and the fifth drain electrode 155e in the “C” region. The third gate T6 including the 124f, the sixth semiconductor pattern 151f, the sixth source electrode 153f, and the sixth drain electrode 155f, respectively, has a third gate in the “B” region except for the position thereof. Third transistor T3 and fourth gate electrode 124d including an electrode 124c, a third semiconductor pattern 151c, a third source electrode 153c, and a third drain electrode 155c, and a fourth semiconductor pattern. It is substantially the same as the fourth transistor T4 including 151d, the fourth source electrode 153d and the fourth drain electrode 155d. Therefore, repeated description is omitted.

The fifth transistor T5 and the sixth transistor T6 in the “C” region are located close to the third data line 171c unlike the third transistor T3 and the fourth transistor T4 in the “B” region. . That is, the fifth transistor T5 and the sixth transistor T6 in the “B” region have third data than the second data line 171b between the second data line 171b and the third data line 171c. It is located close to the line 171c.

The fifth source electrode 153e and the sixth source electrode 153f in the “C” region are respectively separated from the third source electrode 153c and the fourth source electrode 153d in the “B” region except for the data line connected thereto. Substantially the same. Therefore, repeated description is omitted.

The fifth source electrode 153e and the sixth source electrode 153f in the “C” region are the third source electrode 153c and the fourth source electrode 153d in the “B” region that are connected to the second data line 171b. Unlike the), it is connected to the third data line 171c.

The fifth pixel electrode 191e adjacent to the fourth pixel electrode 191d of the “B” region and the sixth pixel electrode 191f adjacent to the fifth pixel electrode 191e are positioned in the “C” region. The fifth pixel electrode 191e and the sixth pixel electrode 191f may be sequentially disposed along the first direction.

The fifth pixel electrode 191e and the sixth pixel electrode 191f of the “C” region may have the third pixel electrode 191c and the fourth pixel electrode 191d of the “B” region except for the positions of the extension and protrusions. Is substantially the same as Therefore, repeated description is omitted.

The extension part e1 formed in the fifth pixel electrode 191e in the “C” region, the extension part f1 and the protrusion f2 formed in the sixth pixel electrode 191f may include a third pixel electrode (“B”). The left and right sides of the extension part c1 formed in the 191c, the extension part d1 formed in the fourth pixel electrode 191d and the protrusion part d2 are disposed upside down.

Similarly to the region “B”, the extension part e1 of the fifth pixel electrode 191e extends without crossing the second data line 171b in the region “C”, so that the fifth contact hole H5 of the insulating film 193 is formed. ) Is connected to the fifth drain electrode 155e. In addition, the extension part f1 of the sixth pixel electrode 191f extends without crossing the second data line 171b and the sixth drain electrode 155f through the sixth contact hole H6 of the insulating layer 193. Connected. Therefore, in the “C” region, the fifth transistor T5 and the sixth pixel electrode 191e and the sixth pixel electrode 191f include the fifth source electrode 153e and the sixth source electrode 153f, respectively. It is connected to the third data line 171c through the transistor T6.

Similarly to the region “B”, the protrusion f2 of the sixth pixel electrode 191f extends and is electrically connected to the third contact region 139c through the third opening P3 in the region “C”.

In the present exemplary embodiment, a thin film transistor substrate is applied to a charge sharing driving method driven by three data lines by using a charge sharing transistor and a capacitor. However, the thin film transistor substrate includes three data lines. It can be applied to various driving methods, such as a driven charge pumping driving method.

4 is a diagram for describing a wiring arrangement of thin film transistor substrates according to an exemplary embodiment.

Referring to FIG. 4, the thin film transistor substrate includes a plurality of pixels PX arranged in rows. Each pixel PX includes a switching element Q having a pixel electrode PE and at least one transistor connected to the pixel electrode PE.

Three to the teuseon neighboring that there extend in the transverse direction between the row of the pixels _{(PX) (G 1, G} 2, G 3) are arranged, and three gate lines _{(G 1, G 2, G} 3) are different from each Connected to form a group and receive the same scan signal.

Data lines D _1c , D _1d , D _2c , D _2d , D _3c , D _3d , D _4c , D _4d ,…, D _mc , D extending in a vertical direction on the left side of the pixel PX _md ) are arranged, and on the right side, data lines D _1e , D _2e , D _3e , D _4e , and D _me extending in the vertical direction are arranged. The switching element Q is connected to the gate line G ₁ G _n and the data line D ₁ D _me .

For example, referring to the pixel PX of the first column of the first row, one gate line G ₁ and three data lines D _1c , D _1d , and D _1e are disposed per pixel PX. . Hereinafter, among the three data lines D _1c , D _1d , and D _1e , the ones disposed on the left side of the pixel PX are called the first data line D _1c and the second data line D _{1d in order} from the left. The right side of PX is called the third data line D _1e .

According to the present exemplary embodiment, the polarities of the neighboring pixels PX in the row direction are opposite to each other and the polarities of the neighboring pixels PX in the column direction are also opposite to each other in order to prevent vertical stir and vertical crosstalk. It is arranged to be reversed. That is, each pixel PX is arranged to have a polarity opposite to neighboring pixels PX in the row direction and the column direction. Such an arrangement may be achieved through various modifications, but the arrangement illustrated in FIG. 4 will be described below as an example.

The switching element Q of the pixel PX arranged in the first column and the first row is connected to the first data line D _1c . The switching element Q of the pixel PX disposed in the first column and the second row is connected to the second data line D _1d . The switching element Q of the pixel PX arranged in the first column and the third row is connected to the third data line D _1e . That is, the switching element Q of the pixel PX is sequentially connected to the first data line D _1c , the second data line D _1d , and the third data line D _1e along the first column.

The switching elements Q of the pixels PX arranged in the first row are all connected to the first data lines D _1c , D _2c ,..., D _mc . The switching elements Q of the pixels PX arranged in the second row are all connected to the second data lines D _1d , D _2d ,..., D _md . The switching elements Q of the pixels PX arranged in the third row are connected to the third data lines D _1e , D _2e ,..., D _me . That is, the switching element Q of the pixel PX is connected to the same kind of data line in the row direction.

Polarities of the voltages applied to the first data line, the second data line, and the third data line D _1c , D _1d , D _1e , D _2c , D _2d , D _2e ,..., D _mc , D _md , D _me Are opposite to each other between adjacent data lines. For example, as shown in FIG. 4, the first data line, the second data line, and the third data line D _1c , D _1d , D _1e , D _2c , D _2d , D _2e ,..., D _mc , D _md and D _me ) are alternately applied with positive and negative voltages in the row direction. In contrast, the first data line, the second data line, and the third data line D _1c , D _1d , D _1e , D _2c , D _2d , D _2e ,..., D _mc , D _md , D _{me are} arranged in a row direction. Negative (-) and positive (+) voltages may be applied alternately.

Here, a structure is used in the area "A" of FIG. 1 for the pixel PX connected to the first data line D _1c , D _2c ,..., D _mc through a switching element Q including a transistor. In detail, the pixel PX having the pixel electrode PE connected to the first data lines D _1c , D _2c ,..., And D _mc has a transistor connected to the first data lines D _1c , D _2c ,..., D _mc . And a space between the second data lines D _1d , D _2d ,..., And D _md , and an extension of the pixel electrode PE crosses the second data lines D _1d , D _2d ,..., And _md . Connected to the transistor. The pixel electrode PE and the transistor are divided into two, and one of the pixel electrodes may be connected through the down capacitor and the transistor.

The structure described in region “B” of FIG. 1 is used for the pixel PX connected to the second data lines D _1d , D _2d ,..., And _md through a switching element Q including a transistor. In addition, the structure described in region “C” of FIG. 1 is used for the pixel PX connected to the third data line D _1c , D _2c ,..., D _mc through a switching element Q including a transistor. .

FIG. 5 is a diagram for describing a wiring arrangement of the thin film transistor substrate illustrated in FIG. 1, according to an exemplary embodiment.

Similarly to FIG. 4, in the present exemplary embodiment, polarities of pixels PX adjacent to each other in the row direction are opposite to each other in order to prevent vertical stuttering and vertical crosstalk. It is arranged to be reversed. That is, the predetermined pixels PX are arranged with voltages opposite to neighboring pixels PX in the row direction and the column direction.

The switching element Q of the pixel PX disposed in the first row and the first column may be connected to the first data line D _1c . The switching element Q of the pixel PX disposed in the first row and the second column may be connected to the first data line D _2c . The switching element Q of the pixel PX disposed in the first row and the third column may be connected to the first data line D _3c . The switching element Q of the pixel PX disposed in the first row and the fourth column may be connected to the third data line D _4e .

The polarities of the voltages applied to the first data lines D _1c , D _2c ,..., D _mc and the second data lines D _1d , D _2d ,..., D _md are the third data lines D _1e , D _2e. , ..., D _me ) is the reverse of the polarity of the voltage applied. For example, as illustrated in FIG. 5, the positive polarity (+) is applied to the first data lines D _1c , D _2c ,..., And D _mc and the second data lines D _1d , D _2d _,. When a voltage of is applied, a negative voltage (−) is applied to the third data lines D _1e , D _2e ,..., And D _me . However, when the voltage of the negative polarity (−) is applied to the first data lines D _1c , D _2c ,..., D _mc , and the second data lines D _1d , D _2d _,. Positive voltages may be applied to the three data lines D _1e , D _2e ,..., And D _me .

Here, the structure described in region “A” of FIG. 1 is used for the pixel PX connected to the first data line D _1c , D _2c ,..., D _mc through a switching element Q including a transistor. do. In detail, the pixel PX having the pixel electrode PE connected to the first data lines D _1c , D _2c ,..., And D _mc has a transistor connected to the first data lines D _1c , D _2c ,..., D _mc . And a space between the second data lines D _1d , D _2d ,..., And D _md , and an extension of the pixel electrode PE crosses the second data lines D _1d , D _2d ,..., And _md . Connected to the transistor. The pixel electrode PE and the transistor are divided into two, and one of the pixel electrodes may be connected through the down capacitor and the transistor.

As mentioned above, although embodiments of the present invention have been described, the examples are merely examples for describing the protection scope of the present invention described in the claims and do not limit the protection scope of the present invention. In addition, the protection scope of the present invention can be extended to the technically equivalent range of the claims.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 is a cross-sectional view taken along the line II-II 'of FIG. 1.

FIG. 5 is a diagram for describing a wiring arrangement of thin film transistor substrates according to an exemplary embodiment.

110 substrate 121a first gate line

121b: second gate line 121c: third gate line

124a: first gate electrode 124b: second gate electrode

124c: third gate electrode 124d: fourth gate electrode

124e: fifth gate electrode 124f: sixth gate electrode

125a: first charge sharing gate electrode 125b: second charge sharing gate electrode

125c: third charge sharing gate electrode 126a: first charge sharing gate line

126b: second charge sharing gate line 126c: third charge sharing gate line

131a: first storage electrode line 131b: second storage electrode line

131c: third sustain electrode line 133a: first sustain electrode

133b: second sustain electrode 133c: third sustain electrode

134a: first lower electrode 134b: second lower electrode

134c: third lower electrode 135a: first upper electrode

135b: second upper electrode 135c: third upper electrode

139a: first contact region 139b: second contact region

139c: third contact region 140: gate insulating film

151a: first semiconductor pattern 151b: second semiconductor pattern

151c: third semiconductor pattern 151d: fourth semiconductor pattern

151e: fifth semiconductor pattern 151f: sixth semiconductor pattern

152a: first charge sharing semiconductor pattern 152b: second charge sharing semiconductor pattern

152c: third charge sharing semiconductor pattern 153a: first source electrode

153b: second source electrode 153c: third source electrode

153d: fourth source electrode 153e: fifth source electrode

153f: sixth source electrode 154a: first charge sharing source electrode

154b: first charge sharing source electrode 154c: first charge sharing source electrode

155a: first drain electrode 155b: second drain electrode

155c: third drain electrode 155d: fourth drain electrode

155e: fifth drain electrode 155f: sixth drain electrode

156a: first charge sharing drain electrode 156b: second charge sharing drain electrode

156c: third charge sharing drain electrode 160: ohmic contact layer

171a: first data line 171b: second data line

171c: third data line 180: protective film

191a: first pixel electrode 191b: second pixel electrode

191c: third pixel electrode 191d: fourth pixel electrode

191e: fifth pixel electrode 191f: sixth pixel electrode

193: insulating film

Claims

A plurality of pixels each including a pixel electrode and a transistor and arranged in a row;

A gate line extending corresponding to each pixel row and arranged spaced apart from each other in the column direction,

A first data line, a second data line, and a third data line, which extend in correspondence with each pixel column and are spaced apart in the row direction,

The first data line and the second data line are positioned to the left of the corresponding pixel column such that the first data line is arranged outside the second data line, and the third data line is located to the right of the corresponding pixel column. The thin film transistor substrate of which three gate lines are classified into one gate line group, and the same scan signal is applied to the gate line group.

In claim 1,

In a pixel having a transistor connected to the first data line, the transistor is formed in a region between the first data line and the second data line, and an extension of the pixel electrode is connected to the transistor across the second data line. Thin film transistor substrate.

In claim 2,

The region where the transistor is located is formed by refracting the second data line in a shape of becoming closer to and away from the first data line.

4. The method of claim 3,

And an insulating layer interposed between the extension portion of the pixel electrode and the second data line in an area where the extension portion of the pixel electrode crosses the second data line.

In claim 4,

And a source electrode of the transistor extends from the first data line.

In claim 5,

The transistor comprises a first transistor and a second transistor,

The pixel electrode includes a first pixel electrode and a second pixel electrode,

An extension of the first pixel electrode is connected to the drain electrode of the first transistor across the second data line.

The extension portion of the second pixel electrode is connected to the drain electrode of the second transistor across the second data line.

In claim 6,

A first storage electrode line intersecting the first data line and the second data line and extending across the first pixel electrode;

A first gate line crossing the first data line and the second data line and extending between the first pixel electrode and the second pixel electrode and connected to gate electrodes of the first transistor and the second transistor;

A first charge sharing gate line crossing the first data line and the second data line and extending between the first pixel electrode and the second pixel electrode;

A first charge sharing transistor having a gate electrode connected to the first charge sharing gate line and a source electrode connected to the second pixel electrode, and

And a first down capacitor connected between the drain electrode of the first charge sharing transistor and the first storage electrode line.

In claim 2,

And a transistor having a transistor connected to the second data line, wherein the transistor is positioned between the second data line and the third data line.

In claim 8,

And the transistor is located closer to the second data line than the third data line, and an extension of the pixel electrode is connected to the transistor without crossing the second data line.

The method of claim 9,

The transistor comprises a third transistor and a fourth transistor,

The pixel electrode includes a third pixel electrode and a fourth pixel electrode.

The source electrode of the third transistor and the source electrode of the fourth transistor are connected to the second data line, and the drain electrode of the third transistor and the drain electrode of the fourth transistor are respectively the third pixel electrode and the fourth transistor. A thin film transistor substrate connected to the pixel electrode.

In claim 10,

A second storage electrode line intersecting the first data line and the second data line and extending across the third pixel electrode;

A second gate line intersecting the first data line and the second data line and positioned between the third pixel electrode and the fourth pixel electrode and connected to gate electrodes of the third transistor and the fourth transistor;

A second charge sharing gate line intersecting the first data line and the second data line and positioned between the third pixel electrode and the fourth pixel electrode;

A second charge sharing transistor having a gate electrode connected to the second charge sharing gate line and a source electrode connected to the fourth pixel electrode, and

And a second down capacitor connected between the drain electrode of the second charge sharing transistor and the second storage electrode line.

In claim 1,

The pixel having the transistor connected to the third data line, the transistor is formed in the region between the second data line and the third data line.

In claim 12,

And the transistor is located closer to the third data line than the second data line, and an extension of the pixel electrode is connected to the transistor without crossing the second data line.

The method of claim 13,

The transistor comprises a fifth transistor and a sixth transistor,

The pixel electrode includes a fifth pixel electrode and a sixth pixel electrode.

The source electrode of the fifth transistor and the source electrode of the sixth transistor are connected to the third data line, and the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are respectively the fifth pixel electrode and the fifth electrode. A thin film transistor substrate connected to the six pixel electrode.

The method of claim 14,

A third storage electrode line intersecting the first data line and the second data line and extending across the fifth pixel electrode;

A third gate line intersecting the first data line and the second data line and positioned between the fifth pixel electrode and the sixth pixel electrode and connected to gate electrodes of the fifth transistor and the sixth transistor;

A third charge sharing gate line intersecting the first data line and the second data line and positioned between the fifth pixel electrode and the sixth pixel electrode;

A third charge sharing transistor having a gate electrode connected to the third charge sharing gate line and a source electrode connected to the sixth pixel electrode;

And a third down capacitor connected between the drain electrode of the third charge sharing transistor and the third sustain electrode line.

In claim 1,

The pixels neighboring in the row direction have opposite polarities, and the pixels neighboring in the column direction also have opposite polarities.

The method of claim 16,

The pixel may include a first pixel having a first transistor and a second transistor connected to the first data line;

A second pixel having a third transistor and a fourth transistor connected to the second data line, and

A third pixel having a fifth transistor and a sixth transistor connected to the third data line,

And a region in which the first transistor and the second transistor are positioned in the first pixel is between the first data line and the second data line.

The method of claim 17,

And a region in which the first transistor and the second transistor are positioned is refracted in a shape in which the second data line is far from the first data line and then reappears.

The method of claim 18,

And a region in which the third transistor and the fourth transistor are positioned in the second pixel is between the second data line and the third data line, and is located closer to the second data line than the third data line.

The method of claim 18,

And a region in which the fifth transistor and the sixth transistor are positioned in the third pixel is between the second data line and the third data line, and is located closer to the third data line than the second data line.