KR20100106819A - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same Download PDF

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Publication number
KR20100106819A
KR20100106819A KR1020090025034A KR20090025034A KR20100106819A KR 20100106819 A KR20100106819 A KR 20100106819A KR 1020090025034 A KR1020090025034 A KR 1020090025034A KR 20090025034 A KR20090025034 A KR 20090025034A KR 20100106819 A KR20100106819 A KR 20100106819A
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KR
South Korea
Prior art keywords
psoi
forming
sige
pattern
layer
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KR1020090025034A
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Korean (ko)
Inventor
이은숙
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090025034A priority Critical patent/KR20100106819A/en
Publication of KR20100106819A publication Critical patent/KR20100106819A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biotechnology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A semiconductor device and a forming method thereof are provided to reduce the leak current generated on the bottom of the reset gate and the bottom of the impurity area by forming the double PSOIPSOI(partial silicon on insulator) in the semiconductor device including the reset gate structure. CONSTITUTION: A semiconductor substrate(101) comprises an active area defined as an element isolation film(117). A recess gate pattern(130) is formed on the semiconductor substrate. A first PSOI(119) is formed on the lower part of the recess gate pattern. A second PSOI(121) is formed on the lower part of the impurity region(132).

Description

Semiconductor device and method for forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device capable of improving refresh and a method for forming the same.

As the design rule of the semiconductor device decreases, the doping concentration of the channel increases, and thus, the refresh characteristics of the device decrease as the short channel effect, the leakage current, and the electric field increase. That is, the problem of lowering the threshold voltage due to the shortening of the channel length due to the high integration of semiconductor devices has been intensified, and the short channel effect has been increased due to the reduction of the gate width. In particular, when the voltage of the drain region increases, the drain region interacts with the source region to lower the potential barrier toward the source region, thereby increasing the drain induced barrier lowering (DIBL) effect. Therefore, the gate voltage does not control the drain voltage, and when the extreme state is reached, the two depletion layers meet. As a result, electrons are driven to the drain region by the high electric field between the source region and the drain region. In addition, in order to maintain the threshold voltage according to the decrease in the gate width, the channel ion implantation concentration is increased and ions are implanted to control the punchthrough phenomenon, thereby increasing the electric field. Accordingly, there is a problem in that the fresh characteristics of the device is deteriorated.

Accordingly, a PSOI (Partial Silicon On Insulator, hereinafter referred to as a 'PSOI structure') is formed at the bottom of the source / drain to reduce refresh leakage and improve refresh. have. In detail, the semiconductor device of the planar gate structure including the PSOI structure according to the related art of FIG. 1 will be described with reference to the cross-sectional view.

As shown in FIG. 1, the active region 15 is defined by providing an isolation layer 13 on the semiconductor substrate 11, and a gate 17 structure is formed on the semiconductor substrate 11. In the active region 15 between the 17, an insulating film 19 and an impurity region 21 are formed. That is, the PSOI structure of the planar gate structure according to the related art is a structure in which refreshing is improved by the insulating film 19 provided under the impurity region 21 provided between the gates 17.

However, due to the high integration of semiconductor devices, the high-density integration of semiconductor devices has resulted in the reduction of device dimensions in high-density DRAM technology, which has a small gate pitch. I am getting it. In detail, a cross-sectional view illustrating a recess gate structure including a PSOI structure according to the related art of FIG. 2 will be described.

As shown in FIG. 2, the recessed gate structure refers to a device in which the length of the channel is increased in the vertical direction by etching a silicon surface to be a channel and forming a gate thereon. That is, a recess gate (not shown) is provided to fill a recess (not shown) on the semiconductor substrate 31 including a recess (not shown) provided in the active region 35 defined by the device isolation layer 33. 37). And an insulating film 39 and an impurity region 41 provided in the active region 35 between the recess gates 37. At this time, since the insulating layer 39 is formed to be spaced apart from the impurity region 41 by the recess gate structure, the refresh improvement effect obtained from the PSOI structure of the recess gate structure is higher than the refresh improvement effect obtained from FIG. 1. There is a problem that is significantly reduced.

In the semiconductor device including the recess gate structure, the PSOI cannot be formed under the source / drain junction due to the recess gate structure, thereby reducing the leakage current.

The semiconductor device of the present invention is spaced apart from a bottom of a recess gate to form a first partial silicon on insulator (PSOI) formed in an active region and a second partial silicon formed under an impurity region between the recess gate and the device isolation layer. on insulator). As a result, the leakage current generated under the recess gate and under the impurity region can be effectively blocked.

In this case, the first PSOI may be spaced apart from the recess gate by the channel region. This is to effectively block the leakage current while securing the portion where the channel of the recess gate is formed.

In addition, the width of the first PSOI may be within an error range of ± 100 μs compared with the recess gate width. This effectively blocks leakage current generated downward by the width of the recess gate.

In addition, the second PSOI may be spaced apart from the recess gate sidewalls by a channel region. This is to effectively block the leakage current while securing the channel region formed on the sidewall of the recess gate.

The first PSOI and the second PSOI may be formed in different layers. This means that even when the recess gates or the impurity regions are provided in different layers, leakage currents induced under the recess gates can be effectively blocked.

In this case, the different layer is characterized in that it comprises a first semiconductor layer formed on a semiconductor substrate and a second semiconductor layer formed on the first semiconductor layer,

The first PSOI is formed on the semiconductor substrate, and the second PSOI is formed on the first semiconductor layer.

In addition, the impurity region may be provided in the second semiconductor layer.

A method of forming a semiconductor device of the present invention comprises the steps of forming a SiGe pattern provided in each of the recessed region and the impurity predetermined region in the semiconductor substrate, the step of forming a semiconductor layer over the whole and the semiconductor substrate and the semiconductor layer Etching to form a predetermined region of the device isolation layer; removing the SiGe pattern; and forming an oxide film on the predetermined region of the device isolation layer and the region from which the SiGe pattern is removed, thereby forming a first partial silicon on insulator (PSOI) and a first region. It characterized in that it comprises the step of forming a partial silicon on insulator (PSOI).

The forming of the SiGe pattern may include forming a first SiGe layer on a semiconductor substrate, forming a photoresist pattern on the first SiGe layer, and using the photoresist pattern as an etching mask. Etching to form a first SiGe pattern, forming a first semiconductor layer on the first SiGe pattern, and forming a second SiGe layer on the first semiconductor layer and on the second SiGe layer And forming a second SiGe pattern by etching the second SiGe layer using the photoresist pattern as an etching mask.

The first SiGe pattern may be formed under the recess gate predetermined region.

The second SiGe pattern may be formed under the impurity predetermined region.

In addition, the step of removing the SiGe pattern is characterized in that it is performed by a dip out process. As a result, only the SiGe pattern provided in the semiconductor layer can be easily removed.

The method may further include forming a recess gate in the recess gate predetermined region after forming the first PSOI and the second PSOI.

The method may further include forming an impurity region in the impurity predetermined region by performing an ion implantation process on the semiconductor layer using the recess gate as a mask after forming the recess gate. As a result, the first PSOI is formed under the region where the recess gate is formed to weaken the field under the recess gate to reduce the leakage current, and the second PSOI is ion implanted to diffuse the ions under the second PSOI. It is possible to improve the refresh rate by reducing the leakage current under the impurity region.

The present invention provides an effect of improving refresh by forming a double PSOI in a semiconductor device including a recess gate structure to reduce leakage current generated under the recess gate and under the impurity region.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3 is a cross-sectional view illustrating a semiconductor device according to the present invention, and FIGS. 4A to 4D are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

As shown in FIG. 3, the semiconductor device of the present invention includes a recess gate pattern 130 provided on a semiconductor substrate 101 including an active region defined as an isolation layer 117, and a recess gate pattern ( The device isolation layer is formed under the sidewalls of the recess gate pattern 130 by the first PSOI 119 formed to have the same width as the recess gate pattern 130 and the channel region of the recess gate pattern 130. And a second PSOI 121 spaced apart from the 117 side and provided under the impurity region 132. As a result, the first PSOI 119 weakens the electric field under the recess gate pattern 130 to reduce the leakage current, and the second PSOI 121 reduces the leakage current of the impurity region 132 to improve refresh. Can be.

As shown in FIGS. 4A to 4B, the first SiGe layer 103 is grown on the semiconductor substrate 101. Then, a photoresist film (not shown) is coated on the first SiGe layer 103, a photoresist pattern (not shown) is formed through an exposure and development process using an exposure mask, and then the first SiGe layer ( 103 is etched to form a first SiGe pattern 105. In this case, the first SiGe pattern 105 may be disposed below the recess gate (not shown) formed in a subsequent process. In addition, it is preferable that the width w1 of the first SiGe pattern 105 is equal to or equal to the width w2 of the recess gate pattern (not shown) within an error range of ± 100 ms. In addition, the first SiGe pattern 105 may be spaced 100 Å away from the recess gate pattern (not shown). This is to reflect the width of the channel region formed under the recess gate pattern so that the first SiGe pattern 105 is not formed in the channel region so that the leakage current can be accurately blocked.

As shown in FIGS. 4C to 4D, the same semiconductor layer 107 as the semiconductor substrate 101 is grown on the semiconductor substrate 101 including the first SiGe pattern 105. Here, the semiconductor layer 107 is preferably Si. Next, a second SiGe layer 109 is grown on the semiconductor layer 107. Then, a photoresist film (not shown) is coated on the second SiGe layer 109, and a photoresist pattern (not shown) is formed through an exposure and development process using an exposure mask, and then a second SiGe layer (as an etching mask) is formed. 109 is etched to form a second SiGe pattern 111. In this case, it is preferable that the second SiGe pattern 111 is provided below the source / drain junction (not shown) formed in a subsequent process. It is also desirable to be at least 100 microns away from the recess gate channel region. The SiGe pattern 109 is provided so as to be spaced apart from the gate channel region in order to prevent the pattern 109 from being formed in the channel region so as to reliably block the leakage current.

As shown in FIGS. 4E to 4F, the semiconductor layer 113 is grown on the semiconductor layer 107 including the second SiGe pattern 111. In this case, the semiconductor layer 113 is preferably Si. Next, although not shown, after forming a photoresist pattern defining the device isolation layer, the trench 115 is formed by etching the semiconductor layer 113, the semiconductor layer 107, and the semiconductor substrate 101 using the etching mask as an etching mask. . Here, after the trench 115 is formed, the regions 105a and 111a from which the first and second SiGe patterns 105 and 111 are removed through the wet dip out are formed. Although not shown, the first and second SiGe patterns 105 and 111 are removable because they are opened behind the cross section shown.

As shown in FIGS. 4G to 4H, an oxide film is buried in regions 105a and 111a from which the trench 115, the first SiGe pattern 105, and the second SiGe pattern 111 are removed. To form. In this case, the oxide film is buried in regions in which the first and second SiGe patterns 105 and 111 are removed to define the first PSOI 119 and the second PSOI 121, respectively. Subsequently, although not shown, after the photoresist is coated on the entire surface including the semiconductor layer 113 and the device isolation layer 117, a photoresist pattern defining a gate region is formed, and the semiconductor layer 107 is used as an etching mask. The recess 123 is formed by etching the semiconductor layer 113 and the device isolation layer 117.

As shown in FIG. 4I, a gate polysilicon layer 125 and a tungsten silicide layer 127 are sequentially formed as a gate oxide layer (not shown) and a gate conductive layer on the recess 123, and a tungsten silicide layer is formed. A gate hard mask layer 129 is formed on the upper portion 127. Although not shown, a photoresist pattern (not shown) defining a recess gate region is formed on the gate hard mask layer 129, and then the gate hard mask layer 129 is etched using the etching mask as an etching mask. The tungsten silicide layer 127 and the gate polysilicon layer 125 are etched using the gate hard mask layer 129 as an etch mask to form a recess gate pattern 130. Next, an impurity region 132 is formed by performing an ion implantation process on the semiconductor layer 113. Here, the ion implantation process is performed using the recess gate pattern 130 as a mask, and the ions implanted into the semiconductor layer 113 are diffused to the second PSOI 121 so that the thickness of the impurity region 132 is the semiconductor layer 113. It is preferable to become from the uppermost side of) to the upper side of the 2nd PSOI 121. As a result, the second PSOI 121 may be provided directly under the impurity region 132 to effectively block the leakage current.

1 is a cross-sectional view of a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a recess gate structure including a PSOI structure according to the prior art.

3 is a cross-sectional view showing a semiconductor device according to the present invention.

4A to 4I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Claims (15)

A first partial silicon on insulator (PSOI) formed in the active region spaced apart from the recess gate and a second partial silicon on insulator (PSOI) formed under the impurity region between the recess gate and the device isolation layer. A semiconductor device, characterized in that. The method according to claim 1, The first PSOI is, And spaced apart from the recess gate by a channel region. The method according to claim 1, The width of the first PSOI is, A semiconductor device, characterized in that within the error range of ± 100kHz compared to the recess gate width. The method according to claim 1, The second PSOI, And spaced apart from the recess gate sidewalls by a channel region. The method according to claim 1, And the first PSOI and the second PSOI are formed on different layers. The method according to claim 5, The different layers, And a first semiconductor layer formed on the semiconductor substrate and a second semiconductor layer formed on the first semiconductor layer. The method according to claim 6, The first PSOI is formed on the semiconductor substrate, and the second PSOI is formed on the first semiconductor layer. The method according to claim 6 or 7, The impurity region is, A semiconductor device, characterized in that provided in the second semiconductor layer. Forming a SiGe pattern on the lower portion of the recess predetermined region and the impurity predetermined region in the semiconductor substrate; Forming a semiconductor layer over the whole; Etching the semiconductor substrate and the semiconductor layer to form a device isolation region; Removing the SiGe pattern; And Forming an oxide film in the predetermined region of the device isolation layer and the region from which the SiGe pattern is removed to form a first partial silicon on insulator (PSOI) and a second partial silicon on insulator (PSOI), respectively. Formation method of the device. The method according to claim 9, Forming the SiGe pattern, Growing a first SiGe layer on a semiconductor substrate; Forming a photoresist pattern on the first SiGe layer; Etching the first SiGe layer using the photoresist pattern as an etching mask to form a first SiGe pattern; Forming a first semiconductor layer on the first SiGe pattern; Forming a second SiGe layer on the first semiconductor layer; Forming a photoresist pattern on the second SiGe layer; And And etching the second SiGe layer to form a second SiGe pattern by using the photoresist pattern as an etching mask. The method according to claim 10, The first SiGe pattern is, And forming the recess gate under the predetermined region. The method according to claim 10, The second SiGe pattern is, And forming a lower portion of the impurity predetermined region. The method according to claim 9, Removing the SiGe pattern, A method of forming a semiconductor device, characterized in that performed in a dip out process. The method according to claim 9, After forming the first PSOI and the second PSOI, And forming a recess gate in the recess gate predetermined region. The method according to claim 14, After forming the recess gate, And forming an impurity region in the impurity predetermined region by performing an ion implantation process on the semiconductor layer using the recess gate as a mask.
KR1020090025034A 2009-03-24 2009-03-24 Semiconductor device and method for forming the same KR20100106819A (en)

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