KR20100106771A - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE: A nonvolatile semiconductor memory device manufacturing method is provided to improve the operation error of nonvolatile memory device by implementing the flow of current easily in string structure from the bit line. CONSTITUTION: A select line is formed on the top of a semiconductor substrate(101) including an element isolation film. A first junction area(101a) is formed on the active area between the first and second select lines which are adjacent to each other among select lines. A second junction area(101b) is formed on one side or on the other side of first junction areas.

Description

Manufacturing method of nonvolatile semiconductor memory device

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device associated with a cell array of a NAND flash memory device.

Recently, development of NAND flash memory devices having high capacity and easy integration among nonvolatile memory devices has been actively progressed. The memory cell array of the NAND flash memory device includes a string structure arranged in a matrix form. Each string structure includes a drain select transistor having a drain connected to a bit line, a source select transistor having a source connected to a common source line, a plurality of memory cells connected in series between the drain select transistor and the source select transistor. The string structures described above may be connected through the drain of the drain select transistor or the source of the source select transistor.

More specifically, string structures arranged side by side in the same active region among semiconductor substrates including alternately arranged device isolation layers and active regions are connected through a source or a drain. For example, among the first to third string structures arranged side by side within the same active region, the drain of the drain select transistor included in the first string structure is connected to the drain of the drain select transistor included in the second string structure, The source of the source select transistor included in the second string structure is connected to the source of the source select transistor included in the third string structure.

Meanwhile, in order to prevent an error from occurring when the NAND flash memory device is operated, current communication from the bit line to the string structure should be smoothly performed. The bit line and string structure is connected through a drain contact plug connecting the drain and bit line of the drain select transistor. At this time, the drain contact plugs are not arranged in a line to prevent a bridge between the drain contact plugs as the NAND flash memory device is highly integrated. As a result, current communication from the bit line to the string structure may not be performed smoothly, and an error may occur in the operation of the NAND flash memory device.

Hereinafter, the reason why an error occurs in the operation of the NAND flash memory device as the drain contact plugs are not arranged in a line will be described with reference to FIG. 1. 1 is a cross-sectional view illustrating a portion of a memory cell array of a conventional NAND flash memory device. Hereinafter, an area where the drain select line and the word line are formed will be described.

Referring to FIG. 1, a gate of a NAND flash memory device is formed on an upper surface of a semiconductor substrate 1 with a gate insulating film 3 interposed therebetween, and is used for the charge storage film 5, the dielectric film 7, and the control gate. The conductive film 9 is formed in a stacked structure. The conductive film 9 for the control gate of the stacked gates is connected to become a drain select line DSL or a word line WL. In addition, a gate hard mask pattern 11 used as an etch barrier may remain in the uppermost layer of the stacked gates in the etching process for forming the stacked gates.

After the formation of the stacked gate, the impurity ions are implanted using the drain select line DSL and the word line WL as masks. Accordingly, the drain 1D is formed in the semiconductor substrate 1 between the adjacent drain select lines DSL. The cell junction region 1C is formed in the semiconductor substrate 1 on both sides of the word line WL.

After formation of the drain 1D and the cell junction region 1C, spacers 13 are formed on both side walls of the stacked gate. The spacer 13 is formed by depositing a spacer film on the surface of the gate hard mask pattern 11, the surfaces of the stacked gates, and the surface of the semiconductor substrate 1, and then etching the spacer film by an etching process such as etch back. Is formed. Meanwhile, the space between the drain select lines DSL is wider than the space between the word lines WL and the space between the word line WL and the drain select line DSL. Therefore, the spacer layer fills the space between the word lines WL and the space between the word line WL and the drain select line DSL, but does not fill the space between the drain select lines DSL. That is, the thickness of the spacer film formed on the surface of the semiconductor substrate 1 between the drain select lines DSL is between the word lines WL and between the word lines WL and the drain select line DSL. It is relatively thinner than the thickness of the spacer film formed on the surface of (1). Therefore, the semiconductor substrate 1 between the drain select lines DSL may be etched during the etch-back process to form the spacers 13 on both sidewalls of the stacked gate, so that the drain 1D may be lost. .

Subsequently, in a subsequent process, insulating layers including the etch stop layer 15 and the interlayer insulating layers 17a and 17b are formed, and then a contact hole 18 exposing the drain 1D is formed. In this case, the contact holes 18 are not arranged in a line with other contact holes not shown in the drawing, and are formed to expose one side of the drain 1D. Thereafter, the contact hole 18 is filled with a conductive material to form a drain contact plug 19, and a bit line BL connected to the drain contact plug 19 is formed.

As described above, as the drain 1D is lost in the process of forming the spacer 13, it is difficult to smoothly communicate current flowing from the bit line BL to the string structure via the drain 1D. In particular, as the contact hole 18 defining the region where the drain contact plug 19 is formed is formed at one side of the drain 1D, the current flowing in the string structure toward the drain select line DSL is relatively far apart. It is difficult to communicate smoothly. As a result, an error occurs in the operation of the nonvolatile memory device.

The present invention provides a method of manufacturing a nonvolatile memory device that facilitates current communication from a bit line to a string structure so that an error occurs in an operation of the nonvolatile memory device.

A method of manufacturing a nonvolatile memory device according to the present invention includes forming select lines crossing an active region and a device isolation layer on an upper portion of a semiconductor substrate including alternately arranged active regions and device isolation layers, wherein one of the select lines Forming first junction regions in active regions between adjacent first and second select lines, forming second junction regions on one side or the other of the first junction regions, forming spacers on both sides of the select lines Forming an insulating film on the semiconductor substrate on which the select lines, the first and second junction regions and the spacer are formed, and contact holes exposing opposite sides of the region in which the second junction region is formed. Forming a third bonding region in the first bonding region exposed through the contact holes, forming a contact plug in the contact hole Forming a metal wire connected to the contact plug.

In the forming of the select lines, word lines parallel to the select line are formed on both sides of the first and second select lines, and in the forming of the first junction regions, cell junction regions are formed in the active regions on both sides of the word line.

The first and second select lines are drain select lines.

The metal wiring is a bit line.

The second bonding regions are alternately formed at one side of the first bonding region and the other side of the first bonding region.

The forming of the second junction regions may include forming a photoresist pattern opening one side or the other side of the first junction regions, implanting impurity ions into the first junction region using the photoresist pattern as a mask, and photoresist pattern. Removing the step.

The depth of the second junction region and the third junction region is formed deeper than the depth of the first junction region.

In the present invention, even when the first junction region between the select lines is lost during the formation of the spacer, the first junction region lost through additional formation of the second and third junction regions may be compensated for. As a result, the present invention can facilitate the current communication from the bit line to the string structure, thereby improving the operation error of the nonvolatile memory device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a layout diagram illustrating a nonvolatile memory device according to the present invention. In particular, FIG. 2 illustrates a NAND flash memory device. Hereinafter, an area where the drain select line and the word line are formed will be described.

Referring to FIG. 2, a memory cell array of a NAND flash memory device according to the present invention includes word lines WL and first and second drain select lines DSL1 and DSL2 arranged side by side. The first and second drain select lines DSL1 and DSL2 are formed adjacent to each other, and word lines WL are formed on both sides of the first and second drain select lines DSL1 and DSL2. The first and second drain select lines DSL1 and DSL2 and the word lines WL may be disposed on the semiconductor substrate including the device isolation region B and the active region A, which are alternately arranged. And intersect with B) and active region (A).

The device isolation region B of the semiconductor substrate is a region in which the device isolation film 102 is formed. Further, drains are formed in the active region A between the first and second drain select lines DSL1 and DSL2 among the active regions A of the semiconductor substrate, and active regions A on both sides of the word lines WL. Cell junction regions are formed.

The drains are respectively connected to the word lines WL and the bit lines BL formed to intersect the first and second drain select lines DSL1 and DSL2. The drain and the bit line BL are connected to each other through a drain contact plug formed in the drain contact hole 123. The drain contact holes 123 defining regions in which the drain contact plugs are to be formed are not arranged in a line to prevent bridges between contact plugs due to high integration of the NAND flash memory device. That is, the drain contact holes 123 include first and second drain contact holes 123a and 123b that are alternately arranged. The first drain contact hole 123a is formed adjacent to the first drain select line DSL1, and the second drain contact hole 123b is formed adjacent to the second drain select line DSL2.

Hereinafter, a method of manufacturing a NAND flash memory device according to the present invention will be described with reference to FIGS. 2 and 3A to 3F. 3A to 3F are cross-sectional views taken along the line "I-I '" shown in FIG.

2 and 3A, a gate insulating film 103, a charge storage film 105, and a dielectric are formed on a semiconductor substrate 101 on which a well is formed and an ion implantation process for adjusting a threshold voltage is performed. A film 107 and a conductive film 109 for control gate are formed. The gate insulating film 103 may be formed of an oxide film. The charge storage layer 105 may be formed of a polysilicon layer. For example, the charge storage film 105 may be formed of a doped polysilicon film, or may be formed by stacking a doped polysilicon film and an undoped polysilicon film.

On the other hand, although not shown in the cross section of the figure, an element isolation film (not shown) is formed on the semiconductor substrate 101. For example, after forming the gate insulating layer 103 and the charge storage layer 105, the device isolation layer 102 may form a trench, and may be formed by filling an oxide layer in the trench. As a result, the device isolation layer 102 is formed in the device isolation region B of the semiconductor substrate 101, and the gate insulating layer 103 and the charge storage layer 105 remain on the active region A of the semiconductor substrate 101. can do.

As described above, after forming the device isolation film 102, the gate insulating film 103, and the charge storage film 105, the dielectric film 107 is formed on the surfaces of the device isolation film 102 and the charge storage film 105. Can be. The dielectric film 107 can be formed by stacking an oxide film, a nitride film and an oxide film. In addition, the dielectric layer 107 may include a dielectric layer contact hole that exposes the charge storage layer 105 in a region where a select line is to be formed. The dielectric film contact hole may be a hole when the charge storage film 105 and the control gate conductive film 109 are electrically connected to each other. The control gate conductive film 109 may be formed as a single film of a polysilicon film or a double film in which a polysilicon film and a metal film are stacked.

Subsequently, the gate hard mask pattern 111 is formed on the control film conductive film 109. Subsequently, in the etching process using the gate hard mask pattern 111 as an etching barrier, the control gate conductive film 109, the dielectric film 107, and the charge storage film 105 are exposed until the gate insulating film 103 is exposed. Etch As a result, a stacked gate pattern including the word lines WL and the first and second drain select lines DSL1 and DSL2 is formed. That is, the control gate conductive layer 109 is etched to form word lines WL crossing the active region A and the isolation layer 102, and first and second drain select lines DSL1 and DSL2. . In addition, the charge storage layer 105 remaining on the active region A is etched and separated into a plurality of patterns on the upper portion of the active region A. FIG. Although not shown in the drawings, source select lines facing the first or second drain select lines DSL1 and DSL2 may be formed at the same time with a plurality of word lines WL interposed therebetween.

Thereafter, impurity ions are implanted into the active regions A of the semiconductor substrate 101 using the word lines WL and the first and second drain select lines DSL1 and DSL2 as masks. As a result, cell junction regions 101L are formed in the active regions A at both sides of the word lines WL, and first regions are formed in the active regions A between the first and second drain select lines DSL1 and DSL2. Bonding regions 101a are formed. The impurity ions may include n-type impurity ions such as phosphorus (P) when the memory cell and the select transistor of the NAND flash memory device to be formed are NMOS. Although not shown, a source region may be formed at the same time as the cell junction region 101L and the first junction region 101a between the source select lines.

2 and 3B, one side or the other side of the first junction regions 101a is formed on the semiconductor substrate 101 on which the word lines WLs and the first and second drain select lines DSL1 and DSL2 are formed. A photoresist pattern 113 is formed to open. At this time, the photoresist pattern 113 alternates one side or the other side of the first bonding regions 101a in consideration of the first and second contact holes being formed alternately to prevent the bridge of the contact plug in a subsequent process. It is preferably formed to be open.

Thereafter, impurity ions are implanted using the photoresist pattern 113 as a mask to form second junction regions 101b on one side or the other side of the first junction regions 101a. In this case, the second bonding regions 101b are alternately formed at one side of the first bonding region 101a and the other side of the first bonding region 101b. In other words, the second junction regions 101b are alternately adjacent to the first drain select line DSL1 and the second drain select line DSL2. The second junction region 101a is formed to compensate for the first junction region 101a lost in a subsequent spacer forming process, and is formed using the same impurities as those implanted in the first junction region 101a. It is preferable to form deeper than the 1st bonding region 101a. Also, forming the second bonding regions 101b on one side or the other side of the first bonding regions 101a is compensated for through the third bonding region formed in a subsequent process among the first bonding regions 101a lost during the spacer forming process. To compensate for the difficult part. In order to form these second junction regions 101b, it is preferable to implant impurity ions at a dose of 5.0E13.

2 and 3C, spacers 115 may be formed to protect sidewalls of the word lines WL and the first and second drain select lines DSL1 and DSL2. In this case, since the space between the word lines WL is smaller than the space between the first and second drain select lines DSL1 and DSL2, the space between the word lines WL may be filled by the spacer 115. .

The spacer 115 forms a spacer film on the surface of the semiconductor substrate 101 including the surface of the stacked gate pattern including the first and second drain select lines DSL1 and DSL2, and then the spacer film forms the first and second drain selects. It may be formed by performing an etching process so as to remain on the sidewalls of the lines DSL1 and DSL2. The spacer film can be formed using an insulating film such as an oxide film. The etching process may be performed by an etch-back or a full surface etching process. In this case, since the interval between the first and second drain select lines DSL1 and DSL2 is wider than the interval between the word lines WL, the first junction region between the first and second drain select lines DSL1 and DSL2. 101a and the second junction region 101b may be lost. At this time, since the second junction region 101b is formed deeper than the first junction region 101a, the second junction region 101b may remain at a sufficient thickness to facilitate current communication even after the formation of the spacer 115. On the other hand, the portion of the first bonding region 101a that is lost opposite the second bonding region 101b may be compensated in a subsequent process of forming the third bonding region.

Since the spacers 115 remain between the word lines WL so that the semiconductor substrate 101 is not exposed, the cell junction region 101L is not lost.

After the formation of the spacers 115, insulating films are formed. The insulating layers may include an etch stop layer 117 and first and second interlayer insulating layers 119 and 121. The etch stop layer 117 is formed along the surfaces of the spacers 115 and the stacked gate semiconductor substrate 101. The etch stop layer 117 is formed to prevent the sidewall of the stacked gate from being exposed during the etching process of forming a subsequent contact hole, and may be formed of a nitride layer. The first and second interlayer insulating layers 119 and 121 are formed on the etch stop layer 117. The first and second interlayer insulating films 119 and 121 may be formed of oxide films. Although not illustrated, before forming the second interlayer insulating layer 121, the first interlayer insulating layer 119 and the etch stop layer 117 may be formed to form a source contact line in contact with the source region between the source select lines. After forming a source contact hole through which the source region is exposed, a source contact line may be formed inside the source contact hole.

2 and 3D, the drain contact hole 123 exposing the first junction region 101a positioned opposite the second junction region 101b is formed. Here, the drain contact hole 123 exposes the first junction regions 101a which are opposite to the second junction regions 101b, and the second junction regions 101b are connected to the first drain select line DSL1. Alternately adjacent to the second drain select line DSL2. Accordingly, the drain contact hole 123 includes a first drain contact hole 123a adjacent to the first drain select line DSL1 and a second drain contact hole 123b adjacent to the second drain select line DSL2. The first drain contact hole 123a and the second drain contact hole 123b are alternately arranged.

Thereafter, impurity ions are implanted into the first junction region 101a exposed through the drain contact hole 123 to form a third junction region 101c. The third junction region 101c not only compensates for the first junction region 101a lost during the spacer 115 formation process but also compensates for the first junction region 101a lost during the drain contact hole 123 formation process. can do. In addition, the third junction region 101c is formed using the same impurities as the impurities injected into the first junction region 101a, and is preferably formed deeper than the first junction region 101a.

By forming the third junction region 101c described above, the drain region 101D including the first to third junction regions 101a, 101b, and 101c is formed.

2 and 3E, the drain contact hole 123 is formed by filling the inside of the drain contact hole 123 with a conductive material. More specifically, the drain contact plug 125 may have a conductive material having a sufficient thickness to fill the drain contact hole 123 inside the second interlayer insulating layer 121, and then planarize the exposed second interlayer insulating layer 121. It can be formed by carrying out the process. Here, the planarization process may be performed by a chemical mechanical polishing (CMP) process. Thus, the drain contact plug 125 is connected to the third junction region 101c of the drain region 101D.

2 and 3F, a bit line BL connected to the drain contact plug 125 is formed on the second interlayer insulating layer 121.

As described above, in the present invention, even when the first junction region 101a is lost during the formation of the spacer 115, the first junction region 101a lost through the additional formation of the second and third junction regions 101b and 101c. ) Can be compensated. Accordingly, the present invention can facilitate the current communication from the bit line BL to the string structure. Meanwhile, in the present invention, even if the drain contact hole 123 is formed to be biased on one side or the other side of the first junction region 101a, the drain select line DSL1 or DSL2 is relatively far apart through the second junction region 101b. The current flowing in the string structure can be smoothly communicated. As a result, a problem that an error occurs in the operation of the nonvolatile memory device can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view showing a portion of a memory cell array of a conventional NAND flash memory device.

2 is a layout for explaining a nonvolatile memory device according to the present invention;

3A-3F are cross-sectional views cut along the line " I-I " shown in FIG.

<Explanation of symbols for the main parts of the drawings>

101: semiconductor substrate 101a: first junction region

101b: second junction region 101c: third junction region

101L: cell junction region 102: device isolation film

103: gate insulating film 105: charge storage film

107 dielectric film 109 conductive film for control gate

111: gate hard mask pattern 113: photoresist pattern

115: spacer 117: etching stop film

119: first interlayer insulating film 121: second interlayer insulating film

123: drain contact hole

Claims (7)

Forming select lines crossing the active region and the device isolation layer on the semiconductor substrate including alternately arranged active regions and the device isolation layers; Forming first junction regions in the active regions between first and second select lines adjacent to each other of the select lines; Forming second bonding regions on one side or the other side of the first bonding regions; Forming spacers on both sides of the select lines; Forming an insulating layer on the semiconductor substrate on which the select lines, the first and second junction regions, and the spacer are formed; Forming contact holes exposing opposite sides of the first bonding region in which the second bonding region is formed; Forming a third junction region in the first junction region exposed through the contact holes; Forming a contact plug in the contact hole; And Forming a metal wire connected to the contact plug. The method of claim 1, In the forming of the select lines, word lines parallel to the select line are formed on both sides of the first and second select lines, And forming cell junction regions in the active regions on both sides of the word line in the forming of the first junction regions. The method of claim 1, The first and second select lines are drain select lines. The method of claim 1, And the metal wiring is a bit line. The method of claim 1, And the second junction regions are alternately formed at one side of the first junction region and the other side of the first junction region. The method of claim 1, Forming the second junction regions is Forming a photoresist pattern opening one side or the other side of the first bonding regions; Implanting impurity ions into the first junction region using the photoresist pattern as a mask; And And removing the photoresist pattern. The method of claim 1, The depth of the second junction region and the third junction region is formed deeper than the depth of the first junction region.

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