KR20100091804A - Metal wiring of semiconductor device and method of manufacturing the same - Google Patents

Metal wiring of semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20100091804A
KR20100091804A KR1020090011168A KR20090011168A KR20100091804A KR 20100091804 A KR20100091804 A KR 20100091804A KR 1020090011168 A KR1020090011168 A KR 1020090011168A KR 20090011168 A KR20090011168 A KR 20090011168A KR 20100091804 A KR20100091804 A KR 20100091804A
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KR
South Korea
Prior art keywords
film
copper
metal
wiring
forming
Prior art date
Application number
KR1020090011168A
Other languages
Korean (ko)
Inventor
하가영
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090011168A priority Critical patent/KR20100091804A/en
Publication of KR20100091804A publication Critical patent/KR20100091804A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: The metal wiring of the semiconductor device and a method of formation thereof minimizes the hillock phenomenon of the copper layer. The property and reliability of the copper routing are improved. CONSTITUTION: The insulating layer(104) having the routing region on the semiconductor substrate(102) is formed. The barrier film(106) is formed in the surface of the routing region. The buffer layer is formed in the barrier film surface. The metal layer is buried within the routing region. The seed layer is allowed in between the buffer layer and metal layer.

Description

Metal wiring of semiconductor devices and method of forming the same {METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring of a semiconductor device and a method of forming the same. More particularly, the metal wiring and formation of a semiconductor device capable of securing the characteristics and reliability of a copper wiring by minimizing the hillock phenomenon of the copper film. It is about a method.

In general, a metal element is formed in the semiconductor element to electrically connect the element and the element, or the interconnection and the interconnection, and a contact plug is formed to connect the upper metal interconnection and the lower metal interconnection. On the other hand, according to the trend of high integration of semiconductor devices, design rules are reduced, and the aspect ratio of the contact holes in which the contact plugs are formed is gradually increasing. Therefore, the difficulty and importance of the process of forming the metal wiring and contact plug is increasing.

Aluminum (Al) and tungsten (W), which have excellent electrical conductivity, have been mainly used as the material for the metallization, and in recent years, the RC signal delay in high-integrated high-speed operation devices has much higher electrical conductivity and lower resistance than aluminum and tungsten. Research into using copper (Cu) as a next-generation metallization material that can solve the problem is being conducted.

However, since copper is not easily etched in the form of wiring, a new process technology called damascene is used. The damascene metal wiring process is a technique of forming a wiring formation region by etching an interlayer insulating film, and forming the metal wiring by filling the wiring formation region with a copper film.

Hereinafter, a method of forming metal wirings of a semiconductor device according to the prior art will be briefly described.

After the insulating film is formed on the semiconductor substrate, the insulating film is etched to form a wiring formation region. After forming a diffusion barrier on the insulating film including the surface of the wiring formation region, a copper film is deposited to fill the wiring formation region on the diffusion barrier. The copper film and the diffusion barrier layer formed on the insulating film are removed by a chemical mechanical polishing (CMP) process to form metal wiring in the wiring formation region. Subsequently, a capping film is formed on the metal wiring and the insulating film.

However, in the above-described prior art, the capping film is formed by a pre-enhanced chemical vapor deposition (PE-CVD) process at a relatively low temperature. Is generated.

This thermal compressive stress causes deformation in the vertical direction in the copper film, which causes the copper film to expand on grain boundaries and cause a hillock phenomenon.

Furthermore, when the hillock phenomenon of the copper film is intensified, the resistance of the metal wiring formed of the copper film is increased, resulting in deterioration of device characteristics and reliability.

The present invention provides a metal wiring and a method for forming the semiconductor device that can prevent the hillock phenomenon to improve the resistance of the copper wiring.

In addition, the present invention provides a metal wiring of the semiconductor device and a method for forming the semiconductor device capable of preventing the hillock phenomenon and thereby improving the resistance of the copper wiring, thereby preventing deterioration of device characteristics and reliability.

Metal wiring of a semiconductor device according to an embodiment of the present invention, a semiconductor substrate; An insulating film formed on the semiconductor substrate and having a wiring formation region; A barrier film formed on a surface of the wiring formation region; A buffer film formed on the barrier film surface; And a metal film embedded in the wiring forming region.

The barrier film includes at least one of TaN and Ta.

The buffer film includes a mixed material of Cu (x) Ta (1-x) (X = 0.5 to 0.9).

And a seed film interposed between the buffer film and the metal film.

The seed film includes a copper film.

The metal film includes a copper film.

In addition, the method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention, forming an insulating film having a wiring forming region on a semiconductor substrate; Forming a barrier film on a surface of the wiring formation region; Forming a buffer film on the barrier film surface; And embedding a metal film in the wiring forming region.

The barrier film is formed of any one or more of TaN and Ta.

The buffer film is formed of a mixed material of Cu (x) Ta (1-x) (X = 0.5 to 0.9).

And forming a seed film on the buffer film between forming the buffer film and filling the metal film.

The seed film is formed of a copper film.

The metal film is formed of a copper film.

The present invention relates to Cu (x) Ta (1-x) on the barrier film. By forming the formed buffer film to form a copper metal wiring, during the damascene process for forming a copper metal wiring, the crystal structure between the barrier film and the copper film is homogenized to reduce the defect density in the copper film. In this way, the compressive stress applied to the copper film may be dispersed by the insulating film adjacent to the copper film.

Accordingly, the present invention can prevent the hillock phenomenon of the copper film and improve the resistance of the copper wiring, thereby improving the device characteristics and reliability.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a metal wiring of a semiconductor device according to an embodiment of the present invention.

As illustrated, the metal wiring 100 of the semiconductor device according to the embodiment of the present invention may include the semiconductor substrate 102, the insulating film 104, the barrier film 106, the buffer film 108, and the metal film 112. Include.

The semiconductor substrate 102 includes a bottom structure (not shown). Such substructures include, for example, gates, bitlines, capacitors, and the like.

The insulating film 104 is formed on the semiconductor substrate 102 having such a lower structure, and has a wiring formation region D.

In this case, the wiring formation region D may include a trench structure according to a single damascene process, or may include at least one via hole connected to a trench and a trench according to a dual damascene process. It may include a structure containing.

The barrier film 106 is formed on the surface of the wiring formation region D. FIG. The barrier film 106 formed on the surface of the wiring formation region D includes, for example, any one or more of TaN and Ta.

At this time, the barrier film 160 made of any one or more of such TaN and Ta has a (0,1,0) plane lattice structure of BCC (Body Center Cubic).

The buffer film 108 is formed on the surface of the barrier film 106 made of any one or more of such TaN and Ta films.

The buffer film 108 also includes a mixed material of, for example, Cu (x) Ta (1-x) (X = 0.5 to 0.9).

At this time, the buffer film 108 including a mixed material of such Cu (x) Ta (1-x) (X = 0.5 to 0.9) is, for example, the (1, 1, 1) plane of the FCC (Face Center Cubic) surface. It has a lattice structure.

In this case, the present invention has a (1, 1, 1) plane lattice structure of the FCC (Face Center Cubic) as described above, Cu (x) Ta (1-x ) by combining the properties of the Cu material and the properties of Ta material A buffer film made of a mixed material of (X = 0.5 to 0.9) is formed on the barrier film, thereby allowing the copper film to be artificially grown in the barrier film.

That is, Cu (x) Ta ( having a (1, 1, 1) plane lattice structure of FCC (Face Center Cubic) in the barrier film having the (0,1,0) plane lattice structure of the BCC (Body Center Cubic) A mixed material of 1-x (X = 0.5 to 0.9) is formed, thereby causing a copper film to be artificially grown in the barrier film, thereby artificially forming a BCC (body center cubic) lattice structure of the barrier film artificially such as copper. By changing to, the crystal structure between the TaN or Ta material and the Cu material can be homogenized to offset the heterogenization of the different lattice structures between the conventional copper seed film or the barrier film made of the copper film and the TaN or Ta material.

Therefore, since the lattice structure between the copper film and the barrier film can be homogenized as described above, the defect density of the copper film can be reduced, and the hillock of the copper film can be reduced.

The metal film 112 is embedded in the wiring formation region D in which the buffer film 108 and the barrier film 106 are formed. The metal film 112 includes, for example, a copper film.

On the other hand, the metal wiring 100 of the semiconductor device according to an embodiment of the present invention further includes a seed film 110 interposed between the metal film 112 and the buffer film 108, such a seed film 110 Silver contains a copper film, for example.

2A through 2E are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an insulating film 104 is formed on a semiconductor substrate 102 having a lower structure (not shown) such as a gate, a bit line, and a capacitor. Then, the insulating film 104 is etched to form the wiring formation region D.

In this case, the wiring formation region D may be formed of a trench structure according to a single damascene process, or may include at least one via hole connected to a trench and a trench according to a dual damascene process. It may be formed into a structure containing.

Referring to FIG. 2B, the barrier film 106 is formed on the surface of the wiring formation region D. FIG. At this time, the barrier film 106 formed on the surface of the wiring formation region D is formed of, for example, any one or more of TaN and Ta.

At this time, the barrier film 106 made of any one or more of such TaN and Ta has a (0,1,0) plane lattice structure of BCC (Body Center Cubic).

Referring to FIG. 2C, a buffer film 108 is formed on the barrier film 106. The buffer film 108 is formed of a mixed material of, for example, Cu (x) Ta (1-x) (X = 0.5 to 0.9).

At this time, the buffer film 108 including a mixed material of such Cu (x) Ta (1-x) (X = 0.5 to 0.9) is, for example, the (1, 1, 1) plane of the FCC (Face Center Cubic) surface. It has a lattice structure.

In this case, the present invention has a (1, 1, 1) plane lattice structure of the FCC (Face Center Cubic) as described above, Cu (x) Ta (1-x ) by combining the properties of the Cu material and the properties of Ta material A buffer film made of a mixed material of (X = 0.5 to 0.9) is formed on the barrier film, whereby a copper film is artificially grown in the barrier film.

That is, Cu (x) Ta ( having a (1, 1, 1) plane lattice structure of FCC (Face Center Cubic) in the barrier film having the (0,1,0) plane lattice structure of the BCC (Body Center Cubic) A buffer film made of a mixed material of 1-x (X = 0.5 to 0.9) is formed to grow a copper film in the barrier film, thereby artificially changing the BCC (body center cubic) lattice structure of the barrier film to an FCC structure such as copper. You can.

Therefore, the crystal structure between the TaN or Ta material and the Cu material can be homogenized to offset the heterogenization of the different lattice structures between the conventional copper seed film or the barrier film made of the copper film and the TaN or Ta material.

As a result, a lattice structure between a conventional copper seed film or copper film and a barrier film made of TaN or Ta material, which is naturally misfit and susceptible to lattice defects such as stacking fault dislocations. Since the defect density can be reduced by homogenizing, the hillock of the copper film can be reduced.

Referring to FIG. 2D, a copper seed film 110 is formed on the surface of the buffer film 108. Then, a metal film 112 made of copper is formed on the insulating film 104 including the wiring forming region D in which the copper seed film 110 is formed by electroplating.

Referring to FIG. 2E, the metal film 112, the seed film 110, the buffer film 108 and the barrier film 106 are removed by chemical mechanical polishing (CMP) until the insulating film 104 is exposed. The metallization 100 of the semiconductor device according to the embodiment is completed.

As described above, the present invention uses Cu (x) Ta (1-x) on the barrier film as described above. By forming the buffer film and filling the copper film, when forming the copper metal wiring, the crystal structure between the barrier film and the copper film may be homogenized to reduce the defect density in the copper film.

Therefore, since the compressive stress applied to the copper film can be dispersed by the insulating film adjacent to the copper film, the hillock phenomenon can be prevented, and the resistance of the copper wiring can be improved, and the device characteristics and reliability can be improved. .

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a cross-sectional view for explaining a metal wiring of a semiconductor device according to an embodiment of the present invention.

2A through 2E are cross-sectional views illustrating processes for forming metal wirings of a semiconductor device in accordance with an embodiment of the present invention.

Claims (12)

Semiconductor substrates; An insulating film formed on the semiconductor substrate and having a wiring formation region; A barrier film formed on a surface of the wiring formation region; A buffer film formed on the barrier film surface; And A metal film embedded in the wiring formation region; Metal wiring of a semiconductor device comprising a. The method of claim 1, The barrier film may include at least one of TaN and Ta. The method of claim 1, And the buffer film comprises a mixed material of Cu (x) Ta (1-x) (X = 0.5 to 0.9). The method of claim 1, And a seed film interposed between the buffer film and the metal film. The method of claim 4, wherein The seed film is a metal wiring of the semiconductor device, characterized in that it comprises a copper film. The method of claim 1, The metal layer of the semiconductor device, characterized in that the copper film comprises a copper film. Forming an insulating film having a wiring formation region on the semiconductor substrate; Forming a barrier film on a surface of the wiring formation region; Forming a buffer film on the barrier film surface; And Embedding a metal film in the wiring forming region; Metal wiring forming method of a semiconductor device comprising a. The method of claim 7, wherein And the barrier film is formed of at least one of TaN and Ta. The method of claim 7, wherein The buffer film is formed of a mixed material of Cu (x) Ta (1-x) (X = 0.5 to 0.9). The method of claim 7, wherein Between the step of forming the buffer film and the step of embedding the metal film, Forming a seed film on the buffer film; Forming a metal wiring of the semiconductor device further comprising. The method of claim 10, And the seed film is formed of a copper film. The method of claim 7, wherein And the metal film is formed of a copper film.
KR1020090011168A 2009-02-11 2009-02-11 Metal wiring of semiconductor device and method of manufacturing the same KR20100091804A (en)

Priority Applications (1)

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KR1020090011168A KR20100091804A (en) 2009-02-11 2009-02-11 Metal wiring of semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090011168A KR20100091804A (en) 2009-02-11 2009-02-11 Metal wiring of semiconductor device and method of manufacturing the same

Publications (1)

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KR20100091804A true KR20100091804A (en) 2010-08-19

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