KR20100091408A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20100091408A
KR20100091408A KR1020090010589A KR20090010589A KR20100091408A KR 20100091408 A KR20100091408 A KR 20100091408A KR 1020090010589 A KR1020090010589 A KR 1020090010589A KR 20090010589 A KR20090010589 A KR 20090010589A KR 20100091408 A KR20100091408 A KR 20100091408A
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KR
South Korea
Prior art keywords
signal
input
inverter unit
circuit
output
Prior art date
Application number
KR1020090010589A
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Korean (ko)
Inventor
김보겸
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090010589A priority Critical patent/KR20100091408A/en
Publication of KR20100091408A publication Critical patent/KR20100091408A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

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  • Electronic Switches (AREA)

Abstract

PURPOSE: A semiconductor device is provided to prevent the malfunction of a circuit by initializing an output signal of a buffer circuit to an inactive state. CONSTITUTION: A buffer circuit(A) buffers and outputs an input signal. An initialization circuit includes a plurality of connection units connected to internal nodes of the buffer circuit and is connected to the buffer circuit through one connection unit among a plurality of connection units. The initialization circuit initializes the output signal of the buffer circuit to an inactive state. A first inverter(100) inverts the signal inputted from a pad. A second inverter(200) inverts the signal outputted from the first inverter and outputs the inverted signal to a preset voltage level.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an input buffer.

In the semiconductor device, an input buffer is a portion that buffers a signal applied from the outside and inputs it into the semiconductor device. The input buffer circuit of the semiconductor memory device adapts an externally applied TTL level voltage to a usage environment inside the chip. It converts to CMOS level.

In a typical NAND Flash memory device, an address latch enable (ALE) signal is input at a high level when enabled, a read enable (/ RE) signal, a write in A write enable (/ WE) signal or the like is input at a low level when enabled. However, when the corresponding signal is not input through each pad, the respective input buffers must output the disabled signal, otherwise it may cause a malfunction.

In addition, circuit correction is performed to correct an error when a signal is newly added or an initial value is incorrectly set in a conventional semiconductor device. To this end, it is inconvenient to add a new circuit path or modify an existing circuit path. There is a ham.

The present invention has been made to solve the above problems, and an object thereof is to provide an input buffer which can simply set an initial value to an inactive state.

The present invention for achieving the above object includes a buffer circuit for buffering and outputting an input signal, and a plurality of connection means connected to the internal nodes of the buffer circuit, one of the connection means of the plurality of connection means And an initialization circuit connected to the buffer circuit to initialize an output signal of the buffer circuit to an inactive state.

The buffer circuit may include a first inverter unit for inverting the signal input from the pad, and a second inverter unit for inverting the signal output from the first inverter unit and outputting the signal at a predetermined voltage level. In this case, the predetermined voltage is preferably a CMOS level voltage.

The first inverter unit may include: a first PMOS transistor having a signal input from the pad being input to a gate and connected between a driving power supply terminal and an output node of the first inverter portion; The first NMOS transistor may be connected between the output node of the first inverter unit and the ground terminal.

The second inverter unit may include an output signal of the first inverter unit input to the gate, a second PMOS transistor connected between an internal power supply terminal and an output node of the second inverter unit, and an output signal of the first inverter unit input to the gate; And a second NMOS transistor connected between an output node of the second inverter unit and a ground terminal.

The initialization circuit may include a first metal option connected to an output node of the first inverter unit, a second metal option connected to an output node of the second inverter unit, and a first enable signal input to a gate, and the first metal option may be input to the gate. The option and the second metal option may include a third NMOS transistor connected between a node that is commonly connected and a ground.

Alternatively, the initialization circuit may include a third metal option connected to an output node of the first inverter unit, a fourth metal option connected to an output node of the second inverter unit, a second enable signal input to a gate, and a power supply terminal. A fourth PMOS transistor may be connected between nodes in which the third metal option and the fourth metal option are commonly connected.

The first inverter unit may further include a third PMOS transistor, the first enable signal being input to a gate, and connected between a driving power supply terminal and a first PMOS transistor.

The buffer circuit may further include a circuit protection unit for protecting the circuit from static electricity input from the pad.

The circuit protection unit may include a fourth NMOS transistor having a gate connected to a ground terminal and connected between an input node of the first inverter unit and a ground terminal.

According to the present invention, it is possible to simply initialize the semiconductor device to an inactive state by using a metal option. For example, if the initial value of the input buffer is incorrectly set during the semiconductor manufacturing process and the circuit is to be corrected, the initial value can be easily corrected by modifying the metal option. That is, the circuit malfunction can be prevented by simply initializing the semiconductor device to the inactive state without changing the layout during the semiconductor manufacturing process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device of the present invention includes a buffer circuit A and an initialization circuit 300.

The buffer circuit A serves to buffer and output an input signal, and includes a first inverter unit 100, a second inverter unit 200, and a circuit protection unit 400.

The initialization circuit 300 includes a plurality of connecting means connected to the internal nodes of the buffer circuit A, and is connected to the buffer circuit A through one of the plurality of connecting means to the buffer circuit A. Initialize the output signal to the inactive state.

Now, each component constituting the semiconductor device will be described.

The first inverter unit 100 inverts a signal input from the pad Pad. In the present invention, the first inverter unit 100 is a signal input from the pad is input to the gate

The first PMOS transistor P10 connected between the driving power supply VCC terminal and the output node of the first inverter unit 100 and the signal input from the pad are input to the gate, and the output node of the first inverter unit 100 is connected to the output node of the first inverter unit 100. And a first NMOS transistor N10 connected between the ground terminals.

The second inverter unit 200 inverts the signal output from the first inverter unit 100 to output at a predetermined voltage level. The predetermined level is preferably a CMOS level which is an internal voltage of the semiconductor device. In the present invention, the second inverter unit 200 includes a second PMOS transistor in which an output signal of the first inverter unit 100 is input to a gate and connected between an internal power supply (Vin) terminal and an output node of the second inverter unit 200. And a second NMOS transistor N20 connected to the gate and the output signal of the first inverter unit 100 connected between the output node of the second inverter unit 200 and the ground terminal.

The circuit protection unit 400 protects a circuit from electrostatic discharge (ESD) input from the pad. The circuit protection unit 400 includes a fourth NMOS transistor N40 having a gate connected to the ground terminal and connected between the input node of the first inverter unit 100 and the ground terminal. In the present invention, the fourth NMOS transistor N40 is maintained in an off state during normal times, and then turns on at the moment when tens of thousands to millions [V] of static electricity flows from the pad to discharge the static electricity. In this way, the circuit protection unit 400 protects the circuit from static electricity.

The initialization circuit 300 initializes the signal at the output terminal of the second inverter unit 200 to an inactive state. In the present invention, the initialization circuit 300 is a first metal option 310 connected to the output node of the first inverter unit 100, a second metal option 320 connected to the output node of the second inverter unit 200, A third NMOS transistor N30 connected between a ground terminal and a node commonly connected to the first metal option 310 and the second metal option 320 and input to the gate of the first enable signal ENb. Is done. In the embodiment of the present invention, the metal option is used as a connecting means, but various connecting means such as a fuse may be used in addition to the metal option according to the embodiment.

In the embodiment of FIG. 1, the first inverter unit 100 receives a first enable signal ENb at a gate thereof and is connected between the driving power supply VCC terminal and the first PMOS transistor P10. It may further include. In the state in which the input buffer is activated, the first enable ENb signal having a low level is input to the gate of the third PMOS transistor P30 to turn on the third PMOS transistor P30, thereby applying the VCC power to the circuit. On the other hand, in the state in which the input buffer is initialized, the first enable signal ENb of the high level is input to the gate of the third PMOS transistor P30, and the third PMOS transistor P30 is turned off. Not authorized

The input buffer of the present invention serves to buffer and output the signal input through the pad. Referring to the drawings the operation of the input buffer of the present invention will be described.

The signal input through the pad is inverted in phase through the first inverter unit 100. Next, the signal from the first inverter unit 100 passes through the second inverter unit 200 and is inverted in phase and output. In addition, since the second inverter unit 200 is driven by the internal power source Vin as the source power source, the size of the signal input through the pad is adjusted to the size of the internal power source of the semiconductor chip. For example, the TTL level input signal is output while being adjusted to a CMOS level while maintaining its phase while passing through the input buffer.

The circuit operation when the signal input through the pad is a high level signal is described as follows. When the high level signal is input, the first PMOS transistor P10 is turned off and the first NMOS transistor N10 is turned on. Accordingly, a low signal is output from the first inverter unit 100, and the second PMOS transistor P20 is turned on and the second NMOS transistor N20 is turned off due to the low signal. Accordingly, the output signal Out of the second inverter unit 200 becomes a high signal having an internal power supply Vin.

Next, a circuit operation when the signal input through the pad is a low level signal will be described. When the low level signal is input, the first PMOS transistor P10 is turned on and the first NMOS transistor N10 is turned off. Accordingly, a high signal is output from the first inverter unit 100, and the second PMOS transistor P20 is turned off and the second NMOS transistor N20 is turned on due to the high signal. Accordingly, the output signal Out of the second inverter unit 200 becomes a low signal.

As described above, the semiconductor device of the present invention buffers a signal input from a pad and outputs a signal having a size appropriate for an internal power supply.

In the present invention, when the semiconductor device is not used, the output signal Out is initialized, and the output signal Out is initialized through the initialization circuit 300. Referring to the operation of the initialization circuit 300 in the present invention in detail.

The initialization circuit 300 includes two metal options 310 and 320 and a third NMOS transistor N30. For reference, the metal option refers to a technology in which any two points are connected by metal lines in the manufacturing process of a semiconductor integrated circuit, and the user cuts the metal layer as needed.

In the present invention, the initialization circuit 300 selectively cuts the first metal option 310 and the second metal option 320 to form a current path to initialize the output signal Out to an inactive state.

2 is an equivalent circuit diagram of an input buffer circuit according to an embodiment of the present invention. 2 is an equivalent circuit diagram of a circuit in which the first metal option 310 is connected and the second metal option 320 is cut in order to output a high signal as the output signal Out.

In FIG. 2, when the high level first enable ENb signal is input to the gate of the third NMOS transistor N30, the third NMOS transistor N30 is turned on, and accordingly, the second PMOS transistor P20 and the second NMOS transistor ( The low signal is applied to the gate terminal of N20). Accordingly, the second PMOS transistor P20 is turned on and the second NMOS transistor N20 is turned off to output a high level signal as the output signal Out. That is, as shown in the embodiment of FIG. 2, when the first metal option 310 is connected, the output signal Out of the input buffer is initialized to a high level signal.

3 is an equivalent circuit diagram of an input buffer according to an embodiment of the present invention. 3 is an equivalent circuit diagram of a circuit in which the first metal option 310 is cut and the second metal option 320 is connected to output the low signal as the output signal Out.

In FIG. 3, when the high level first enable ENb signal is input to the gate of the third NMOS transistor N30, the third NMOS transistor N30 is turned on. Accordingly, the signal output from the second inverter unit 200 is connected to the ground through the third NMOS transistor N30, and a low level signal is output as the output signal Out. That is, as shown in the embodiment of FIG. 3, when the second metal option 320 is connected, the output signal Out of the input buffer is initialized to a low level signal.

1 to 3 illustrate an embodiment in which an NMOS transistor is used as the switching means of the initialization circuit. An embodiment in which a PMOS transistor is used as the switching means of the initialization circuit will now be described with reference to the drawings.

4 is a circuit diagram of a semiconductor device according to another embodiment of the present invention. 4 illustrates an embodiment in which a fourth PMOS transistor P40 is used as the switching means of the initialization circuit 600.

Since the other circuit components except for the initialization circuit 600 in FIG. 4 are the same as the circuit components described with reference to FIG. 1, a description of the circuit components will be omitted.

In FIG. 4, the initialization circuit 600 includes a third metal option 610 connected to an output node of the first inverter unit 100 and a fourth metal option 620 connected to an output node of the second inverter unit 200. And a fourth PMOS transistor (P40) connected between a power supply terminal and a node to which the third metal option 610 and the fourth metal option 620 are commonly connected. do. In this case, the power applied to the fourth PMOS transistor P40 is preferably an internal power supply Vin.

In FIG. 4, the initialization circuit 600 selectively cuts the third metal option 610 and the fourth metal option 620 to form a current path in order to initialize the output signal Out to an inactive state.

5 is an equivalent circuit diagram of an input buffer circuit according to an embodiment of the present invention. 5 is an equivalent circuit diagram of a circuit in which a third metal option 610 is connected and a fourth metal option 620 is cut in order to output a low signal as an output signal Out.

In FIG. 5, when the low level second enable EN signal is input to the gate of the fourth PMOS transistor P40, the fourth NMOS transistor P40 is turned on, and accordingly, the second PMOS transistor P20 and the second NMOS transistor ( The high signal is applied to the gate terminal of N20). Accordingly, the second PMOS transistor P20 is turned off and the second NMOS transistor N20 is turned on to output a low level signal as the output signal Out. That is, as shown in the embodiment of FIG. 5, when the third metal option 610 is connected, the output signal Out of the input buffer is initialized to a low level signal.

6 is an equivalent circuit diagram of an input buffer according to an embodiment of the present invention. 6 is an equivalent circuit diagram of a circuit in which the third metal option 610 is cut and the fourth metal option 620 is connected to output the high signal as the output signal Out.

In FIG. 6, when the low level second enable EN signal is input to the gate of the fourth PMOS transistor P40, the fourth PMOS transistor P40 is turned on. Accordingly, the signal output from the second inverter unit 200 is connected to the internal power supply Vin through the fourth NMOS transistor P40, and thus a high level signal is output as the output signal Out. That is, as shown in the embodiment of FIG. 6, when the fourth metal option 620 is connected, the output signal Out of the input buffer is initialized to the high level signal.

As described above, the semiconductor device may be initialized by selectively cutting the metal options 310, 320, 610, and 620. For example, when circuit correction is performed by incorrectly setting an initial value of an input buffer during a semiconductor manufacturing process, the initial value can be easily modified by modifying a metal option.

While the invention has been described using some preferred embodiments, these embodiments are illustrative and not restrictive. Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the invention and the scope of the rights set forth in the appended claims.

1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

2 and 3 are equivalent circuit diagrams of a semiconductor device according to an embodiment of the present invention.

4 is a circuit diagram of a semiconductor device according to another embodiment of the present invention.

5 and 6 are equivalent circuit diagrams of a semiconductor device according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100 First Inverter 200 Second Inverter

300, 600 initialization circuit 400 circuit protection unit

310 First connecting means 320 Second connecting means

610 third connecting means 620 fourth connecting means

A buffer circuit

Claims (10)

A buffer circuit for buffering and outputting an input signal; An initialization circuit including a plurality of connection means connected to internal nodes of the buffer circuit, and connected to the buffer circuit through one of the plurality of connection means to initialize the output signal of the buffer circuit to an inactive state. A semiconductor device comprising a. The method of claim 1, The buffer circuit includes a first inverter part for inverting a signal input from a pad, and a second inverter part for inverting the signal output from the first inverter part and outputting the signal at a predetermined voltage level. . The method of claim 2, The first inverter unit, A first PMOS transistor having a signal input from the pad being input to a gate and connected between a driving power supply terminal and an output node of the first inverter unit; And a first NMOS transistor connected to an output node of the first inverter unit and a ground terminal of a signal input from the pad. The method of claim 2, The second inverter unit, A second PMOS transistor connected to an internal power supply terminal and an output node of the second inverter unit, the output signal of the first inverter unit being input to the gate; And a second NMOS transistor connected to a gate of the output signal of the first inverter unit and connected between an output node of the second inverter unit and a ground terminal. The method of claim 2, The initialization circuit, A first metal option connected to an output node of the first inverter part, A second metal option connected to the output node of the second inverter part; And a third NMOS transistor connected to a ground and a node to which a first enable signal is input to a gate and the first metal option and the second metal option are commonly connected. The method of claim 3, The first inverter unit further comprises a third PMOS transistor, the first enable signal is input to the gate and connected between a driving power supply terminal and the first PMOS transistor. The method of claim 2, The buffer circuit further comprises a circuit protection unit for protecting the circuit from static electricity input from the pad. The method of claim 7, wherein The circuit protection unit includes a fourth NMOS transistor whose gate is connected to the ground terminal and is connected between the input node and the ground terminal of the first inverter unit. The method of claim 2, And said predetermined voltage is a CMOS level voltage. The method of claim 2, The initialization circuit, A third metal option connected to the output node of the first inverter unit, A fourth metal option connected to the output node of the second inverter unit, And a fourth PMOS transistor connected to a power supply terminal and a node to which the third metal option and the fourth metal option are commonly connected.
KR1020090010589A 2009-02-10 2009-02-10 Semiconductor device KR20100091408A (en)

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KR1020090010589A KR20100091408A (en) 2009-02-10 2009-02-10 Semiconductor device

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KR1020090010589A KR20100091408A (en) 2009-02-10 2009-02-10 Semiconductor device

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