KR20100088922A - Oscillator circuit and high voltage generating device comprising of the same - Google Patents

Oscillator circuit and high voltage generating device comprising of the same Download PDF

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Publication number
KR20100088922A
KR20100088922A KR1020090008067A KR20090008067A KR20100088922A KR 20100088922 A KR20100088922 A KR 20100088922A KR 1020090008067 A KR1020090008067 A KR 1020090008067A KR 20090008067 A KR20090008067 A KR 20090008067A KR 20100088922 A KR20100088922 A KR 20100088922A
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KR
South Korea
Prior art keywords
clock
voltage
signal
output
external power
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Application number
KR1020090008067A
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Korean (ko)
Inventor
박명진
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090008067A priority Critical patent/KR20100088922A/en
Publication of KR20100088922A publication Critical patent/KR20100088922A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit of a semiconductor device and a high voltage generator circuit including the same, comprising: a detection signal generation circuit for detecting an external power supply voltage and generating a clock control signal using the same; and a clock signal using the external power supply voltage. Disclosed is an oscillator circuit including a clock generation circuit for generating a cycle and controlling a period of the clock signal in response to the clock control signal, and a high voltage generation circuit including the same.

Description

Oscillator circuit and high voltage generating device comprising the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit of a semiconductor device and a high voltage generating circuit including the same, and in particular, an oscillator circuit capable of constantly outputting a pumping voltage by changing a cycle of a pump clock generated when an external voltage changes, and a high voltage including the same. It relates to a generation circuit.

In general, there are circuits that need to use an internal clock as well as an external clock in memory devices and IC chips. In flash memory, an internal clock is used without input of an external clock to a microcontroller or a pump circuit. An oscillator circuit generates the clock.

The oscillator circuit according to the prior art has a structure in which an odd number of inverters are connected in series as a ring oscillator so that the output of the final stage is fed back to the input of the first inverter. However, the ring oscillator has a disadvantage in that the period varies greatly due to the influence of the supply voltage instead of being simple. To improve this, circuits are used that connect a constant current source to the inverter, include resistors, capacitance and Schmitt triggers, or comparators to allow the RC delay effect to determine the period.

1 is a block diagram showing a high voltage generation circuit using an oscillator according to the prior art.

Referring to FIG. 1, the oscillator 10 is enabled in response to the enable signal EN to generate a clock signal CLK using the external power supply voltage Vext. The clock driver 20 generates the first and second high voltage clock signals H-CLK and / H-CLK by using the clock signal CLK output from the oscillator 10. The charge pump 30 generates a high voltage Vpp by performing a pumping operation using the first and second high voltage clock signals H-CLK and / H-CLK.

The oscillator 10 of the above-described high voltage generation circuit generates the clock signal CLK using the external power supply voltage Vext. At this time, when a drop phenomenon of the external power supply voltage Vext occurs due to an external environment change, the generated clock signal CLK is not generated at a constant potential level and a clock signal CLK of a low potential level is generated. Done. The clock signal CLK of the low potential level generated in this way is applied to the clock driver 20 to cause generation of the first and second high voltage clock signals H-CLK and / H-CLK lower than the target potential level. Finally, the pumping operation of the charge pump 30 is lowered to the boosting voltage of the pump. As a result, more pumping operation is required to form a high voltage, which increases the time for forming a high voltage (Vpp). This degrades the performance of program operation using high voltage (Vpp).

An object of the present invention is to detect the external power supply voltage when the external power supply voltage drops to change the period of the clock signal output from the oscillator, thereby outputting a constant time to output a high voltage from the charge pump An oscillator circuit of a semiconductor device is provided.

An oscillator circuit of a semiconductor device according to an embodiment of the present invention detects an external power supply voltage and generates a clock control signal using the detection signal generation circuit, and generates a clock signal using the external power supply voltage. And a clock generation circuit for adjusting a period of the clock signal in response to a control signal.

When the external power supply voltage drops, the period of the clock signal is increased.

The detection signal generation circuit may include a reference voltage generator for generating a plurality of reference voltages using a down converter voltage, a voltage comparator for generating a plurality of detection signals by comparing the plurality of reference voltages with the external power supply voltage, respectively, And a clock controller configured to generate the clock control signal using a plurality of detection signals.

The clock generation circuit may include a buffer unit generating an output voltage in response to an input signal, a resistance controller connected between the buffer and ground power and controlling an output node potential of the buffer in response to the clock control signal; And a comparison unit configured to compare an output voltage and a comparison voltage to output a comparison signal, and a clock generation circuit configured to generate the clock signal using the comparison signal.

According to an embodiment of the present invention, when the external power supply voltage is detected and the external power supply voltage is dropped, the period of the clock signal output from the oscillator is changed and outputted, thereby maintaining a constant consumption time for outputting a high voltage from the charge pump. To provide an oscillator circuit of a semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2 is a block diagram showing a high voltage generation circuit according to an embodiment of the present invention.

2, a high voltage generation circuit according to an embodiment of the present invention includes an external power detector 100, a clock controller 200, an oscillator 300, a clock driver 400, and a charge pump 500. do.

The external power detector 100 includes a reference voltage generator 110 and a voltage comparator 120. The reference voltage generator 110 receives the down converter voltage V DC to output a plurality of reference voltages Vref0 to VrefN. The down converter voltage V DC is output from the down converter voltage generator 600, and the down converter voltage generator 600 always outputs a constant down converter voltage V DC even when an input power voltage is changed.

The voltage comparator 120 receives an external power supply voltage Vext and compares it with a plurality of reference voltages Vref0 to VrefN, respectively, and outputs a plurality of detection signals TB <N: 0>.

The clock controller 200 receives a plurality of detection signals TB <N: 0> and outputs the clock control signals CB <M: 0>.

The oscillator 300 is enabled in response to the enable signal en, and receives the external power supply voltage Vext to generate the clock signal CLK. At this time, the period of the clock signal CLK output in response to the clock control signal CB <M: 0> is changed.

The clock driver 400 generates the first and second high voltage clock signals H-CLK and / H-CLK by using the clock signal CLK output from the oscillator 300. The charge pump 500 performs a pumping operation using the first and second high voltage clock signals H-CLK and / H-CLK to generate a high voltage Vpp.

3 is a detailed circuit diagram of the reference voltage generator 110 of FIG. 2.

Referring to FIG. 3, the reference voltage generator 110 includes a plurality of resistors R1 to RN + 1. The plurality of resistors R1 to RN + 1 are connected in series between the terminal to which the down converter voltage V DC is input and the ground power supply Vss. To VrefN).

4 is a detailed circuit diagram of the voltage comparator 120 of FIG. 2.

Referring to FIG. 4, the voltage comparator 120 includes a plurality of comparators CP0 to CPN. Each of the plurality of comparators CP0 to CPN compares any one of the plurality of reference voltages Vref0 to VrefN with an external power supply voltage Vext and outputs a plurality of detection signals TB <N: 0>.

FIG. 5 is a detailed circuit diagram of the oscillator 300 of FIG. 2.

Referring to FIG. 5, the oscillator 300 includes a first buffer 310 and a second buffer 320. The first resistor controller 330, the second resistor controller 340, the first comparator 350, the second comparator 360, and the clock generator 370 are included.

The first buffer 310 includes a PMOS transistor PM1 and an NMOS transistor NM1 connected in series with an external power supply voltage Vext. One end of the NMOS transistor NM1 is connected to the first resistance controller 330. The PMOS transistor PM1 and the NMOS transistor NM1 output an external power supply voltage Vext to the output voltage VA through the output node A in response to the input signal / Q, or the first resistance adjuster ( The discharged voltage is output as the output voltage VA through the 330.

The first resistance controller 330 is connected between the NMOS transistor NM1 of the first buffer 310 and the ground power source. The first resistance controller 330 controls the amount of current discharged through the NMOS transistor NM1 of the first buffer 310 by adjusting its own resistance in response to the clock control signal CB <M: 0>. Adjust the time (A) is discharged to the low level.

The first comparator 350 includes a comparator CR1, a PMOS transistor PM3, and an inverter IV1. The comparator CR1 generates the first output signal Vout1 by comparing the output voltage VA output from the first buffer 310 with the comparison voltage Vref. For example, a low level first output signal Vout1 is generated when the output voltage VA is greater than the comparison voltage Vref, and a high level first output when the output voltage VA is less than the comparison voltage Vref. Signal Vout1 is generated. The PMOS transistor PM3 is connected to the power supply voltage and the output terminal of the comparator CR1. The PMOS transistor PM3 blocks the power supply voltage applied to the output terminal of the comparator CR1 in response to the enable signal en. The inverter IV1 inverts the first output signal Vout1 output from the comparator CR1 and outputs the inverted signal to the clock generator 370.

The second buffer 320 includes a PMOS transistor PM2 and an NMOS transistor NM2 connected in series with an external power supply voltage Vext. One end of the NMOS transistor NM2 is connected to the second resistance controller 340. The PMOS transistor PM2 and the NMOS transistor NM2 output the external power voltage Vext to the output voltage VB through the output node B in response to the input signal Q, or the second resistance controller 340. ) Outputs the discharged voltage to the output voltage (VB) for a predetermined time.

The second resistance controller 340 is connected between the NMOS transistor NM2 of the second buffer 320 and the ground power source. The second resistance controller 340 controls the amount of current discharged through the NMOS transistor NM2 of the second buffer 320 by adjusting its own resistance in response to the clock control signal CB <M: 0>. Adjust the time (B) is discharged to the low level.

The second comparator 360 includes a comparator CR2, an NMOS transistor NM3, and an inverter IV2. The comparator CR2 generates the second output signal Vout2 by comparing the output voltage VB output from the second buffer 320 with the comparison voltage Vref. For example, a low level second output signal Vout2 is generated when the output voltage VB is greater than the comparison voltage Vref, and a high level second output when the output voltage VB is less than the comparison voltage Vref. Signal Vout2 is generated. The NMOS transistor NM3 is connected to the ground power supply and the output terminal of the comparator CR2. The NMOS transistor NM3 cuts off the ground power applied to the output terminal of the comparator CR2 in response to the inversion enable signal enb. The inverter IV2 inverts the second output signal Vout2 output from the comparator CR2 and outputs the inverted signal to the clock generator 370.

The clock generator 370 includes NAND gates ND1 and ND2 and an inverter IV3. The NAND gate ND1 generates an input signal Q by logically combining the output signal of the first comparator 350 and the input signal / Q, which is an output signal of the NAND gate ND1. The NAND gate ND2 logically combines an output signal of the second comparator 360 and an input signal Q, which is an output signal of the NAND gate ND2, to generate an input signal / Q. The inverter IV3 inverts the input signal / Q, which is the output signal of the NAND gate ND1, and outputs the inverted signal as the clock signal CLK.

FIG. 6 illustrates that the voltage comparator 120 of FIG. 4 outputs a plurality of detection signals TB <N: 0> by comparing a plurality of reference voltages Vref0 to VrefN and an external power supply voltage Vext. Voltage waveform diagram.

For example, when the external power supply voltage Vext is dropped to be lower than the reference voltage Vref1 and higher than the reference voltage Vref2, the detection signal TB <1: 0> is generated at a low level, and the detection signal ( TB <N: 2>) is output at a high level.

Referring to FIGS. 2 to 6, an operation of an oscillator circuit and a high voltage generation circuit including the same according to an embodiment of the present invention will be described.

The reference voltage generator 110 receives a down converter voltage V DC input at a constant level and outputs a plurality of reference voltages Vref0 to VrefN. The voltage comparator 120 receives an external power supply voltage Vext and compares it with a plurality of reference voltages Vref0 to VrefN, respectively, and outputs a plurality of detection signals TB <N: 0>. The clock controller 200 receives a plurality of detection signals TB <N: 0> and outputs the clock control signals CB <M: 0>.

The oscillator 300 is enabled in response to the enable signal en, and receives the external power supply voltage Vext to generate the clock signal CLK. At this time, the period of the clock signal CLK output in response to the clock control signal CB <M: 0> is changed.

The operation of the oscillator 300 will now be described in detail.

First, a low level input signal / Q is input to the first buffer 310 to generate a high level first output voltage VA. In addition, the high level input signal Q is input to the second buffer 320 to generate a low level second output voltage VB. In this case, the second resistance controller 340 controls its own resistance in response to the clock control signal CB <M: 0> generated by detecting the voltage level of the external power supply voltage Vext, thereby controlling the NMOS transistor NM2 and the first resistor. By controlling the amount of current discharged through the resistance adjusting unit 340, the discharge time is controlled.

The first comparator 350 generates a high level output signal by comparing the first output voltage VA having a high level with the reference voltage Vref. The clock signal generator 370 generates the high level clock signal CLK in response to the high level output signal and the low level input signal / Q output from the first comparator 350. In addition, the high level input signal Q transitions to the low level.

 The second comparator 360 generates a low level output signal by comparing the low level second output voltage VB and the reference voltage Vref. At this time, the output signal of the second comparator 360 is later than the output signal of the first comparator 350 by the time when the low level second output voltage VB output from the second buffer 320 is discharged. Is generated. The clock signal generator 370 generates the high level input signal / Q in response to the low level output signal and the low level input signal Q output from the second comparator 360.

As described above, the clock signal CLK is shifted and the input signals Q and / Q are shifted to repeat the above-described operation to generate the clock signal CLK having a predetermined period. In this case, the period of the clock signal CLK may include first and second resistance adjusting units configured to adjust the time discharged when the first and second output voltages VA and VB of the first and second buffers 310 and 320 are generated. Controlled by 330 and 340. That is, the oscillator 300 of the present invention changes the period of the clock signal CLK according to the degree of drop of the external power supply voltage Vext. Preferably, as the drop amount of the external power supply voltage Vext increases and decreases, the period of the clock signal CLK increases.

The clock driver 400 generates the first and second high voltage clock signals H-CLK and / H-CLK by using the clock signal CLK output from the oscillator 300. At this time, the periods of the first and second high voltage clock signals H-CLK and / H-CLK also increase or decrease according to the period of the clock signal CLK. The charge pump 500 performs a pumping operation using the first and second high voltage clock signals H-CLK and / H-CLK to generate a high voltage Vpp. At this time, even if the external power supply voltage Vext falls during the pumping operation and the maximum voltage level of the clock falls, the clock period increases to maintain the consumption time for reaching a constant voltage during the pumping operation.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram showing a high voltage generation circuit using an oscillator according to the prior art.

2 is a block diagram showing a high voltage generation circuit according to an embodiment of the present invention.

3 is a detailed circuit diagram of the reference voltage generator 110 of FIG. 2.

4 is a detailed circuit diagram of the voltage comparator 120 of FIG. 2.

FIG. 5 is a detailed circuit diagram of the oscillator 300 of FIG. 2.

6 is a voltage waveform diagram illustrating the voltage comparator 120 of FIG. 4.

<Description of the symbols for the main parts of the drawings>

310 and 320: first and second buffers 330 and 340: first and second resistance adjusting units

350, 360: first and second comparators 370: clock signal generator

Claims (8)

A detection signal generation circuit for detecting an external power supply voltage and generating a clock control signal using the same; And And a clock generation circuit configured to generate a clock signal using the external power voltage, and to adjust a period of the clock signal in response to the clock control signal. The method of claim 1, An oscillator circuit generated by increasing a period of the clock signal when the external power supply voltage drops. The method of claim 1, The detection signal generation circuit A reference voltage generator for generating a plurality of reference voltages using the down converter voltage; A voltage comparator configured to generate the plurality of detection signals by comparing the plurality of reference voltages with the external power supply voltage, respectively; And And a clock controller configured to generate the clock control signal using the plurality of detection signals. The method of claim 1, The clock generation circuit A buffer unit generating an output voltage in response to an input signal; A resistance adjuster connected between the buffer and a ground power source and configured to discharge an output node potential of the buffer, and adjust a discharge time in response to the clock control signal; A comparator for comparing the output voltage with a comparison voltage to output a comparison signal; And An oscillator circuit comprising a clock generation circuit for generating the clock signal using the comparison signal. A detection signal generation circuit for detecting an external power supply voltage and generating a clock control signal using the same; An oscillator for generating a clock signal using the external power supply voltage and adjusting a period of the clock signal in response to the clock control signal; And a charge pump circuit configured to generate a high voltage by performing a pumping operation using the clock signal. The method of claim 5, The oscillator is generated by increasing the period of the clock signal, when the external power supply voltage drops. The method of claim 5, The detection signal generation circuit A reference voltage generator for generating a plurality of reference voltages using the down converter voltage; A voltage comparator configured to generate the plurality of detection signals by comparing the plurality of reference voltages with the external power supply voltage, respectively; And And a clock controller configured to generate the clock control signal using the plurality of detection signals. The method of claim 5, The oscillator A buffer unit generating an output voltage in response to an input signal; A resistance adjuster connected between the buffer and a ground power source and configured to discharge an output node potential of the buffer, and adjust a discharge time in response to the clock control signal; A comparator for comparing the output voltage with a comparison voltage to output a comparison signal; And And a clock generation circuit configured to generate the clock signal using the comparison signal.
KR1020090008067A 2009-02-02 2009-02-02 Oscillator circuit and high voltage generating device comprising of the same KR20100088922A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190081487A (en) * 2017-12-29 2019-07-09 에스케이하이닉스 주식회사 Temperature sensor circuit and semiconductor device including it
US10860248B2 (en) 2018-03-26 2020-12-08 SK Hynix Inc. Electronic device with control based on voltage abnormality, memory system having the same, and operating method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190081487A (en) * 2017-12-29 2019-07-09 에스케이하이닉스 주식회사 Temperature sensor circuit and semiconductor device including it
US10860248B2 (en) 2018-03-26 2020-12-08 SK Hynix Inc. Electronic device with control based on voltage abnormality, memory system having the same, and operating method thereof

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