KR20100087806A - Method of reading data in flash memory device - Google Patents

Abstract

PURPOSE: A method of reading data in a flash memory device is provided to improve junction overlap by increasing a pass voltage supplied to non-selected word line in a reading operation. CONSTITUTION: A bit line is pre-charged. A read voltage is applied to selected first word lines of word lines. A first pass voltage is applied to the second word line adjacent to the first word line. A first pass voltage is supplied to a second word line adjacent to the first word line. The second pass voltage lower than the first pass voltage is applied to the word lines. The voltage variation of the bit line is detected. The first pass voltage is applied to the second word line adjacent to the first word line.

Description

Method of reading data in flash memory device

The present invention relates to a data reading method of a flash memory device, and more particularly, to a data reading method of a flash memory device capable of improving the threshold voltage distribution of a memory cell during a read operation.

The flash memory device includes memory cells including a tunnel insulating layer, a floating gate, a dielectric layer, and a stacked gate in which a control gate is sequentially stacked. The flash memory device performs program and erase by controlling the threshold voltage Vt of a memory cell while injecting or emitting electrons to a floating gate using an F-N tunneling method.

In general, after the erase / program operation of the flash memory device is performed, that is, cycling, a trap charge is generated at the edge of the tunnel insulation layer. The increase in trap charge causes the same phenomenon as the junction overlap of the memory cell to decrease. That is, an increase in trap charge causes a decrease in memory cell current and an increase in threshold voltage.

1 is a diagram illustrating a threshold voltage distribution characteristic of a memory cell after cycling.

Referring to FIG. 1, it can be seen that the threshold voltage of the memory cell is increased after cycling (EW), thereby expanding the threshold voltage distribution. In addition, it can be seen that the expansion of the threshold voltage distribution increases as the number of cycling EW increases from 5000 (5k) times to 10000 (10k) times.

Meanwhile, during a read operation, a read voltage is applied to a word line connected to a memory cell to be read, and a pass voltage for turning on the memory cells is applied to the remaining word lines. At this time, when the threshold voltage of an arbitrary memory cell is lower than the threshold voltage of the memory cell adjacent thereto, the electric field applied to the tunnel insulating film of the memory cell having the relatively low threshold voltage is caused by the memory cells having the relatively high threshold voltage. Is reduced. As a result, in any memory cell having a relatively low threshold voltage, the effect of reducing junction overlap is further exacerbated, which further degrades the threshold voltage distribution.

The present invention provides a data reading method of a flash memory device capable of improving a threshold voltage distribution of a memory cell during a read operation.

A data read method of a flash memory device according to the present invention includes precharging a bit line, applying a read voltage to selected first word lines among word lines, and applying a first voltage to a second word line adjacent to the first word line. Applying a pass voltage, applying a second pass voltage lower than the first pass voltage to the remaining word lines, and detecting a voltage change of the bit line.

The first pass voltage is applied to the second word line adjacent to the first word line in the drain select line direction among the drain select line and the source select line facing each other with the word lines therebetween.

Alternatively, the first pass voltage is applied to a second word line adjacent to the first word line in the direction of the source select line among the drain select line and the source select line facing each other with the word lines therebetween.

Alternatively, the first pass voltage is applied to the second word line adjacent to the first word line in the drain select line direction and the source select line direction among the drain select line and the source select line facing each other with the word lines therebetween.

The first pass voltage is 6V to 9V.

The second pass voltage is 5V to 8V.

According to the present invention, the same effect as that of junction overlap is improved by increasing a pass voltage applied to an unselected word line during a read operation. That is, the present invention increases the current flowing through the cell by increasing the pass voltage applied to the unselected word line during the read operation, thereby lowering the threshold voltage of the corresponding cell. Accordingly, the present invention can improve the phenomenon that the threshold voltage distribution is expanded by controlling the pass voltage applied during the read operation even when the threshold voltage of the cell increases after cycling.

The present invention reduces the risk of read-disturb by increasing the pass voltage by limiting the non-selected word lines adjacent to the selected word line rather than increasing the pass voltage applied to the entire unselected word lines during a read operation. Can be.

According to the present invention, the threshold voltage distribution can be improved during the read operation, so that the yield of the flash memory device can be improved.

The present invention can improve the reliability of the flash memory device by improving the cycling characteristics during the read operation.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 and 3 illustrate a method of reading a flash memory device according to an exemplary embodiment of the present invention. 2 is a circuit diagram illustrating a method of reading a flash memory device according to an embodiment of the present invention, and FIG. 3 is a flash memory parallel to a cell string to explain a method of reading a flash memory device according to an embodiment of the present invention. It is sectional drawing which cut | disconnected the element.

2 and 3, a flash memory device according to an embodiment of the present invention may include a plurality of memory cells MC0,... MCn-1, MCn, MCn + 1. Includes a cell string 210 connected in series between the drain select transistor DST and the source select transistor SST. Here, the drain select transistor DST selectively connects the cell string 210 and the bit lines BLO and BLe. In addition, the source select transistor SST selectively connects the cell string 210 and the common source line CSL connected to the ground terminal.

The plurality of cell strings 210 connected to the plurality of bit lines BLO and BLe are connected to the common source line CSL in parallel to form a memory cell block. Memory cells constituting the cell string 210 (MC0, ... MCn-1, MCn, MCn + 1 ..., MCm; m, n is a natural number), a source select transistor (DST) and a drain select transistor (SST) Gates are formed of stacked gates in which a tunnel insulating film 303, a floating gate first conductive film 305, a dielectric film 307, and a control gate second conductive film 309 are sequentially stacked. The second conductive layer 309 of the source select transistor DST and the drain select transistor SST is electrically connected to the first conductive layer 305 through a contact hole formed in the dielectric layer 307. In addition, the gates in the cell string 210 may be electrically connected through the junction region 301a.

The word lines WLa, WLb, and WLc, the drain select line DSL, or the source select line formed with the second conductive layer 309 of the cell string 210 arranged in parallel to intersect the cell string 210. SSL). In more detail, the second conductive layers 309 of the memory cells arranged in parallel with and intersecting with the cell string 210 are connected to form word lines WLa, WLb, and WLc, and the second of the drain select transistor DST. The conductive layer 309 is connected to form a drain select line DSL, and the second conductive layer 309 of the source select transistor SST is connected to form a source select line SSL. Cell strings 210 arranged side by side are connected through the drain select line DSL, the word lines WLa, WLb, and WLc, and the source select line SSL.

Table 1 shows voltages applied to the cell string 210 during a read operation of a flash memory device according to an embodiment of the present invention.

Node name Applied voltage WLa Vread WLb (at least one of WLa ± 1) Vpass1 WLc Vpass2 DSL Vcc SSL Vcc CSL 0 BL (BLe) selected To 1 Unselected BL (BLo) 0 Bulk 0

Referring to FIGS. 2, 3 and Table 1, the power supply voltage Vcc is applied to the drain select line DSL for the read operation to precharge the selected bit line BLe and the channel.

Thereafter, the read voltage Vread is applied to the selected first word line WLa among the word lines, and the first pass voltage Vpass1 is applied to the second word line WLb adjacent to the first word line WLa. The second pass voltage Vpass2 is applied to the remaining word lines WLc.

The read voltage Vread may be set at various levels according to the state of the cell A to be read. For example, since a memory cell has four states in a multi-level cell (MLC), the read voltage may be any one of 0 V, 1.5 V, and 3 V according to each state of the cell A to be read. In this case, when the threshold voltage of the cell A to be read is at a level higher than the read voltage Vread, the cell A to be read may be in an off state even if the read voltage is applied. On the other hand, when the threshold voltage of the cell A to be read is applied at a level lower than the read voltage Vread, the cell A to be read may be in an on state.

The first and second pass voltages Vpass1 and Vpass2 are voltages for turning on memory cells connected to the unselected word lines WLb and WLc. The second pass voltage Vpass2 is typically a voltage for turning on the memory cells, which is lower than the first pass voltage Vpass1. The first pass voltage Vpass1 is typically a voltage higher than a voltage for turning on the memory cells, and a voltage applied to not only turn on the memory cells but also to improve a cell current that decreases as charge is trapped in the tunnel insulating layer 303. to be. For example, the second pass voltage Vpass2 is 5V to 8V, more preferably 6.5V. The first pass voltage Vpass1 is 6V to 9V, more preferably 7.5V.

Since the first pass voltage Vpass1 is higher than the second pass voltage Vpass2, the cell current is increased when the first and second pass voltages Vpass1 and Vpass2 are applied than when only the second pass voltage Vpass2 is applied. Can be. That is, by applying the first pass voltage Vpass1 higher than the second pass voltage Vpass2, the same effect as that of the threshold voltage of the corresponding cell is lowered. Accordingly, as shown in FIG. 4, as the pass voltage applied during the read operation is adjusted upward, the enlarged threshold voltage distribution after cycling is improved.

Meanwhile, when the first pass voltage Vpass1 is applied to all of the unselected word lines WLb and WLc, cycling characteristics of all cells connected to the unselected word lines WLb and WLc may be improved. However, even though the current flowing through the cell string 210 connected to the selected bit line BLe is greatly increased and the threshold voltage of the cell A to be read is higher than the read voltage Vread, the threshold voltage is equal to the read voltage (Vread). Read disturb, which is recognized as a cell below Vread, may occur. Therefore, in the present invention, the first pass voltage Vpass1 is applied to the second word line WLb adjacent to the first word line WLa, and the second pass voltage Vpass2 is applied to the remaining unselected word lines WLc. Is applied. More specifically, the first pass voltage Vpass1 may be applied to the second word line WLb = WLa + 1 adjacent to the first word line WLa between the first word line WLa and the drain select transistor DST. Can be. Alternatively, the first pass voltage Vpass1 may be applied to the second word line WLb = WLa−1 adjacent to the first word line WLa between the first word line WLa and the source select transistor SST. . Alternatively, the first pass voltage Vpass1 may be adjacent to the first word line WLa between the first word line WLa and the drain select transistor DST, and between the first word line WLa and the source select transistor SST. The second word lines WLb = WLa ± 1 may be applied.

When the first pass voltage Vpass1 is applied to at least one of the second word lines WLb = WLa ± 1 adjacent to the first word line WLa, the tunnel insulating layer 303 of the cell A to be read. The electric field applied to the edge can be improved to have the same effect as the junction overlap of the cell A to be read out is improved. That is, during the read operation, the threshold voltage of the cell A to be read may be lowered by applying a relatively high first pass voltage Vpass1 to the cells adjacent to the cell A to be read. Therefore, the present invention can suppress the phenomenon that the threshold voltage is expanded due to the low reading of the threshold voltage during the read operation even when the threshold voltage is high after cycling.

On the other hand, the expansion of the threshold voltage after cycling is intensified when the states of the memory cells are distributed in a checker-board (CKBD) pattern in which two states (for example, PV1 and PV2) are alternated. Therefore, the read operation according to the embodiment of the present invention is effective when applied to CKBD memory cells.

As described above, the present invention reduces the risk of read disturb and increases the distribution of the threshold voltage after cycling by applying upward the pass voltage of the word line adjacent to the cell to be read so that the threshold voltage is read low during the read operation. The phenomenon can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a diagram for explaining threshold voltage distribution characteristics of a memory cell after cycling;

2 is a circuit diagram illustrating a method of reading a flash memory device according to an embodiment of the present invention.

3 is a cross-sectional view of the flash memory device taken along line with a cell string to explain a method of reading a flash memory device according to an exemplary embodiment of the present invention.

4 is a view for explaining that the threshold voltage distribution is improved when the pass voltage is adjusted upward.

<Explanation of symbols for the main parts of the drawings>

210: cell string 301: semiconductor substrate

301a: junction region 303: tunnel insulating film

305: First conductive film 307: Dielectric film

309: second conductive film

Claims (6)

Precharging the bit line; A read voltage is applied to selected first word lines among the word lines, a first pass voltage is applied to a second word line adjacent to the first word line, and a lower than the first pass voltage is applied to the remaining word lines. Applying a two pass voltage; And Detecting a change in voltage of the bit line. The method of claim 1, The first pass voltage is a data read of a flash memory device applied to the second word line adjacent to the first word line in a direction of the drain select line among a drain select line and a source select line facing each other with the word lines therebetween. Way. The method of claim 1, The first pass voltage is a data read of a flash memory device applied to the second word line adjacent to the first word line in a direction of the source select line among the drain select line and the source select line facing each other with the word lines interposed therebetween. Way. The method of claim 1, The first pass voltage is applied to the second word line adjacent to the first word line in the drain select line direction and the source select line direction among the drain select line and the source select line facing each other with the word lines interposed therebetween. A method of reading data from a flash memory device. The method of claim 1, The first pass voltage is a data read method of a flash memory device of 6V to 9V. The method of claim 1, And a second pass voltage of about 5V to about 8V.

Images