US8804427B2 - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory device Download PDFInfo
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- US8804427B2 US8804427B2 US14/094,438 US201314094438A US8804427B2 US 8804427 B2 US8804427 B2 US 8804427B2 US 201314094438 A US201314094438 A US 201314094438A US 8804427 B2 US8804427 B2 US 8804427B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
Definitions
- Embodiments described in this specification relate to an electrically data-rewritable nonvolatile semiconductor memory device.
- a semiconductor memory device employing transistors of a circular cylindrical type structure represents one such conventional semiconductor memory device having memory cells disposed three-dimensionally.
- FIG. 1 is a block diagram of a nonvolatile semiconductor memory device in accordance with a first embodiment.
- FIG. 2 is a schematic perspective view of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 3 is a circuit diagram of a memory cell array 1 in accordance with the first embodiment.
- FIG. 4A is a cross-sectional view of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 4B is a cross-sectional view of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 5 is an enlarged view of FIG. 4A .
- FIG. 6 is a schematic view of during a first erase operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 7 is a timing chart of during the first erase operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 8A is a schematic view of during a first write operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 8B is a schematic view of during the first write operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 9 is a timing chart of during the first write operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 10 is a schematic view of during a first read operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 11 is a timing chart of during the first read operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 12 is a timing chart of during a second erase operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 13 is a timing chart of during a second write operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 14 is a timing chart of during a second read operation in the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 15 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 16 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 17 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 18 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment.
- FIG. 19 is a circuit diagram of a memory cell array 1 in accordance with a second embodiment.
- FIG. 20 is a cross-sectional view of a nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 21 is a schematic view of during an erase operation in the nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 22 is a timing chart of during the erase operation in the nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 23A is a schematic view of during a write operation in the nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 23B is a schematic view of during the write operation in the nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 24 is a timing chart of during the write operation in the nonvolatile semiconductor memory device in accordance with the second embodiment.
- FIG. 25 is a cross-sectional view of a nonvolatile semiconductor memory device in accordance with a third embodiment.
- FIG. 26 is a cross-sectional view of a nonvolatile semiconductor memory device in accordance with a fourth embodiment.
- FIG. 27 is a cross-sectional view of a nonvolatile semiconductor memory device in accordance with a fifth embodiment.
- FIG. 28 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fifth embodiment.
- FIG. 29 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fifth embodiment.
- FIG. 30 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fifth embodiment.
- FIG. 31 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fifth embodiment.
- FIG. 32 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fifth embodiment.
- a nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of memory blocks, a first line, a second line, and a control circuit.
- Each of the plurality of memory blocks includes a plurality of cell units and is configured as a smallest unit of an erase operation.
- the first line is provided commonly to the plurality of memory blocks and is connected to one ends of the plurality of cell units.
- the second line is connected to the other ends of the plurality of cell units.
- the control circuit is configured to control a voltage applied to the plurality of memory blocks.
- Each of the plurality of cell units comprises a memory string, a first transistor, a second transistor, and a diode.
- the memory string is configured by a plurality of memory transistors connected in series, the memory transistors being electrically rewritable.
- the first transistor has one end connected to one end of the memory string.
- the second transistor is provided between the other end of the memory string and the second line.
- the diode is provided between the first transistor and the first line and has a forward bias direction from a side of the first transistor to a side of the first line.
- the memory string comprises a first semiconductor layer, a charge storage layer, and a first conductive layer.
- the first semiconductor layer includes a columnar portion extending in a perpendicular direction with respect to a substrate and is configured to function as a body of the memory transistors.
- the charge storage layer is formed to surround a side surface of the columnar portion and is configured to be capable of storing a charge.
- the first conductive layer is formed commonly in the plurality of memory blocks to surround the side surface of the columnar portion with the charge storage layer interposed therebetween and is configured to function as agate of the memory transistors.
- the diode comprises a second semiconductor layer and a third semiconductor layer.
- the second semiconductor layer is configured as a first conductivity type extending in the perpendicular direction with respect to the substrate.
- the third semiconductor layer is configured as a second conductivity type being in contact with an upper surface of the second semiconductor layer and extending in the perpendicular direction with respect to the substrate.
- the control circuit is configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the first line higher than a voltage of a gate of the first transistor by a first voltage to generate a GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by a second voltage.
- the control circuit is configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the first line and the voltage of the gate of the first transistor to a third voltage different from the first voltage for prohibiting generation of the GIDL current.
- a nonvolatile semiconductor memory device in accordance with another embodiment comprises a plurality of memory blocks, a first line, a second line, and a control circuit.
- Each of the memory blocks is configured as an arrangement of a plurality of cell units and is configured as a smallest unit of an erase operation.
- the first line is provided commonly to the plurality of memory blocks and is connected to one ends of the plurality of cell units.
- the second line is connected to the other ends of the plurality of cell units.
- the control circuit is configured to control a voltage applied to the plurality of memory blocks.
- Each of the plurality of cell units comprises a memory string, a first transistor, a second transistor, and a diode.
- the memory string is configured by a plurality of memory transistors connected in series, the memory transistors being electrically rewritable.
- the first transistor has one end connected to one end of the memory string.
- the second transistor is provided between the other end of the memory string and the second line.
- the diode is provided between the first transistor and the first line and has a forward bias direction from a side of the first line to a side of the first transistor.
- the memory string comprises a first semiconductor layer, a charge storage layer, and a first conductive layer.
- the first semiconductor layer includes a columnar portion extending in a perpendicular direction with respect to a substrate and is configured to function as a body of the memory transistors.
- the charge storage layer is formed to surround a side surface of the columnar portion and is configured to be capable of storing a charge.
- the first conductive layer is formed commonly in the plurality of memory blocks to surround the side surface of the columnar portion with the charge storage layer interposed therebetween and is configured to function as a gate of the memory transistors.
- the diode comprises a second semiconductor layer and a third semiconductor layer.
- the second semiconductor layer is configured as a first conductivity type extending in the perpendicular direction with respect to the substrate.
- the third semiconductor layer is configured as a second conductivity type being in contact with the second semiconductor layer and extending in the perpendicular direction with respect to the substrate.
- the control circuit is configured to perform the erase operation in a selected one of the memory blocks by setting a voltage of the second line higher than a voltage of a gate of the second transistor by a first voltage to generate a GIDL current for raising a voltage of the body of the memory transistors, and setting a voltage of the gate of the memory transistors lower than the voltage of the body of the memory transistors by a second voltage.
- the control circuit is configured to prohibit the erase operation in an unselected one of the memory blocks by setting a voltage difference between the voltage of the second line and the voltage of the gate of the second transistor to a third voltage different from the first voltage for prohibiting generation of the GIDL current.
- FIG. 1 is a block diagram of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention
- FIG. 2 is a schematic perspective view of the nonvolatile semiconductor memory device in accordance with the first embodiment of the present invention.
- the nonvolatile semiconductor memory device in accordance with the first embodiment includes a memory cell array 1 and a control circuit 1 A, as shown in FIG. 1 .
- the memory cell array 1 is configured by memory transistors MTr 1 -MTr 4 arranged in a three-dimensional matrix, each of the memory transistors being configured to store data electrically, as shown in FIG. 2 . That is, the memory transistors MTr 1 -MTr 4 , in addition to being arranged in a matrix in a horizontal direction, are arranged also in a stacking direction (perpendicular direction with respect to a substrate).
- a plurality of the memory transistors MTr 1 -MTr 4 aligned in the stacking direction are connected in series to configure a publicly known memory string MS (NAND string).
- MS non-transistive memory string
- Changing an amount of charge stored in a charge storage layer of the memory transistors MTr 1 -MTr 4 causes a threshold voltage of the memory transistors MTr 1 -MTr 4 to change.
- Changing the threshold voltage causes data retained in the memory transistors MTr 1 -MTr 4 to be rewritten.
- Connected respectively one each to the two ends of the memory string MS are a drain side select transistor SDTr and a source side select transistor SSTr which are turned on when the memory string MS is selected.
- drain side select transistor SDTr has its drain connected via a diode D 1 to a bit line BL
- the source side select transistor SSTr has its source connected to a source line SL. Note that specific circuit configurations and stacking structure of the memory cell array 1 are described later.
- the control circuit 1 A is configured to control a voltage applied to the memory cell array 1 (memory block BK to be described later).
- the control circuit 1 A comprises row decoders 2 and 3 , a sense amplifier 4 , a column decoder 5 , and a control signal generating unit (high voltage generating unit) 6 .
- the row decoders 2 and 3 decode downloaded block address signals and so on to control the memory cell array 1 .
- the sense amplifier 4 reads data from the memory cell array 1 .
- the column decoder 5 decodes a column address signal to control the sense amplifier 4 .
- the control signal generating unit 6 boosts a reference voltage to generate a high voltage required during write and erase, and, moreover, generates a control signal to control the row decoders 2 and 3 , the sense amplifier 4 , and the column decoder 5 .
- the memory cell array 1 includes a plurality of memory blocks BK_ 1 , BK_ 2 , . . . , BK_n, a plurality of bit lines BL 1 , BL 2 , . . . , BLn, and a plurality of source lines SL 1 , SL 2 , . . . , SLn.
- memory blocks are sometimes collectively referred to as memory block BK, instead of specifying either one of BK_ 1 , BK_ 2 , BK_n.
- Bit lines are sometimes collectively referred to as bit line BL, instead of specifying either one of BL 1 , BL 2 , . . . , BLn.
- Source lines are sometimes collectively referred to as source line SL, instead of specifying either one of SL 1 , SL 2 , . . . , SLn.
- Each of the memory blocks BK includes a plurality of cell units MU and is configured as a smallest unit of an erase operation for erasing data.
- Each of the bit lines BL is provided commonly to the memory blocks BK_ 1 , BK_ 2 , . . . , BK_n.
- Each of the bit lines BL is connected to drains of a plurality of the cell units MU.
- Each of the source lines SL is provided divided on a memory block BK basis.
- Each of the source lines SL is connected commonly to sources of a plurality of cell units MU in one memory block BK.
- each one of the memory blocks BK has the cell units MU provided in a matrix over k rows and n columns.
- Each of the cell units MU includes the memory string MS, the drain side select transistor SDTr, the source side select transistor SSTr, and the diode D 1 .
- the memory string MS is configured by the memory transistors MTr 1 -MTr 4 connected in series.
- the drain side select transistor SDTr is connected to a drain of the memory string MS (drain of the memory transistor MTr 4 ).
- the source side select transistor SSTr is connected to a source of the memory string MS (source of the memory transistor MTr 1 ).
- the memory string MS may be configured by more than four memory transistors.
- the memory transistors MTr 1 arranged in a matrix in the plurality of memory blocks BK have their gates connected commonly to a word line WL 1 .
- the memory transistors MTr 2 -MTr 4 have their gates commonly connected to word lines WL 2 -WL 4 , respectively.
- the drain side select transistors SDTr arranged in a line in a row direction in the memory block BK_ 1 have their gates connected commonly to one drain side select gate line SGD 1 , 1 (or SGD 1 , 2 , . . . , SGD 1 , k ).
- the drain side select transistors SDTr arranged in a line in the row direction in the memory block BK_ 2 have their gates connected commonly to one drain side select gate line SGD 2 , 1 (or SGD 2 , 2 , . . . , SGD 2 , k ).
- drain side select transistors SDTr arranged in a line in the row direction in the memory block BK_n have their gates connected commonly to one drain side select gate line SGDn, 1 (or SGDn, 2 , . . . , SGDn,k).
- drain side select gate lines are sometimes collectively referred to as drain side select gate lines SGD, instead of specifying either one of SGD 1 , 1 , . . . , SGDn,k.
- the drain side select gate lines SGD are each provided to extend in the row direction and having a certain pitch in a column direction.
- drain side select transistors SDTr arranged in a line in the column direction have their other ends connected commonly via a respective diode D 1 to one bit line BL 1 (or BL 2 , . . . , BLn).
- the diode D 1 is provided to have a forward bias direction from a side of the drain side select transistor SDTr to a side of the bit line BL.
- the bit line BL is formed to extend in the column direction straddling the memory blocks BK.
- the source side select transistors SSTr arranged in a line in the row direction in the memory block BK_ 1 have their gates connected commonly to one source side select gate line SGS 1 , 1 (or SGS 1 , 2 , . . . , SGS 1 , k ).
- the source side select transistors SSTr arranged in a line in the row direction in the memory block BK_ 2 have their gates connected commonly to one source side select gate line SGS 2 , 1 (or SGS 2 , 2 , . . . , SGS 2 , k ).
- the source side select transistors SSTr arranged in a line in the row direction in the memory block BK_n have their gates connected commonly to one source side select gate line SGSn, 1 (or SGSn, 2 , . . . , SGSn,k). Note that source side select gate lines are sometimes collectively referred to as source side select gate lines SGS, instead of specifying either one of SGS 1 , 1 , . . . , SGSn,k.
- the source side select gate lines SGS are each provided to extend in the row direction and having a certain pitch in the column direction.
- all the source side select transistors SSTr in the memory block BK_ 1 are connected commonly to one source line SL 1 .
- all the source side select transistors SSTr in the memory block BK_ 2 are connected commonly to one source line SL 2
- all the source side select transistors SSTr in the memory block BK_n are connected commonly to one source line SLn.
- the nonvolatile semiconductor memory device in accordance with the first embodiment includes a semiconductor substrate 10 , and, stacked sequentially on the semiconductor substrate 10 , a source side select transistor layer 20 , a memory transistor layer 30 , a drain side select transistor layer 40 , a diode layer 50 , and a wiring layer 60 .
- the semiconductor substrate 10 functions as the source line SL.
- the source side select transistor layer 20 functions as the source side select transistor SSTr.
- the memory transistor layer 30 functions as the memory string MS (memory transistors MTr 1 -MTr 4 ).
- the drain side select transistor layer 40 functions as the drain side select transistor SDTr.
- the diode layer 50 functions as the diode D 1 .
- the wiring layer 60 functions as the bit line BL and as various other wirings.
- the semiconductor substrate 10 includes a diffusion layer 11 in its upper surface, as shown in FIGS. 4A and 4B .
- the diffusion layer 11 functions as the source line SL.
- the diffusion layer 11 is divided on a memory block BK basis.
- the source side select transistor layer 20 includes a source side conductive layer 21 disposed on the semiconductor substrate 10 via an insulating layer, as shown in FIGS. 4A and 4B .
- the source side conductive layer 21 functions as the gate of the source side select transistor SSTr and as the source side select gate line SGS.
- the source side conductive layer 21 is formed in stripes in each of the memory blocks MB, the stripes extending in the row direction and having a certain pitch in the column direction.
- the source side conductive layer 21 is configured by polysilicon (poly-Si).
- the source side select transistor layer 20 includes a source side hole 22 .
- the source side hole 22 is formed to penetrate the source side conductive layer 21 .
- the source side holes 22 are formed in a matrix in the row direction and the column direction.
- the source side select transistor layer 20 includes a source side gate insulating layer 23 and a source side columnar semiconductor layer 24 .
- the source side columnar semiconductor layer 24 functions as a body (channel) of the source side select transistor SSTr.
- the source side gate insulating layer 23 is formed with a certain thickness on a side wall of the source side hole 22 .
- the source side columnar semiconductor layer 24 is formed to be in contact with a side surface of the source side gate insulating layer 23 and to fill the source side hole 22 .
- the source side columnar semiconductor layer 24 is formed in a column shape extending in the stacking direction (perpendicular direction with respect to the semiconductor substrate 10 ).
- the source side columnar semiconductor layer 24 is formed on the diffusion layer 11 .
- the source side gate insulating layer 23 is configured by silicon oxide (SiO 2 ).
- the source side columnar semiconductor layer 24 is configured by polysilicon (poly-Si).
- the source side conductive layer 21 is formed to surround the source side columnar semiconductor layer 24 with the source side gate insulating layer 23 interposed therebetween.
- the memory transistor layer 30 includes word line conductive layers 31 a - 31 d stacked sequentially on the source side select transistor layer 20 with insulating layers interposed therebetween, as shown in FIGS. 4A and 4B .
- the word line conductive layers 31 a - 31 d function, respectively, as the gates of the memory transistors MTr 1 -MTr 4 and as the word lines WL 1 -WL 4 .
- the word line conductive layers 31 a - 31 d are formed to extend two-dimensionally in the row direction and the column direction (in a plate-like shape) over the plurality of memory blocks BK.
- the word line conductive layers 31 a - 31 d are configured by polysilicon (poly-Si).
- the memory transistor layer 30 includes a memory hole 32 .
- the memory hole 32 is formed to penetrate the word line conductive layers 31 a - 31 d .
- the memory holes 32 are formed in a matrix in the row direction and the column direction.
- the memory hole 32 is formed at a position aligning with the source side hole 22 .
- the memory transistor layer 30 includes a memory gate insulating layer 33 and a memory columnar semiconductor layer 34 .
- the memory columnar semiconductor layer 34 functions as a body (channel) of the memory transistors MTr 1 -MTr 4 .
- the memory gate insulating layer 33 is formed with a certain thickness on a side wall of the memory hole 32 .
- the memory columnar semiconductor layer 34 is formed to be in contact with a side surface of the memory gate insulating layer 33 and to fill the memory hole 32 .
- the memory columnar semiconductor layer 34 is formed in a column shape extending in the stacking direction.
- the memory columnar semiconductor layer 34 is formed having its lower surface in contact with an upper surface of the source side columnar semiconductor layer 24 .
- FIG. 5 is an enlarged view of FIG. 4A .
- the memory gate insulating layer 33 includes, from a side surface of the memory hole 32 side to a memory columnar semiconductor layer 34 side, a block insulating layer 33 a , a charge storage layer 33 b , and a tunnel insulating layer 33 c .
- the charge storage layer 33 b is configured to be capable of storing a charge.
- the block insulating layer 33 a is formed with a certain thickness on a side wall of the memory hole 32 .
- the charge storage layer 33 b is formed with a certain thickness on a side wall of the block insulating layer 33 a .
- the tunnel insulating layer 33 c is formed with a certain thickness on a side wall of the charge storage layer 33 b .
- the block insulating layer 33 a and the tunnel insulating layer 33 c are configured by silicon oxide (SiO 2 ).
- the charge storage layer 33 b is configured by silicon nitride (SiN).
- the memory columnar semiconductor layer 34 is configured by polysilicon (poly-Si).
- the word line conductive layers 31 a - 31 d are formed to surround the memory columnar semiconductor layer 34 with the memory gate insulating layer 33 interposed therebetween.
- the drain side select transistor layer 40 includes a drain side conductive layer 41 , as shown in FIGS. 4A and 4B .
- the drain side conductive layer 41 functions as the gate of the drain side select transistor SDTr and as the drain side select gate line SGD.
- the drain side conductive layer 41 is stacked on the memory transistor layer 30 via an insulating layer.
- the drain side conductive layer 41 is formed directly above the memory columnar semiconductor layer 34 .
- the drain side conductive layer 41 is formed in stripes in each of the memory blocks BK, the stripes extending in the row direction and having a certain pitch in the column direction.
- the drain side conductive layer 41 is configured by, for example, polysilicon (poly-Si).
- the drain side select transistor layer 40 includes a drain side hole 42 .
- the drain side hole 42 is formed to penetrate the drain side conductive layer 41 .
- the drain side holes 42 are formed in a matrix in the row direction and the column direction.
- the drain side hole 42 is formed at a position aligning with the memory hole 32 .
- the drain side select transistor layer 40 includes a drain side gate insulating layer 43 and a drain side columnar semiconductor layer 44 .
- the drain side columnar semiconductor layer 44 functions as a body (channel) of the drain side select transistor SDTr.
- the drain side gate insulating layer 43 is formed with a certain thickness on a side wall of the drain side hole 42 .
- the drain side columnar semiconductor layer 44 is formed to be in contact with the drain side gate insulating layer 43 and to fill the drain side hole 42 .
- the drain side columnar semiconductor layer 44 is formed in a column shape to extend in the stacking direction.
- the drain side columnar semiconductor layer 44 is formed having its lower surface in contact with an upper surface of the memory columnar semiconductor layer 34 .
- the drain side gate insulating layer 43 is configured by silicon oxide (SiO 2 ).
- the drain side columnar semiconductor layer 44 is configured by polysilicon (poly-Si).
- the drain side columnar semiconductor layer 44 has its lower portion 44 a configured by an intrinsic semiconductor and its upper portion 44 b configured by an N + type semiconductor.
- the drain side conductive layer 41 is formed to surround the drain side columnar semiconductor layer 44 with the drain side gate insulating layer 43 interposed therebetween.
- the diode layer 50 includes an ohmic contact layer 51 , a P type semiconductor layer 52 , and an N type semiconductor layer 53 , as shown in FIGS. 4A and 4B .
- the ohmic contact layer 51 causes ohmic contact between the P type semiconductor layer 52 and the drain side columnar semiconductor layer 44 .
- the P type semiconductor layer 52 and the N type semiconductor layer 53 function as the diode D 1 .
- the ohmic contact layer 51 is formed in a column shape extending in the stacking direction from an upper surface of the drain side columnar semiconductor layer 44 .
- the P type semiconductor layer 52 is formed in a column shape extending in the stacking direction from an upper surface of the ohmic contact layer 51 .
- the N type semiconductor layer 53 is formed in a column shape extending in the stacking direction from an upper surface of the P type semiconductor layer 52 .
- the P type semiconductor layer 52 is configured by polysilicon doped with a P type impurity.
- the N type semiconductor layer 53 is configured by polysilicon doped with an N type impurity.
- the wiring layer 60 includes a bit layer 61 , as shown in FIGS. 4A and 4B .
- the bit layer 61 functions as the bit line BL.
- the bit layer 61 is formed to be in contact with an upper surface of the N type semiconductor layer 53 .
- the bit layer 61 is formed to extend in the column direction and having a certain pitch in the row direction.
- the bit layer 61 is configured by a metal such as tungsten.
- memory block BK 1 is assumed to be selected as object of the erase operation.
- memory block BK_ 2 which shares bit lines BL with memory block BK_ 1 , is not an object of the erase operation, and erase of data retained in memory block BK_ 2 is prohibited.
- a voltage Vera (for example, about 17 V) is applied to bit line BL 1 .
- source line SL 1 is applied with voltage Vera
- drain side select gate lines SGD and source side select gate lines SGS are applied with a voltage Vera- ⁇ V that is smaller than voltage Vera by ⁇ V (for example, about 3 V).
- source line SL 2 is applied with 0 V
- voltage Vera of bit line BL 1 is higher than voltage Vera- ⁇ V of gates of drain side select transistors SDTr by an the voltage ⁇ V.
- voltage Vera of source line SL 1 is higher than voltage Vera- ⁇ V of gates of source side select transistors SSTr by the voltage ⁇ V.
- This causes a GIDL current (refer to symbol “E 11 ”) to occur proximal to gates of source side select transistors SSTr and drain side select transistors SDTr in memory block BK_ 1 .
- holes caused by the GIDL current flow into the body of memory transistors MTr 1 -MTr 4 , causing a voltage of the body of memory transistors MTr 1 -MTr 4 to rise.
- a voltage of the gates of the memory transistors MTr 1 -MTr 4 is set to 0 V, in other words, is set lower than the voltage of the body of memory transistors MTr 1 -MTr 4 .
- a high voltage is applied to the charge storage layer of memory transistors MTr 1 -MTr 4 , whereby the erase operation on memory block BK_ 1 is executed.
- a voltage of gates of the drain side select transistors SDTr is set to 0 V. That is, a voltage Vera of bit line BL 1 is set higher than a voltage (0 V) of gates of the drain side select transistors SDTr by Vera.
- source line SL 2 is set to 0 V
- a voltage of gates of the source side select transistors SSTr is set to the power supply voltage Vdd (for example, 1.2 V). That is, a voltage (Vdd) of gates of the source side select transistors SSTr is set higher than a voltage (0 V) of source line SL 2 by Vera.
- gates of the memory transistors MTr 1 -MTr 4 are connected commonly between memory blocks BK_ 1 and BK_ 2 by the word lines WL 1 -WL 4 .
- gates of memory transistors MTr 1 -MTr 4 have their voltage set to 0 V in memory block BK_ 2 as well as in memory block BK_ 1 .
- the voltage of the body of memory transistors MTr 1 -MTr 4 is not boosted by the GIDL current.
- the source side select transistors SSTr are turned on, hence, even if the voltage of the body of memory transistors MTr 1 -MTr 4 rises due to effects of leak current and so on, that voltage is discharged to source line SL 2 via those turned-on source side select transistors SSTr (refer to symbol “E 12 ”).
- the first embodiment includes the diode D 1 . This may suppress a current flowing from bit line BL 1 into the body of memory transistors MTr 1 -MTr 4 in unselected memory block BK_ 2 (refer to symbol “E 13 ”).
- the first embodiment may suppress incorrect erase in unselected memory block BK_ 2 .
- a specific operation procedure when executing the above-described erase operation is described with reference to a timing chart in FIG. 7 .
- the voltage of bit line BL 1 and voltage of source line SL 1 are raised to erase voltage Vera (for example, 17V).
- the voltage of source side select gate lines SGS 1 , 1 -SGS 1 , k and voltage of drain side select gate lines SGD 1 , 1 -SGD 1 , k are raised to voltage Vera- ⁇ V (for example, 14 V). This causes the GIDL current to occur in memory block BK_ 1 .
- the voltage of source line SL 2 is maintained at 0 V.
- the voltage of source side select gate lines SGS 2 , 1 -SGS 2 , k is raised to the power supply voltage Vdd, and the voltage of drain side select gate lines SGD 2 , 1 -SGD 2 , k is maintained at 0 V.
- the GIDL current does not occur in memory block BK_ 2 , and the source side select transistors SSTr are turned on.
- the voltage of word lines WL 1 -WL 4 is lowered to 0 V. This causes data in the memory transistors MTr 1 -MTr 4 in memory block BK_ 1 to be erased, and data in the memory transistors MTr 1 -MTr 4 in memory block BK_ 2 to be retained (not erased).
- FIGS. 8A and 8B an example is described of the case in which a cell unit MU (hereafter referred to as selected cell unit sMU) in memory block BK_ 1 is selected as write target. Description proceeds assuming write to be performed on memory transistor MTr 3 (hereafter referred to as selected memory transistor sMTr 3 ) in the selected cell unit sMU.
- the memory transistors MTr 1 -MTr 4 included in memory blocks BK_ 1 and BK_ 2 are applied with a pass voltage Vpass (for example, 10 V) at their gates and turned on.
- the source side select transistors SSTr are applied with a voltage Vdd+Vt at their gates and turned on. This causes the voltage of the body of the memory transistors MTr 1 -MTr 4 included in memory blocks BK_ 1 and BK_ 2 to be charged to the power supply voltage Vdd via source lines SL 1 and SL 2 (refer to symbol “W 11 ”).
- the voltage of the body of the memory transistors MTr 1 -MTr 4 included in memory blocks BK_ 1 and BK_ 2 is set to not less than the power supply voltage Vdd that may be applied to bit line BL 1 during the write operation. Moreover, after a certain time, the source side select transistors SSTr are turned off again.
- the drain side select transistors SDTr included in selected cell unit sMU are supplied with voltage Vdd+Vt at their gates.
- the drain side select transistors SDTr are turned on, whereby the voltage of the body of the memory transistors MTr 1 -MTr 4 included in selected cell unit sMU are discharged to the same 0 V as bit line BL 1 (refer to symbol “W 12 ”).
- the drain side select transistors SDTr remain turned off, hence, the body of the memory transistors MTr 1 -MTr 4 included in selected cell unit sMU is not discharged but set to a floating state, whereby its potential is retained at the power supply voltage Vdd.
- Vprg program voltage
- the voltage of the body of selected memory transistor sMTr 3 is discharged to 0 V, hence, a high voltage is applied to the charge storage layer of selected memory transistor sMTr 3 , whereby the write operation on selected memory transistor sMTr 3 is executed.
- gates of the memory transistors MTr 1 -MTr 4 are connected commonly by the word lines WL 1 -WL 4 over a plurality of the cell units MU. If the voltage of the gate of selected memory transistor sMTr 3 is set to the program voltage Vprg, the gates of memory transistors MTr 3 included in unselected cell units MU are also applied with the program voltage Vprg. However, the voltage of the body of memory transistors MTr 1 -MTr 4 included in unselected cell units MU is set to the floating state by the turned-off drain side select transistors SDTr and source side select transistors SSTr. As a result, a high voltage is not applied to the charge storage layer of memory transistors MTr 3 included in unselected cell units MU, whereby the write operation is not executed on those memory transistors.
- a specific operation procedure when executing the above-described write operation is described with reference to a timing chart in FIG. 9 .
- the voltage of source lines SL 1 and SL 2 is raised to the power supply voltage Vdd
- the voltage of source side select gate lines SGS 1 , 1 -SGS 1 , k and SGS 2 , 1 -SGS 2 , k is raised to voltage Vdd+Vt.
- the voltage of word lines WL 1 -WL 4 is raised to the pass voltage Vpass.
- bit line BL 1 is lowered to 0 V during a “0” data write, and is raised to the power supply voltage Vdd during a “1” data retention.
- drain side select gate line SGD 1 , 2 is raised to voltage Vdd+Vt. This causes the drain side select transistor SDTr in selected cell unit sMU only to be turned on.
- Vprog for example, 18 V
- FIG. 10 a first read operation in the nonvolatile semiconductor memory device in accordance with the first embodiment is described with reference to FIG. 10 .
- the read operation is executed on selected memory transistor sMTr 3 .
- bit line BL 1 is set to 0 V.
- Source line SL 1 is set to power supply voltage Vdd
- source line SL 2 is set to 0 V.
- the drain side select transistors SDTr and source side select transistors SSTr included in selected cell unit sMU is applied with voltage Vdd+Vt from the select gate lines SGD 1 , 2 and SGS 1 , 2 , and are turned on.
- the gates of memory transistors MTr 1 , MTr 2 , and MTr 4 are applied with pass voltage Vpass, and the gates of memory transistors MTr 3 are applied with a read voltage Vread (Vread ⁇ Vpass).
- a specific operation procedure when executing the above-described read operation is described with reference to a timing chart in FIG. 11 .
- the voltage of source line SL 1 is raised to the power supply voltage Vdd
- the voltage of source side select gate line SGS 1 , 2 and voltage of drain side select gate line SGD 1 , 2 are raised to voltage Vdd+Vt.
- the voltage of word lines WL 1 , WL 2 , and WL 4 is raised to the pass voltage Vpass. This causes the memory transistors MTr 1 , 2 , 4 , source side select transistors SSTr, and drain side select transistors SDTr to be turned on.
- the voltage of word line WL 3 is raised to the read voltage Vread. Subsequently, detection of the voltage of bit line BL 1 is performed, whereby the read operation on selected memory transistor sMTr 3 is executed.
- the above-described voltage V 1 causes a voltage applied to the gate insulating layer of source side select transistors SSTr and drain side select transistors SDTr in unselected memory block BK_ 2 during the above-described second erase operation to be lower than that during the first erase operation.
- the second erase operation therefore may suppress damage to the source side select transistors SSTr and drain side select transistors SDTr even if those transistors have a low breakdown voltage.
- the first write operation executes a charging process for charging the body of memory transistors MTr 1 -MTr 4 in memory blocks BK_ 1 and BK_ 2 to the power supply voltage Vdd.
- the second write operation omits from the first write operation this charging process of the body to the power supply voltage Vdd. That is, as shown in FIG.
- drain side select gate line SGD 1 , 2 rises from 0 V to Vdd+Vt, whereby the body of the cell unit MU connected to bit lines BL applied with the power supply voltage Vdd are charged to the power supply voltage Vdd to be set to the floating state, and a similar write operation can be executed.
- the voltage applied to gates of memory transistors MTr 1 , 2 , 4 in selected cell unit sMU and the voltage applied to the gate of selected memory transistor sMTr 3 differ from those of the first read operation. That is, as shown in FIG. 14 , at time t 31 , the word line WL 3 is retained at 0 V, and word lines WL 1 , WL 2 , and WL 4 are raised to read voltage Vread.
- the source side select transistor layer 20 , memory transistor layer 30 , and drain side select transistor layer 40 are formed. Now, an upper portion of the drain side hole 42 is not filled but left as is.
- the ohmic contact layer 51 is deposited on an upper portion of the drain side columnar semiconductor layer 44 in the drain side hole 42 .
- the P type semiconductor layer 52 is deposited on an upper portion of the ohmic contact layer 51 in the drain side hole 42 .
- the N type semiconductor layer 53 is deposited on an upper portion of the P type semiconductor layer 52 in the drain side hole 42 .
- the N type semiconductor layer 53 is formed, for example, by depositing polysilicon and then implanting N + ions in the polysilicon.
- FIG. 19 a circuit configuration of a memory cell array 1 included in a nonvolatile semiconductor memory device in accordance with a second embodiment is described with reference to FIG. 19 .
- the second embodiment differs from the first embodiment in having the diode D 1 provided such that its forward bias direction is from the bit line BL side to the drain side select transistor SDTr side. Note that in the second embodiment, identical symbols are assigned to configurations similar to those of the first embodiment, and descriptions thereof are omitted.
- FIG. 20 is a cross-sectional view of the nonvolatile semiconductor memory device in accordance with the second embodiment.
- the diode 50 a includes an N type semiconductor layer 54 and a P type semiconductor layer 55 .
- the N type semiconductor layer 54 is formed in a column shape to extend in the stacking direction from the upper surface of the drain side columnar semiconductor layer 44 .
- the P type semiconductor layer 55 is formed in a column shape to extend in the stacking direction from an upper surface of the N type semiconductor layer 54 .
- the P type semiconductor layer 55 is formed to have its upper surface in contact with a lower surface of the bit layer 61 .
- the N type semiconductor layer 54 is configured by polysilicon doped with an N type impurity
- the P type semiconductor layer 55 is configured by polysilicon doped with a P type impurity.
- the erase operation in the second embodiment differs in this regard from the erase operation in the first embodiment.
- the second embodiment includes a diode D 1 connected in a reverse direction to that of the first embodiment. This may suppress the current flowing from selected memory block BK_ 1 into bit line BL 1 (refer to symbol “E 22 ”). Consequently, no leak current flows in memory block BK_ 2 .
- the above allows the erase operation in the second embodiment to suppress incorrect erase in unselected memory block BK_ 2 .
- bit line BL 1 is retained at 0 V, and drain side select gate lines SGD 2 , 1 -SGD 2 , k and source side select gate lines SGS 2 , 1 -SGS 2 , k are retained at 0 V.
- FIGS. 23A and 23B an example is described assuming write to be performed on memory transistor MTr 3 in selected cell unit sMU in memory block BK_ 1 .
- Source side select transistors SSTr in memory block BK_ 1 are applied with 0 V at their gates, whereby the body of cell units MU in memory block BK_ 1 is once charged to the negative voltage ⁇ VSG.
- drain side select transistors SDTr in memory block BK_ 1 are applied with ⁇ VSG from the start at their gates, whereby, while the body of cell units MU in memory block BK_ 1 is being charged to the negative voltage ⁇ VSG, the drain side select transistors SDTr in memory block BK_ 1 are maintained turned off.
- source line SL 1 has its potential raised from the negative voltage ⁇ VSG to 0 V, and drain side select gate line SGD 1 , 2 connected to selected cell unit sMU is applied with power supply voltage Vdd.
- drain side select gate lines SGD 1 , 1 and SGD 1 , 3 - 1 , k connected to unselected cell units MU in selected memory block BK_ 1 are applied with 0 V, whereby the body of the unselected cell units MU is charged to 0 V or the power supply voltage Vdd to be set to the floating state.
- the write operation on selected memory block BK_ 1 is executed in a similar manner to the first embodiment.
- drain side select gate lines SGD 2 , 1 - 2 , k are maintained at 0 V throughout, and source side select gate lines SGS 2 , 1 - 2 , k and source line SL 2 are maintained at the power supply voltage Vdd throughout.
- FIG. 24 shows a specific timing chart of the above-described operation.
- source line SL 1 and drain side select gate lines SGD 1 , 1 -SGD 1 , k are lowered to the negative voltage ⁇ VSG.
- This causes source side select transistors SSTr in memory block BK_ 1 to be turned on.
- the voltage of the body of memory transistors MTr 1 -MTr 4 included in memory block BK_ 1 is discharged to the same negative voltage ⁇ VSG as source line SL 1 .
- word lines WL 1 -WL 4 are raised to the pass voltage Vpass.
- drain side select gate line SGD 1 , 2 is raised to voltage Vdd+Vt. This causes the drain side select transistor SDTr included in selected cell unit sMU to be turned on, whereby the voltage of the body of memory transistors MTr 1 -MTr 4 included in selected cell unit sMU becomes 0 V or the power supply voltage Vdd (floating state).
- word line WL 3 is raised to the program voltage Vprog. This causes the write operation on selected memory transistor sMTr 3 to be executed.
- a read operation in the nonvolatile semiconductor memory device in accordance with the second embodiment is similar to that of the first embodiment, and description thereof is thus omitted.
- FIG. 25 a stacking structure of a nonvolatile semiconductor memory device in accordance with a third embodiment is described with reference to FIG. 25 .
- identical symbols are assigned to configurations similar to those of the first and second embodiments, and descriptions thereof are omitted.
- the third embodiment includes a diode layer 50 b having a stacking structure substantially similar to that of the first embodiment.
- the diode layer 50 b further includes a P type semiconductor layer 56 configured to extend in a column shape in the stacking direction from the upper surface of the N type semiconductor layer 53 .
- This structure allows a bi-directional diode to be formed as the diode DI.
- FIG. 26 a stacking structure of a nonvolatile semiconductor memory device in accordance with a fourth embodiment is described with reference to FIG. 26 .
- identical symbols are assigned to configurations similar to those of the first through third embodiments, and descriptions thereof are omitted.
- the fourth embodiment includes a diode layer 50 c having a stacking structure substantially similar to that of the second embodiment.
- the diode layer 50 c further includes an N type semiconductor layer 57 configured to extend in a column shape in the stacking direction from the upper surface of the P type semiconductor layer 55 .
- This structure allows a bi-directional diode to be formed as the diode DI.
- the nonvolatile semiconductor memory device in accordance with the fifth embodiment differs greatly from the above-described embodiments in including a U-shaped memory semiconductor layer 84 shown in FIG. 27 in place of the I-shaped memory columnar semiconductor layer 34 of the above-described embodiments.
- the nonvolatile semiconductor memory device in accordance with the fifth embodiment includes, stacked sequentially on the semiconductor substrate 10 , a back gate layer 70 , a memory transistor layer 80 , a select transistor layer 90 , a diode layer 100 , and a wiring layer 110 .
- the memory transistor layer 80 functions as the memory transistors MTr.
- the select transistor layer 90 functions as the drain side select transistor SDTr and as the source side select transistor SSTr.
- the diode layer 100 functions as the diode D 1 .
- the wiring layer 110 functions as the source line SL and as the bit line BL.
- the back gate layer 70 includes a back gate conductive layer 71 , as shown in FIG. 27 .
- the back gate conductive layer 71 is formed to extend two-dimensionally in the row direction and the column direction parallel to the substrate 10 .
- the back gate conductive layer 71 is configured by polysilicon (poly-Si).
- the back gate layer 70 includes a back gate hole 72 , as shown in FIG. 27 .
- the back gate hole 72 is formed to dig out the back gate conductive layer 71 .
- the back gate hole 72 is formed in a substantially rectangular shape having the column direction as a long direction as viewed from an upper surface.
- the back gate holes 72 are formed in a matrix in the row direction and the column direction.
- the memory transistor layer 80 is formed in a layer above the back gate layer 70 , as shown in FIG. 27 .
- the memory transistor layer 80 includes word line conductive layers 81 a - 81 d .
- Each of the word line conductive layers 81 a - 81 d functions as the word line WL and as the gate of the memory transistor MTr.
- the word line conductive layers 81 a - 81 d are stacked sandwiching interlayer insulating layers.
- the word line conductive layers 81 a - 81 d are formed extending with the row direction as a long direction and having a certain pitch in the column direction.
- the word line conductive layers 81 a - 81 d are configured by polysilicon (poly-Si).
- the memory transistor layer 80 includes a memory hole 82 , as shown in FIG. 27 .
- the memory hole 82 is formed to penetrate the word line conductive layers 81 a - 81 d and the interlayer insulating layers.
- the memory hole 82 is formed to align with a near vicinity of an end of the back gate hole 72 in the column direction.
- the back gate layer 70 and the memory transistor layer 80 include a memory gate insulating layer 83 and a memory semiconductor layer 84 , as shown in FIG. 27 .
- the memory semiconductor layer 84 functions as a body of the memory transistors MTr (memory string MS).
- the memory gate insulating layer 83 includes a charge storage layer configured to store a charge, similarly to the above-described embodiments.
- the memory semiconductor layer 84 is formed to fill the back gate hole 72 and the memory hole 82 .
- the memory semiconductor layer 84 is formed in a U shape as viewed from the row direction.
- the memory semiconductor layer 84 includes a pair of columnar portions 84 a extending in the perpendicular direction with respect to the substrate 10 , and a joining portion 84 b configured to join lower ends of the pair of columnar portions 84 a .
- the memory semiconductor layer 84 is configured by polysilicon (poly-Si).
- the back gate conductive layer 71 is formed to surround the joining portion 84 b with the memory gate insulating layer 83 interposed therebetween.
- the word line conductive layers 81 a - 81 d are formed to surround the columnar portions 84 a with the memory gate insulating layer 83 interposed therebetween.
- the select transistor layer 90 includes a source side conductive layer 91 a and a drain side conductive layer 91 b , as shown in FIG. 27 .
- the source side conductive layer 91 a functions as the source side select gate line SGS and as the gate of the source side select transistor SSTr.
- the drain side conductive layer 91 b functions as the drain side select gate line SGD and as the gate of the drain side select transistor SDTr.
- the source side conductive layer 91 a is formed in a layer above one of the columnar portions 84 a configuring the memory semiconductor layer 84 .
- the drain side conductive layer 91 b is in the same layer as the source side conductive layer 91 a and formed in a layer above the other of the columnar portions 84 a configuring the memory semiconductor layer 84 .
- the source side conductive layer 91 a and the drain side conductive layer 91 b are formed in stripes extending in the row direction and having a certain pitch in the column direction.
- the source side conductive layer 91 a and the drain side conductive layer 91 b are configured by polysilicon (poly-Si).
- the select transistor layer 90 includes a source side hole 92 a and a drain side hole 92 b , as shown in FIG. 27 .
- the source side hole 92 a is formed to penetrate the source side conductive layer 91 a .
- the drain side hole 92 b is formed to penetrate the drain side conductive layer 91 b .
- the source side hole 92 a and the drain side hole 92 b are each formed at a position aligning with the memory hole 82 .
- the select transistor layer 90 includes a source side gate insulating layer 93 a , a source side columnar semiconductor layer 94 a , a drain side gate insulating layer 93 b , and a drain side columnar semiconductor layer 94 b , as shown in FIG. 27 .
- the source side columnar semiconductor layer 94 a functions as a body of the source side select transistor SSTr.
- the drain side columnar semiconductor layer 94 b functions as a body of the drain side select transistor SDTr.
- the source side gate insulating layer 93 a is formed with a certain thickness on aside surface of the source side hole 92 a .
- the source side columnar semiconductor layer 94 a is formed in a column shape to extend in the perpendicular direction with respect to the substrate 10 and to be in contact with a side surface of the source side gate insulating layer 93 a and one of upper surfaces of the pair of columnar portions 84 a .
- the source side gate insulating layer 93 a is configured by silicon oxide (SiO 2 ).
- the source side columnar semiconductor layer 94 a is configured by polysilicon (poly-Si).
- the source side columnar semiconductor layer 94 a has a lower portion 94 aa configured by an intrinsic semiconductor and an upper portion 94 ab configured by an N+ type semiconductor.
- the drain side gate insulating layer 93 b is formed with a certain thickness on a side surface of the drain side hole 92 b .
- the drain side columnar semiconductor layer 94 b is formed in a column shape to extend in the perpendicular direction with respect to the substrate 10 and to be in contact with a side surface of the drain side gate insulating layer 93 b and the other of the upper surfaces of the pair of columnar portions 84 a .
- the drain side gate insulating layer 93 b is configured by silicon oxide (SiO 2 ).
- the drain side columnar semiconductor layer 94 b is configured by polysilicon (poly-Si).
- the drain side columnar semiconductor layer 94 b has a lower portion 94 ba configured by an intrinsic semiconductor and an upper portion 94 bb configured by an N + type semiconductor.
- the diode layer 100 includes a source side ohmic contact layer 101 a , a source side N type semiconductor layer 102 a , a drain side ohmic contact layer 101 b , a drain side P type semiconductor layer 102 b , and a drain side N type semiconductor layer 103 b , as shown in FIG. 27 .
- the drain side P type semiconductor layer 102 b and drain side N type semiconductor layer 103 b function as the diode D 1 .
- the source side ohmic contact layer 101 a is formed in a column shape extending in the stacking direction from an upper surface of the source side columnar semiconductor layer 94 a .
- the source side N type semiconductor layer 102 a is formed in a column shape extending in the stacking direction from an upper surface of the source side ohmic contact layer 101 a .
- the source side N type semiconductor layer 102 a is configured by polysilicon including an N type impurity.
- the drain side ohmic contact layer 101 b is formed in a column shape extending in the stacking direction from an upper surface of the drain side columnar semiconductor layer 94 b .
- the drain side P type semiconductor layer 102 b is formed in a column shape extending in the stacking direction from an upper surface of the drain side ohmic contact layer 101 b .
- the drain side N type semiconductor layer 103 b is formed in a column shape extending in the stacking direction from an upper surface of the drain side P type semiconductor layer 102 b .
- the drain side P type semiconductor layer 102 b is configured by polysilicon including a P type impurity
- the drain side N type semiconductor layer 103 b is configured by polysilicon including an N type impurity.
- the wiring layer 110 includes a source layer 111 , a plug layer 112 , and a bit layer 113 .
- the source layer 111 functions as the source line SL.
- the bit layer 113 functions as the bit line BL.
- the source layer 111 is formed to extend in the row direction and to be in contact with an upper surface of the source side N type semiconductor layer 102 a .
- the bit layer 113 is formed to extend in the column direction and to be in contact with an upper surface of the drain side N type semiconductor layer 103 b via the plug layer 112 .
- the source layer 111 , the plug layer 112 , and the bit layer 113 are configured by a metal such as tungsten.
- the back gate layer 70 , memory transistor layer 80 , and select transistor layer 90 are formed. Now, an upper portion of the source side hole 92 a and an upper portion of the drain side hole 92 b are not filled but left as is.
- the source side ohmic contact layer 101 a is deposited on an upper portion of the source side columnar semiconductor layer 94 a in the source side hole 92 a .
- the drain side ohmic contact layer 101 b is deposited on an upper portion of the drain side columnar semiconductor layer 94 b in the drain side hole 92 b.
- a source side P type semiconductor layer 104 is deposited on an upper portion of the source side ohmic contact layer 101 a in the source side hole 92 a .
- the drain side P type semiconductor layer 102 b is deposited on an upper portion of the drain side ohmic contact layer 101 b in the drain side hole 92 b .
- the source side P type semiconductor layer 104 in the source side hole 92 a is removed.
- the source side N type semiconductor layer 102 a is deposited on the upper surface of the source side ohmic contact layer 101 a in the source side hole 92 a .
- the drain side N type semiconductor layer 103 b is deposited on an upper surface of the drain side P type semiconductor layer 102 b in the drain side hole 92 b .
- the source side N type semiconductor layer 102 a and drain side N type semiconductor layer 103 b are formed, for example, by depositing polysilicon and then implanting N+ ions in the polysilicon.
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Abstract
Description
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JP2020087495A (en) * | 2018-11-29 | 2020-06-04 | キオクシア株式会社 | Semiconductor memory |
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Also Published As
Publication number | Publication date |
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KR20120030923A (en) | 2012-03-29 |
US20120069660A1 (en) | 2012-03-22 |
US20130229876A1 (en) | 2013-09-05 |
US20140313829A1 (en) | 2014-10-23 |
US8659947B2 (en) | 2014-02-25 |
US20140085991A1 (en) | 2014-03-27 |
JP2012069606A (en) | 2012-04-05 |
US20160240261A1 (en) | 2016-08-18 |
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