KR20100082220A - Testing method of wafer - Google Patents

Abstract

PURPOSE: A method for testing a wafer is provided to reduce a time for testing a semiconductor device by effectively allocating channels and increasing the number of devices to be tested through one test. CONSTITUTION: A tester(110) implements a test for a chip by applying electrical signal to each chip of a wafer(100). A wafer is loaded on a chuck(114) which is installed on a probe station(112). A channel(120) transfers the electrical signal from the tester to a probe card(130). The probe card tests the wafer using the electrical signal. The probe card is connected with a tester head(134) through pogo pins(136) and is connected with a probe card holder(138).

Description

Testing Method of Wafer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor wafer, and more particularly, to a method for inspecting a semiconductor wafer that can increase productivity by shortening the inspection time.

After fabricating a semiconductor device on a wafer, an electrical test is performed to check for defects in the manufacturing process.

In general, electrical inspection uses a parallel inspection method to shorten the inspection time and increase productivity. However, even in the parallel test method, the number of channels that transmit electrical signals from the tester to the tester is inevitably finite. Testing with these limited channels limits the number of Die Under Tests (DUTs) that can be tested at one time.

The technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, by reducing the time to inspect the semiconductor device by increasing the number of devices to be tested at a time through efficient channel assignment. To provide a wafer inspection method that can be.

The wafer inspection method according to the present invention divides the plurality of channels into a first channel group for cell / core inspection and a second channel group for input / output inspection. The cell / core test is performed using the first channel group and the second channel group. Subsequently, an input / output test is performed using the second channel group.

In this case, the first channel group may allocate a number of channels smaller than the number of input / output terminals to each device under test.

The cell / core test may take a longer test time than the input / output test.

In addition, the number of parameters by the first channel group may be set larger than the number of all channels divided by the number of input / output terminals.

According to the embodiment, the number of channels is 1024, the input / output terminals are 32, the first channel group allocates 16 channels to each device under test, and the second channel group is assigned to each device under test. 32 channels are allocated, and the number of parameters by the first channel group may be set to 32 or more and 56 or less.

In particular, the number of parameters by the first channel group may be set to 48.

According to the wafer inspection method according to the present invention, a limited channel of the inspection apparatus can be used efficiently. That is, since the test is performed by allocating the channel in consideration of the difference in the test time according to the test type, the idle period during which the channel transmits no signal can be reduced. Accordingly, the productivity of the semiconductor device can be increased by shortening the inspection time of the entire wafer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

1 is a view showing an electrical inspection device of the wafer according to the embodiment.

Referring to FIG. 1, an electrical test apparatus for a wafer may include a tester 110, a channel 120, and a probe card 130.

The tester 110 may apply an electrical signal such as a voltage, a current, and a clock to an individual chip in the wafer 100 to inspect the chip. The channel 120 may receive various electrical signals from the tester 110 and transmit the various electrical signals to the probe card 130. The probe card 130 may receive electrical signals generated by the tester 110 through the channel 120 to perform electrical inspection of the semiconductor wafer. The probe card 130 may be connected to the tester head 134 by the pogo pin 136. In addition, the probe card 130 may be coupled to the probe card holder 138. Wafer 100 may be seated on chuck 114 installed on probe station 112. In addition, the wafer 100 may connect semiconductor needles formed on the wafer 100 with the needle 132 of the probe card as the probe station 112 moves.

2 is a diagram illustrating a layout of a probe card according to the embodiment.

Referring to FIG. 2, the probe card 130 may include first and second probe blocks 130a and 130b. The first probe block 130a may be aligned with the first channel group 120a. The second probe block 130b may be aligned with the second channel group 120b.

The probe card 130 may be connected to 40 channels in order to receive an electrical signal for inspecting the wafer from the tester. In this case, the limited number of 40 channels may be divided into cell / core inspection and input / output inspection. That is, the first channel group 120a for the cell / core test and the second channel group 120b for the input / output test may be divided. In all 40 channels, the first and second channel groups 120a and 120b may be configured as 20 channels, respectively.

The first probe block 130a may include two terminals for cell / core inspection. That is, each first probe block 130a may be allocated two channels from the first channel group 120a. Accordingly, the first channel group 120a may inspect ten inspected elements through one inspection.

The second probe block 130b may include four terminals for the input / output test. That is, each second probe block 130b may be allocated four channels from the second channel group 120b. Accordingly, the second channel group 120b may inspect five inspected devices through one inspection.

In this case, the number of inspected devices that can be inspected through a single electrical test may be defined as para.

3 illustrates a wafer and semiconductor devices formed on the wafer.

A method of inspecting 60 inspected devices 102 formed on the wafer 100 illustrated in FIG. 3 using the probe card 130 illustrated in FIG. 2 will be described below. In this case, each device under test 102 may be semiconductor devices having four input / output terminals 104.

The process of inspecting the wafer may include cell / core inspection and input / output inspection. The cell / core check may be a process of checking for defects of cells. This cell / core check may be performed by repeating a process of writing and reading different data into a neighboring cell for each cell. In addition, the input / output test may be a test for operating defects of semiconductor devices. The input / output test is for operation verification, and the time required for conducting the test may be shorter than the cell / core test.

As such, the inspection of the wafer through the cell / core inspection and the input / output inspection can be performed on all the inspected devices formed on the wafer.

For example, the electrical inspection of the wafer can be done by cell / core inspection followed by input / output inspection.

First, cell / core inspection may be performed using the first and second channel groups 120a and 120b. Allocating two channels to each device under test for cell / core inspection may be a minimum channel assignment. That is, cell / core checking can be performed even when two or more channels are allocated. Therefore, the cell / core inspection can also be performed through the second channel group 120b in which four channels are assigned to each device under test. Accordingly, the cell / core test may be performed on 15 devices under test by the first and second channel groups 120a and 120b through a single test. That is, as illustrated in FIG. 3, the 15 inspected elements including the 3 rows and 5 columns of blocks corresponding to the first and second probe blocks 130a and 130b of the probe card 130 may be inspected. have. In addition, by inspecting the blocks of the 15 devices under test four times, a cell / core test may be performed on all 60 devices under test.

Subsequently, an input / output test may be performed using the second channel group 120b. Since the input / output test is performed by the second channel group 120b as shown in FIG. 4, the number of para tested by one test may be five corresponding to the second probe block 130b. In this way, by inspecting the blocks of the five devices under test 12 times, input / output inspection of all 60 devices under test can be performed.

As described above, each test time may be different due to the characteristics of the cell / core test and the input / output test. In general, cell / core inspection can take five to seven times longer than input / output inspection. If the time required to perform the cell / core inspection and the input / output inspection once is 85s and 15s, respectively, the wafer inspection time according to the embodiment may be as follows.

The cell / core inspection time of the entire wafer can be expressed as the product of one cell / core inspection time and the number of inspections. In this case, since 15 inspected devices are inspected at a time, a total of 60 inspected devices can be inspected by 4 inspection processes. Therefore, the cell / core check time can be expressed as follows.

85s × 4 = 340s

That is, the total cell / core scan time may take 340 seconds.

In addition, since the I / O inspection examines five inspected devices at a time, a total of 60 inspected devices can be inspected in 12 inspection processes. Therefore, the input / output test time can be expressed as follows.

15s × 12 = 180s

That is, the total input / output test time may take 180 seconds.

Accordingly, the time required for the cell / core inspection and the input / output inspection of the entire device under test may be 520 seconds.

As described above, by dividing channels for cell / core inspection and input / output inspection and assigning different numbers of channels to each inspected device, the inspection time can be shortened.

Compared to the following case where the wafer is inspected by allocating the same channel to each device under test without distinguishing the channels, the following is described.

Since input / output test must be performed for each device under test, if 4 channels are allocated to all devices under test, there can be 10 devices under test. That is, the cell / core test and the input / output test are sequentially performed on the ten devices under test 102, and the test is repeated six times to complete the electrical tests on all six devices under test 102. Can be. In this case, one cell / core test and one input / output test can take 85s + 15s. That is, it may take 100 seconds to perform a cell / core test and an input / output test once, and 600 seconds to test a total of 60 devices under test.

Looking at the method for inspecting the wafer on which the DRAM device is formed as a wafer inspection method according to an embodiment of the present invention as follows.

In the case of NAND FLASH MEMORY, which is a relatively simple structure, the number of inspected devices that can be inspected at one time generally uses 256 para or 512 para, but a relatively complicated DRAM is 32 para or 64. Para can be used.

In the DRAM device described in this embodiment, a total of 32 input / output terminals are formed, and the minimum required number of terminals required for cell / core inspection is 16 devices. In addition, the total number of channels of the inspection apparatus may be set to 1024.

The 1024 total channels may be divided into first and second channel groups.

The first channel group may be a channel group for performing cell / core inspection. For this purpose, the first channel group may allocate 16 channels to each device under test.

The second channel group may be a channel group for performing an input / output test. For this purpose, the second channel group may allocate 32 channels for each device under test.

The number of channels in each of the first and second channel groups may vary. That is, the number of channels of each of the first and second channel groups may be determined by setting the number of para of each channel group.

In this case, it is preferable that the first channel group inspects 32 or more devices under test in one shot. This is because separating the first channel group allocating 16 channels can increase the number of elements to be inspected at one time. Since the cell / core test takes longer than the I / O test, the total test time can be reduced by increasing the number of parameters of the first channel group.

The number of channels of the second channel group may be set according to the number of first channel groups.

Looking at the relationship between the number of para of the first channel group and the number of para of the second channel group can be as follows.

When the number of parameters that can be checked at one time with the first channel group is N1, the total number of channels of the first channel group may be as shown in [Equation 1].

16 x N1

Since the total number of channels is 1024, the total number of channels of the second channel group may be expressed by Equation 2.

1024- (16 × N1)

Here, since the second channel group allocates 32 channels to each device under test, N2, which is a para number that can be inspected at once by the second channel group, may be expressed by Equation 3 below.

{1024- (16 × N1)} / 32 = 32- (1/2) × N1

In addition, since the para number that can be checked in the second channel group is a positive integer, N1 may be set to a multiple of 2 which is 62 or less. That is, the number of params that can be checked at one time by the first channel group may be 32 or more and even number 62 or less.

For example, if the number of params that can be checked at one time by the first channel group is 32, the total number of channels of the first channel group may be 16 × 32 = 512 according to [Equation 1]. Accordingly, the total number of channels of the second channel group may be 1024-512 = 512 according to Equation 2. In addition, the number of params that can be examined at one time by the second channel group may be 32− (1/2) × 32 = 16 according to Equation (3).

Based on the above relationship, the results of the number of inspected elements that can be inspected at once in the second channel group and the wafer electrical inspection time according to the number of inspected elements at the same time in the first channel group will be described. It may be as shown in [Table 1] below. Here, the number of shots may be defined as the number of times electrical inspection is performed to inspect the entire wafer.

Para can Shots Inspection time First channel group Second channel group First channel group Second channel group First channel group Second channel group Total time 58 3 34 583 5032 3498 8530 56 4 34 436 5032 2616 7648 54 5 36 361 5328 2166 7494 52 6 36 298 5328 1788 7116 50 7 36 258 5328 1548 6876 48 8 36 225 5328 1350 6678 46 9 38 202 5624 1212 6836 44 10 39 184 5772 1104 6876 42 11 41 173 6068 1038 7106 40 12 41 154 6068 924 6992 38 13 41 149 6068 894 6962 36 14 41 133 6068 798 6866 34 15 42 126 6216 756 6972 32 16 42 117 6216 702 6918

In general, when all 32 devices are assigned the same number of channels, wafer inspection can be performed with 32 para numbers. In this case, the number of shots for inspecting the entire wafer is 61 times, and the total wafer inspection time may be 8052 seconds.

As shown in Table 1 above, when the number of paras in the first channel group is 32 or more and 56 or less, it can be seen that the overall wafer inspection time is shorter than the conventional method.

In particular, when the number of paras in the first channel group is 48, the total wafer inspection time is 6678 seconds, which is about 20% shorter than that of the conventional method.

In the above-described embodiment, a method of inspecting a wafer of a DRAM semiconductor device in which 32 input / output terminals are formed by using an inspection apparatus having 1024 channels has been described. There may be various kinds of semiconductor wafers depending on the type of semiconductor elements formed. In addition, the channel of the wafer inspection apparatus may be different for each inspection apparatus. Accordingly, the example shown in [Table 1] may vary.

The embodiment of the present invention can shorten the total inspection time by dividing a limited channel to increase the number of paras for the cell / core inspection that takes a long time.

As described above, the selection of the number of para for the channel groups can obtain an optimal combination by calculating the test time according to the number of para of each channel group.

In addition, the para number of these channel groups may be found in the condition range of the equation by extending the above equations.

That is, when the para number of the first channel group is determined to be unknown, the para number of the second channel group may be set by Equation 1 or an application thereto. In addition, the total number of channels and the time required for one-time cell / core inspection and input / output inspection are known to the operator and can be treated as constants in the equation. Here, since the number of shots can be defined according to the number of parameters for each channel group, the product of the number of shots and the test time between channel groups has a value smaller than the test time when the conventional channel is not divided. You will be able to build Therefore, the inequalities can be summarized to calculate the range of para numbers of the first and second channel groups.

The present invention is not limited to the above-described embodiments and can be modified in various other forms within the spirit of the present invention.

1 is a view showing a wafer inspection apparatus.

2 shows a probe card according to an embodiment of the invention.

3 and 4 are layout views showing some of the devices under test on the wafer.

DESCRIPTION OF REFERENCE NUMERALS

110: tester 120: channel

100: wafer 130: probe card

132: needle 102: device to be inspected

Claims (6)

Dividing the plurality of channels for applying electrical signals for wafer inspection from the tester into a first channel group for cell / core inspection and a second channel group for input / output inspection, Align the first channel group with a first probe block of a probe card for performing a cell / core test, Align the second channel group with a second probe block of a probe card for performing an input / output test, Perform a cell / core test using the first channel group and the second channel group, And an input / output test using the second channel group. The method of claim 1, And the first channel group allocates a number of channels smaller than the number of input / output terminals to each device under test. The method of claim 1, Wherein the cell / core test performs a functional test of the devices under test and the input / output test performs an operation test of the devices under test. The method of claim 1, The sum of all probe blocks of the first probe block and the second probe blocks is set to be larger than the number of probe blocks obtained by dividing the number of channels by the number of input / output terminals. The method of claim 1, The number of channels is 1024, the input / output terminals are 32, the first channel group allocates 16 channels to each device under test, and the second channel group is assigned to each device under test. 32 channels are allocated, and the number of parameters by the first channel group is set to 32 or more and 56 or less. The method of claim 5, And the number of parameters by the first channel group is set to 48.

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