KR20100079769A - Integrated circuit - Google Patents

Abstract

The present invention relates to a technique for controlling the toggling of a clock signal, and an object of the present invention is to provide an integrated circuit capable of controlling the clock signal to be toggled only during a specific period. According to an aspect of the present invention, a clock control signal generation unit for generating a clock control signal activated by receiving an internal column signal activated upon application of a command and receiving a precharge signal, and receiving the first clock signal as an input; An integrated circuit including a clock control unit for outputting a second clock signal that toggles during an activation period of a clock control signal is provided.

Description

Integrated Circuits {INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and more particularly, to a technique for controlling toggling of a clock signal.

Semiconductor devices, integrated circuits, and the like have been continuously improved for the purpose of improving the operation speed with the increase in the degree of integration. Such semiconductor devices and integrated circuits operate in synchronization with a reference periodic pulse signal, such as a clock, to improve the operation speed and to efficiently operate the internal device. In general, semiconductor devices and integrated circuits are largely composed of a combinational circuit (Combinational logic) and a sequential logic (Sequential logic), in particular sequential logic (clock) that pulses at a predetermined frequency in order to proceed with each step Clock is required. Therefore, most semiconductor devices and integrated circuits operate through an externally supplied clock or an internal clock generated as needed.

1 is a block diagram of an integrated circuit of the prior art.

Referring to FIG. 1, the clock controller 110 outputs an output clock ICLK in which the input clock CLKB is delayed for a predetermined time and the phase is inverted. The conventional clock control unit 110 controls and outputs only the delay time and the phase of the input clock CLKB, and does not control the toggling. Therefore, there is a disadvantage in that current consumption due to toggling of the output clock ICLK is large.

The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide an integrated circuit which can control the clock signal to be toggled only during a specific period.

According to an aspect of the present invention for achieving the above technical problem, a clock control signal generation unit for generating a clock control signal that is activated by receiving an internal column signal that is activated when a command is applied and receives a precharge signal; And a clock control unit configured to output a second clock signal toggling during the activation period of the clock control signal by receiving the first clock signal as an input.

The integrated circuit to which the present invention is applied can control the clock signal to be toggled only during a read operation or a write operation period, thereby reducing current consumption due to toggling of the clock signal CLK.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

In general, the logic signal of the circuit is divided into a high level (HIGH LEVEL, H) or a low level (LOW LEVEL, L) corresponding to the voltage level, and may be expressed as '1' and '0', respectively. In addition, it is defined and described that it may additionally have a high impedance (Hi-Z) state and the like. In addition, PMOS (P-channel Metal Oxide Semiconductor) and N-channel Metal Oxide Semiconductor (NMOS), which are terms used in the present embodiment, are known to be a type of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). In addition, the clock signal CLOCK is a periodic pulse signal that toggles at a constant cycle. In general, the clock signal is used to determine the activation time of an internal circuit or an internal signal based on a rising edge or a falling edge. The clock signal is applied in a differential form between a positive clock signal and a subclock signal. Also used. Toggling of the clock signal is also referred to as transition.

2 is a configuration diagram of an integrated circuit according to a first embodiment of the present invention.

Referring to FIG. 2, the integrated circuit generates a clock control signal generator for generating a clock control signal CLK_CTRL which is activated by receiving an internal column signal CASP6 activated when a command is applied and deactivated by receiving a precharge signal PCGALL. 20 and a clock control unit 30 for outputting a second clock signal ICLK that toggles during the activation period of the clock control signal CLK_CTRL as the first clock signal ICLKB.

The command may include a column series read command, a write command, and the like, and is a command for accessing a column COLUMN area of an integrated circuit. For reference, a row series command includes an active command and the like to access a row area of an integrated circuit. The column area and the row area divide the memory area for storing data in the integrated circuit into rows and columns.

Looking at the detailed configuration and the main operation of the integrated circuit configured as described above are as follows.

The clock control signal generator 20 includes an RS latch unit 21 that receives a reset signal RESET corresponding to the internal column signal CASP6 and a set signal SET corresponding to the precharge signal PCGALL. do. The reset signal RESET is a signal inverting the internal column signal CASP6, and the set signal SET is a signal inverting the precharge signal PCGALL. In addition, the RS latch unit 21 includes a first negative logical means NAND1 for inputting a reset signal RESET and an output signal of the second negative logical means NAND2, the set signal SET, and the first signal. It consists of the 2nd negative logical means NAND2 which inputs the output signal of the negative logical means NAND1. For reference, as shown in the present embodiment, an output inverter INV2 for inverting the signal output from the RS latch unit 21 may be further included.

The clock control unit 30 includes an inverter INV4 for inputting the clock control signal CLK_CTRL, a negative logic unit NAND3 for inputting an output signal of the first clock signal ICLKB and the inverter INV4, It consists of a delay unit 31 for delaying the signal output from the negative logical means NAND3 for a predetermined time. The delay unit 31 is composed of a plurality of inverters INV5 and INV6 connected in series with each other.

Meanwhile, in the present embodiment, the internal column signal CASP6 is a signal that is activated at a high level during read and write operations, and the precharge signal PCGALL is a signal that is activated at a high level during precharge operations.

The clock control signal generation unit 20 activates and outputs the clock control signal CLK_CTRL to a low level when the internal column signal CASP6 is activated in the normal operation mode, and outputs the clock control signal when the precharge signal PCGALL is activated. CLK_CTRL) is deactivated to high level and output. Here, the clock controller 30 outputs a clock signal ICLK that is toggled only when the clock control signal CLK_CTRL is activated. That is, since the integrated circuit provides a clock signal that is toggled only when the read and write operations are performed, current consumption due to the clock signal toggling may be minimized.

3 is a configuration diagram of an integrated circuit according to a second embodiment of the present invention.

Referring to FIG. 3, the integrated circuit generates a clock control signal CLK_CTRL that is activated by receiving an internal column signal CASP6 activated when a command is applied and deactivated by receiving a power-up signal PWRUP and a precharge signal PCGALL. A clock control unit 50 for inputting a clock control signal generation unit 40 and a first clock signal ICLKB to output a second clock signal ICLK that toggles during the activation period of the clock control signal CLK_CTRL. ).

Looking at the detailed configuration and the main operation of the integrated circuit configured as described above are as follows.

The clock control signal generator 40 is connected to a set signal generator 42 for generating a set signal SET corresponding to the precharge signal PCGALL and the power-up signal PWRUP, and an internal column signal CASP6. The RS latch unit 41 receives a corresponding reset signal RESET and a set signal SET corresponding to an output signal of the set signal generator 42. Here, the set signal generation unit 42 inputs the inverter INV3 for inverting the power-up signal PWRUP and the negative logic means NOR for inputting the precharge signal PCGALL and the output signals of the inverter INV3. It is composed of In addition, the RS latch unit 41 includes a first negative logical unit NAND1 for inputting a reset signal RESET inverting the internal column signal CASP6 and an output signal of the second negative logical unit NAND2. And a second negative logical means NAND2 for inputting the output signal of the set signal generator 42 and the output signal of the first negative logical means NAND1. For reference, as shown in the present exemplary embodiment, an output inverter INV2 for inverting a signal output from the RS latch unit 41 may be further included. In this embodiment, the reset signal RESET is a signal inverting the internal column signal CASP6, and the set signal SET uses the output signal of the set signal generator 42.

The clock controller 50 includes an inverter INV4 for inputting the clock control signal CLK_CTRL, a negative logic unit NAND3 for inputting an output signal of the first clock signal ICLKB and the inverter INV4, and And a delay unit 51 for delaying the signal output from the negative logical means NAND3 for a predetermined time. The delay unit 51 is composed of a plurality of inverters INV5 and INV6 connected in series with each other.

On the other hand, in the present embodiment, the power-up signal PWRUP is at a low level before the power is stabilized, that is, at initialization. The internal column signal CASP6 is a signal that is activated at a high level during read and write operations, and the precharge signal PCGALL is a signal that is activated at a high level during precharge operations.

The clock control signal generator 40 deactivates and outputs the clock control signal CLK_CTRL to a high level when the power-up signal PWRUP is at a low level, that is, during an initialization operation. In addition, in the normal operation mode after the initialization operation is completed, when the internal column signal CASP6 is activated, the clock control signal CLK_CTRL is activated at a low level, and when the precharge signal PCGALL is activated, the clock control signal CLK_CTRL is activated. ) To high level and output. Here, the clock controller 50 outputs a clock signal ICLK that is toggled only when the clock control signal CLK_CTRL is activated. That is, since the integrated circuit provides a clock signal that is toggled only when the read and write operations are performed, current consumption due to the clock signal toggling can be minimized.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the configuration of an active high or an active low to indicate an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. In addition, the configuration of the logic gate may be changed as necessary to implement the same function. That is, the negative logical means, the negative logical sum means, etc. may be configured through various combinations such as NAND GATE, NOR GATE, and INVERTER. In particular, in the present embodiment, the RS latch unit and the clock control unit use negative logical means, but may be configured using negative logical sum means. In general, the negative logic means is configured by using a NOR gate. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a block diagram of an integrated circuit of the prior art.

2 is a configuration diagram of an integrated circuit according to a first embodiment of the present invention.

3 is a configuration diagram of an integrated circuit according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20, 40: clock control signal generator

30, 50: clock control unit

21, 41: RS latch

42: set signal generator

31, 51: delay unit

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (11)

A clock control signal generator for generating a clock control signal activated by receiving an internal column signal activated when a command is applied and deactivated by receiving a precharge signal; And A clock control unit configured to output a second clock signal toggling during the activation period of the clock control signal by receiving the first clock signal as an input; Integrated circuit comprising a. The method of claim 1, And the command includes a column series read command and a write command. The method of claim 1, The clock control signal generator, And an RS latch unit configured to receive a reset signal corresponding to the internal column signal and a set signal corresponding to the precharge signal. The method of claim 3, The clock control signal generator, And an output inverter for inverting the signal output from the RS latch unit. The method of claim 3, And the reset signal is a signal inverting the internal column signal, and the set signal is a signal inverting the precharge signal. The method of claim 3, The clock control signal generator, And a set signal generator configured to generate the set signal corresponding to the precharge signal and the power up signal. The method of claim 6, The set signal generator, An inverter for inverting the power-up signal; And And negative logic sum means for inputting the precharge signal and the output signal of the inverter. The method of claim 7, wherein And the reset signal is a signal obtained by inverting the internal column signal. The method according to any one of claims 3 to 8, The RS latch unit, First negative logical means for inputting the reset signal and an output signal of the second negative logical means; And And said second negative logical means for inputting said set signal and said output signal of said first negative logical product. The method of claim 1, The clock control unit, An inverter configured to receive the clock control signal; Negative logic means for inputting the first clock signal and the output signal of the inverter; And And a delay unit for delaying a signal output from the negative logical means for a predetermined time. The method of claim 10, The delay unit includes a plurality of inverters connected in series with each other.

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