KR20100079740A - Semiconductor device and method for manufacturing the device - Google Patents

Semiconductor device and method for manufacturing the device Download PDF

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Publication number
KR20100079740A
KR20100079740A KR1020080138295A KR20080138295A KR20100079740A KR 20100079740 A KR20100079740 A KR 20100079740A KR 1020080138295 A KR1020080138295 A KR 1020080138295A KR 20080138295 A KR20080138295 A KR 20080138295A KR 20100079740 A KR20100079740 A KR 20100079740A
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KR
South Korea
Prior art keywords
region
collector
ions
base
base region
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KR1020080138295A
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Korean (ko)
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신희재
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주식회사 동부하이텍
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Priority to KR1020080138295A priority Critical patent/KR20100079740A/en
Publication of KR20100079740A publication Critical patent/KR20100079740A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to increase base transport efficiency by reducing the density of fluorine ions inside silicon. CONSTITUTION: A metal layer is respectively formed on an emitter region, a collector region, and a base region. A device isolation layer(40) defines an active region on an epitaxial layer formed on the semiconductor substrate. A base region(50) is formed on the active region by implanting fluorine ions and p type impurities. An emitter region and a collector region are formed on the side of the base region by implanting N type impurity ions. The fluorine ions are implanted with the density of 5E14ions/cm^2 to 6E16 ions/cm^2. An N type sub collector(20) is formed on the surface of the semiconductor substrate.

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device such as a bipolar transistor and a method for manufacturing the same.

In general, a PN junction formed by contacting a P-type semiconductor and an N-type semiconductor region in a semiconductor substrate has rectifying characteristics and is the most basic component of a semiconductor device. The bipolar junction transistor (BJT: bipolar transistor) is a bipolar junction transistor composed of two layers. A forward bias is applied to one side of the bipolar transistor with a PN junction and a reverse bias is applied to a PN junction on the other side to induce the movement of electrons and holes.

In the fabrication of NPN bipolar transistors, Boron diffusion of base is a very important problem. Since boron is easily transition enhanced diffusion due to defects caused by ion implantation, diffusivity of the transistor is greatly increased. This phenomenon has a problem of increasing the base width to deteriorate the characteristics of the bipolar transistor and making it difficult to maintain a narrow base width as the device is directly fabricated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device such as an NPN biplane transistor capable of keeping the base width narrow or suppressing the expansion of the base width.

Another object of the present invention is to provide a method of manufacturing a semiconductor device for manufacturing the bipolar transistor.

According to an aspect of the present invention, there is provided a semiconductor device including a device isolation layer formed by defining an active region in an epitaxial layer formed on a semiconductor substrate, and a base formed in the active region by ion implantation of fluorine ions and P-type impurities. It is preferable to comprise an emitter region and a collector region formed on the side of the base region by implanting a region and N-type impurity ions.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an isolation layer defining an active region in an epitaxial layer formed on a semiconductor substrate; Forming a first photoresist mask that selectively opens a portion where a base region is to be formed, and implanting fluorine ions and P-type impurities by using the first photoresist mask as an ion implantation mask to form the active region Forming a base region on the substrate, removing the first photoresist mask, and selectively opening a portion where the emitter region and the collector region are to be formed on the epi layer, including the base region Forming a photoresist film mask and using the second photoresist film mask as an ion implantation mask, It is injected by the injection in a part of the base region to form the emitter region comprising a step of forming the collector region by implanting the epitaxial layer.

The semiconductor device and the manufacturing method thereof according to the present invention

When forming the base, a high concentration of fluorine ions are implanted together with the P-type impurity ions, thereby reducing the base width by reducing the boron diffusion of the base region in ion implantation annealing or subsequent heat treatment processes. It is possible to easily adjust the base width of the NPN bipolar transistor, such as keeping it narrow and suppressing the expansion of the base width even when the device density increases.

Fluorine ions have the effect of increasing the base transport efficiency by reducing the concentration of defects present in the silicon.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to the semiconductor device having the structure of the bipolar transistor illustrated in FIG. 1, an N-type sub collector 20 is formed on the surface of the P-type silicon (Si) substrate 10.

In addition, an epitaxial layer 30 is formed on the semiconductor substrate 10 including the N-type sub-collector 20. The device isolation layer 40 defines an active region in the epi layer 30 and is formed in the epi layer 30.

In addition, the base region 50 is formed in the active region between the device isolation layers 40 by ion implantation of fluorine ions and P-type impurities. The concentration of the fluoride ion used to form the base region 50 may be a 5E14ions / ㎝ 2 to about 6E16 ions / ㎝ 2.

The collector region 60 and the emitter region 62 are formed on the side of the base region 72 by N-type impurity ion implantation, respectively.

Metal layers 72, 74, and 70 are formed in base region (B) 50, collector region (C) 60, and emitter region (E) 62, respectively.

The semiconductor device according to the present invention described above may correspond to an NPM bipolar transistor.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2E show cross-sectional views of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a sub-collector 20 is formed by implanting a high concentration of N-type impurities into the surface of the semiconductor substrate 10. For example, a photoresist mask (not shown) is formed on the semiconductor substrate 10 to expose a portion where the N-type sub collector 20 is to be formed and cover another portion. Using a photoresist mask as an ion implantation mask, a high concentration of N-type impurities may be implanted into the semiconductor substrate 10 to form an N-type sub-collector 20 as shown in FIG. 2A. Thereafter, the photoresist mask is removed by an ashing process.

Thereafter, as shown in FIG. 2B, a silicon epitaxial layer 30 is formed on the entire upper surface of the semiconductor substrate 10 including the N-type sub-collector 20. The N-type epitaxy layer 30 epitaxially exposes the silicon surface of the semiconductor substrate 10 exposed to the side of the N-type sub-collector 20 on top of the silicon semiconductor substrate 10 shown in FIG. 2A. It can be formed by growing (epitaxial).

Thereafter, as shown in FIG. 2C, an isolation layer 40 defining an active region is formed in the epi layer 30. The device isolation layer 40 may be formed by a general shallow trench isolation (STI) process or may be formed by a LOCOS process. These processes are general and will not be described here.

Thereafter, as illustrated in FIG. 2D, the upper region of the epi layer 30 on which the base region 50 is to be formed is selectively opened on the epi layer 30 including the device isolation layer 40, and the remaining epi layer is selectively opened. A photoresist mask 54 is formed to cover the upper region of 30. In this manner, the photoresist mask 54 selectively opens the epi layer 30. Thereafter, using the photoresist mask 54 as an ion implantation mask, fluorine ions and P-type impurity ions are implanted 52 to form a base region 50 in the active region. For example, Boron may be used as the P-type impurity ion.

According to the invention, fluorine ions can be implanted at a concentration of 5E14ions / cm 2 to 6E16 ions / cm 2 . In addition, the implantation energy of fluorine ions and P-type impurities may be determined so that the center depth of the base region 50 is slightly smaller than the maximum peak value of the ion implanted layer. For example, the fluoride ion and the P-type impurity may be implanted with an ion implantation energy of 5 keV to 15 keV, preferably 10 keV or less.

Thereafter, the photoresist mask 54 shown in FIG. 2D is removed by an ashing process.

Thereafter, as illustrated in FIG. 2E, the photoresist mask 66 is formed on the epi layer 30 including the base region 50. Here, the photoresist mask 66 opens a part of the base area 50 in which the emitter area is to be formed, selectively opens a part of the epi layer 30 in which the collector area is to be formed, and covers the remaining part.

Thereafter, using the photoresist mask 66 as an ion implantation mask, as shown in FIG. 2E, N-type impurity ions are implanted 64 into a portion of the base region 50 to emit an emitter on the side of the base region 50. Area 62 is formed. At the same time, using the photoresist mask 66 as an ion implantation mask, as shown in FIG. 2E, N-type impurity ions are implanted 64 into a part of the epi layer 30 to collect on the side of the base region 50. Area 60 is formed. For example, as an N-type impurity ion, phosphorus (Phosporous) or asic (As) may be used. Here, the N-type impurity ions may be implanted with less than 10 keV, and the injected amount may be 1E14ions / cm 2 to 1E16ions / cm 2 .

Thereafter, after the emitter region 62 and the collector region 60 shown in FIG. 2E are formed, the photoresist mask 66 is removed by an ashing process.

Subsequently, as shown in FIG. 1, metal layers 70, 74, and 72 are formed on the emitter region 62, the collector region 60, and the base region 50, respectively.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

2A to 2E show cross-sectional views of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10 semiconductor substrate 20 sub-collector

30: epilayer 40: device isolation film

50: base area 54, 66: photoresist mask

60: collector region 62: emitter region

70, 72, 74: metal layer

Claims (8)

A device isolation layer formed by defining an active region in an epitaxial layer formed on the semiconductor substrate; A base region formed in the active region by ion implantation of fluorine ions and P-type impurities; And And an emitter region and a collector region formed on the side of the base region by implanting N-type impurity ions. The semiconductor device according to claim 1, wherein the fluorine ions are implanted at a concentration of 5E14ions / cm 2 to 6E16 ions / cm 2 . The method of claim 1, wherein the semiconductor device An N-type sub collector formed on the surface of the semiconductor substrate; And And a metal layer formed in the emitter region, the collector region, and the base region, respectively. Forming an isolation layer defining an active region in an epitaxial layer formed on the semiconductor substrate; Forming a first photoresist mask to selectively open a portion where a base region is to be formed on the epi layer including the device isolation layer; Forming the base region in the active region by ion implanting fluorine ions and P-type impurities using the first photoresist mask as an ion implantation mask; Removing the first photoresist mask; Forming a second photoresist mask on the epi layer including the base region to selectively open a portion where an emitter region and a collector region are to be formed; And Using the second photoresist mask as an ion implantation mask, implanting N-type impurity ions into a portion of the base region to form the emitter region and implanting the epitaxial layer to form the collector region The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 4, wherein said fluorine ion is method of producing a semiconductor device characterized in that the injection at a concentration of 5E14ions / ㎝ 2 to about 6E16 ions / ㎝ 2. The method of claim 4, wherein the implantation energy of the fluorine ions is determined according to a depth of the base region. The method of claim 6, wherein the fluoride ions are implanted with an ion implantation energy of about 5 keV to about 15 keV. The method of claim 4, wherein the semiconductor device is manufactured. Forming an N-type sub collector on a surface of the semiconductor substrate; After forming the emitter region and the collector region, removing the second photoresist mask; And And forming metal layers in the emitter region, the collector region, and the base region, respectively.
KR1020080138295A 2008-12-31 2008-12-31 Semiconductor device and method for manufacturing the device KR20100079740A (en)

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KR1020080138295A KR20100079740A (en) 2008-12-31 2008-12-31 Semiconductor device and method for manufacturing the device

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