KR20100079297A - A metal line of semiconductor device and method of manufacturing the same - Google Patents

A metal line of semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20100079297A
KR20100079297A KR1020080137727A KR20080137727A KR20100079297A KR 20100079297 A KR20100079297 A KR 20100079297A KR 1020080137727 A KR1020080137727 A KR 1020080137727A KR 20080137727 A KR20080137727 A KR 20080137727A KR 20100079297 A KR20100079297 A KR 20100079297A
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KR
South Korea
Prior art keywords
interlayer insulating
insulating layer
via hole
layer
forming
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Application number
KR1020080137727A
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Korean (ko)
Inventor
백인철
Original Assignee
주식회사 동부하이텍
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Priority to KR1020080137727A priority Critical patent/KR20100079297A/en
Publication of KR20100079297A publication Critical patent/KR20100079297A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A metal line of a semiconductor device and a method of manufacturing thereof are provided to improve the reliability of the device by making the bottom of a via hole round when forming a dual damascene structure. CONSTITUTION: A first stop layer(220), a second interlayer dielectric layer(225), a second stop layer(230), and a third interlayer dielectric layer(235) are laminated on the first interlayer dielectric layer(210) in which a metal line is formed. The third interlayer dielectric layer and the second stop layer are successively etched to form a via hole exposing the first stop layer to the outside. The exposed first stop layer from the bottom of the via hole is wet-etched to form a first undercut in the first stop layer. The third interlayer dielectric layer around the via hole is etched to form a trench.

Description

A metal line of semiconductor device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a metal wiring and a method of forming the semiconductor device having a dual damascene structure.

Aluminum, tungsten, copper, and the like are used as metal materials used to electrically connect devices and devices or wires and wires in the manufacture of semiconductor devices.

Aluminum and tungsten have a low melting point and a high resistivity, while copper has a relatively high melting point and low resistivity compared to aluminum and tungsten, so copper wiring has emerged for high integration and high performance of semiconductor devices.

However, due to the problem that copper is hardly etched by general etching materials, the damascene method is mainly used by etching the interlayer insulating film first, then depositing copper and filling it, and then performing a planarization process to form wiring. have.

1A to 1D are cross-sectional views illustrating a method for forming a copper wiring by a general damascene process.

First, as shown in FIG. 1A, a copper wiring 120 is formed in a first interlayer insulating layer 110, for example, an intermetal dielectric (IMD) layer, formed on a semiconductor substrate (not shown).

Subsequently, an etch stop layer 130 and a second interlayer insulating layer 140 are sequentially formed on the first interlayer insulating layer 110 on which the copper wiring 120 is formed. The second interlayer insulating layer 140 is etched until a portion of the etch stop layer is exposed by performing a photo and etching process to form a via hole 142 corresponding to the copper interconnection 120.

Next, as shown in FIG. 1B, the sacrificial layer 145 is filled in the via hole 142.

Next, as shown in FIG. 1C, the sacrificial layer 145 and the surrounding second interlayer insulating layer are formed to form a trench on the second interlayer insulating layer 140 by performing a photolithography process. The exposed photoresist pattern 150 is formed.

Next, as shown in FIG. 1D, the exposed sacrificial layer 145 and the surrounding second interlayer insulating layer 140 are etched using the photoresist pattern 150 as a mask to form the second interlayer insulating layer 140. A trench 162 having a dual damascene structure is formed within the trench. However, in the case of forming the dual damascene structure in this manner, the edge portion of the lower portion of the trench becomes thin when the copper barrier metal is deposited, and copper can penetrate into the interlayer insulating layer by a subsequent thermal process, thereby deteriorating the reliability of the device. Can be.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a metal wiring and a method for forming the semiconductor device, which may improve the reliability of the device by rounding the shape of the via hole bottom when forming the dual damascene structure.

According to an embodiment of the present disclosure, a metal wiring forming method of a semiconductor device may include a first stop layer, a second interlayer insulating layer, and a third interlayer insulating layer on a first interlayer insulating layer on which metal wirings are formed. Sequentially forming the layers, sequentially etching the third interlayer insulating layer and the second interlayer insulating layer to form a via hole exposing the first stop layer, and the first stop exposed at the bottom of the via hole. Wet etching the film to form a first undercut in the first stop film, and etching a third interlayer insulating layer around the via hole to form a trench.

The metal line forming method of the semiconductor device may include forming a second stop layer between the second interlayer insulating layer and the third interlayer insulating layer, and etching the second stop layer when the via hole is formed to form the second stop layer. Exposing the sidewalls. In the method of forming a metal wire of the semiconductor device, when the first undercut is formed in the first stop layer, the second stop layer exposed to the sidewall of the via hole is wet-etched to form a second undercut in the second stop layer. It may further comprise a step.

The forming of the trench may form a trench that exposes the second stop layer on which the second undercut is formed by etching the third interlayer insulating layer around the via hole.

The metal wiring of the semiconductor device according to the embodiment of the present invention for achieving the above object is a first interlayer insulating layer, a first stop film, a second stop layer laminated on the first interlayer insulating layer, the first metal wiring is formed Vias formed through the third interlayer insulating layer, the second stop layer, and the second interlayer insulating layer to expose the interlayer insulating layer, the second stop layer, and the third interlayer insulating layer, and the first stop layer. A hole, a first under cut formed in the first stop film exposed to the bottom of the via hole, a trench formed in a third interlayer insulating layer around the via hole, and a trench and a buried in the via hole in which the first under cut is formed. And a second metal wiring to be formed. The first under cut may have a round shape.

The metallization of the semiconductor device and the method of forming the semiconductor device according to the embodiment of the present invention are formed in the edge portion of the bottom portion of the via hole in a process of forming a barrier metal in the via hole, which is subsequently processed by rounding the bottom portion of the via hole of the dual damascene structure. There is an effect of improving the reliability of the device by suppressing the phenomenon that the barrier metal to be formed is thinned.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2A to 2G are process diagrams illustrating a metal wiring forming method according to an embodiment of the present invention.

First, as shown in FIG. 2A, a first interlayer insulating layer 210 is formed on a semiconductor substrate (not shown). The first interlayer insulating layer 210 may be TEOS (Tetra Ethyl Ortho Silicate) or USG (Undoped Silcate Glass). In addition, a copper metal wiring 215 is formed in the first interlayer insulating layer 210.

The first stop layer 220, the second interlayer insulating layer 225, the second stop layer 230, and the third interlayer insulating layer on the first interlayer insulating layer 210 on which the copper metal wires 215 are formed. (235) are formed sequentially.

The first stop layer 220 and the second stop layer 230 may be formed of a material having a high etching selectivity in relation to the second interlayer insulating layer 225 and the third interlayer insulating layer 235. For example, the first stop layer 220 and the second stop layer 230 may be nitride layers such as SiN.

Subsequently, a first photoresist pattern 240 is formed on the third interlayer insulating layer 235 by performing a photolithography process.

Next, as shown in FIG. 2B, the third interlayer insulating layer 235, the second stop layer 230, and the second interlayer insulating layer using the first photoresist pattern 240 as a mask. 225 is sequentially etched to form a via hole 242. The first photoresist pattern 240 is removed by an ashing or stripping process.

For example, using the first photoresist pattern 240 as an etch mask, the third interlayer insulating layer 235, the second stop layer 230, and the first interlayer insulating layer 220 are exposed until the first stop layer 220 is exposed. The second interlayer insulating layer 225 may be subjected to dry etching, for example, reactive ion etching (RIE).

By the reactive ion etching, a portion of the second stop layer 230 is exposed on the sidewall of the via hole 242, and a portion of the first stop layer 220 is exposed on the bottom of the via hole 242. .

Next, as shown in FIG. 2C, a portion of the second stop layer 230 exposed to the sidewall of the via hole 242 and the first stop layer 220 exposed to the bottom of the via hole 242. Is partially etched by using a phosphate-based chemical to form a first undercut 254 in the first stop layer 220 and a second undercut 252 in the second stop layer 252. To form. At this time, the copper wiring 215 under the first stop layer 220 is not exposed. The first under cut 254 and the second under cut 252 may have a round shape.

Next, as shown in FIG. 2D, the sacrificial layer 260 is gap-filled in the via hole 242 in which the first under cut 254 and the second under cut 252 are formed. Here, the sacrificial layer 260 is formed to protect the inside of the via hole 242 from the trench etching in the trench formation process. The sacrificial layer 260 may be a novolac gapfill material.

A second photoresist pattern 265 is formed on the third interlayer insulating layer 235 to expose the sacrificial layer 260 and the third interlayer insulating layer 235 around the sacrificial layer 260.

Next, as shown in FIG. 2E, the trench 265 is etched by etching the sacrificial layer 260 and the third interlayer insulating layer 235 around the sacrificial layer 260 using the second photoresist pattern 265 as a mask. Form. For example, through the etching process for forming the trench 265, the sacrificial layer 260 gap-filled in the via hole is removed, and the second stop layer 272 and the second undercut 252 are formed. The first stop layer 220 in which the first under cut is formed may be exposed. In addition, a portion 276 of the second interlayer insulating layer between the first under cut 254 and the second under cut 252 may be exposed in a lateral direction. The second photoresist pattern 265 is removed through an ashing process.

Next, as shown in FIG. 2F, between the first under cut 254 and the second under cut 252 using a second stop layer 272 having the second under cut 252 formed thereon as a mask. A portion 276 of the second interlayer insulating film having a protruding shape present in the etch is removed by etching. The copper interconnection 215 may be exposed by etching the first stop layer 220 on which the first undercut 254 is formed.

That is, by using a second stop layer 272 having the second undercut 252 as a hard mask, a portion of the second interlayer insulating layer 276 protruding from the sidewall of the via hole 242 is reactively ion-etched to form a via. The dual damascene structure 284 having the bottom is rounded while the hole sidewalls are flat, and the first stop layer 220 having the first undercut 254 is etched to expose the copper interconnect 215. I can complete it.

Next, as shown in FIG. 2G, a metal wiring 290 may be formed by filling a metal material in a trench and a via hole having a bottomed dual damascene structure 284.

The metal wiring of the semiconductor device according to the embodiment of the present invention may include a first interlayer insulating layer 210 on which a first metal wiring 215 is formed, and a first stop layer 220 stacked on the first interlayer insulating layer 210. ), A second interlayer insulating layer 225, a second stop layer 230, a third interlayer insulating layer 235, and the third interlayer insulating layer 235 to expose the first stop layer 220. A via hole formed through the second stop layer 230 and the second interlayer insulating layer 225, an under cut formed in the first stop layer 220 exposed to a bottom of the via hole, and A trench 265 is formed in the third interlayer insulating layer around the via hole, and the second metal wire 290 is embedded in the trench 265 and the via hole in which the undercut is formed. The under cut may have a round shape.

As described above, by rounding the bottom portion of the via hole having the damascene structure, the barrier metal formed at the edge portion of the bottom of the via hole is reduced in the process of forming the barrier metal in the via hole. Reliability can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A to 1D are cross-sectional views illustrating a method for forming a copper wiring by a general damascene process.

2A to 2G are process diagrams illustrating a metal wiring forming method according to an embodiment of the present invention.

Claims (11)

Sequentially forming a first stop film, a second interlayer insulating layer, and a third interlayer insulating layer on the first interlayer insulating layer on which the metal wiring is formed; Sequentially etching the third interlayer insulating layer and the second interlayer insulating layer to form a via hole exposing the first stop layer; Wet etching the first stop layer exposed on the bottom of the via hole to form a first undercut on the first stop layer; And Forming a trench by etching a third interlayer insulating layer around the via hole. The method of claim 1, wherein the metal wiring forming method of the semiconductor device is performed. Forming a second stop film between the second interlayer insulating layer and the third interlayer insulating layer; And And etching the second stop layer to expose sidewalls of the second stop layer when the via hole is formed. The method of claim 2, wherein the metal wiring forming method of the semiconductor device is performed. And forming a second undercut in the second stop layer by wet etching the second stop layer exposed to the sidewall of the via hole when the first undercut is formed in the first stop layer. Method for forming metal wiring of the device. The method of claim 3, wherein the forming of the trench comprises: Etching a third interlayer insulating layer around the via hole to form a trench for exposing a second stop layer on which a second undercut is formed. The method of claim 4, wherein the metal wiring forming method of the semiconductor device is performed. Etching the second interlayer insulating layer exposed on the sidewalls of the via hole using the exposed second stop layer as a mask. The method of claim 4, wherein the metal wiring forming method of the semiconductor device is performed. Gap-filling a sacrificial layer in a via hole in which the first under cut and the second under cut are formed between the forming of the first and second under cuts and forming the trench, Forming the trench, And forming the trench by etching the sacrificial layer and a third interlayer insulating layer around the gap-filled sacrificial layer. The method of claim 5, wherein the metal wiring forming method of the semiconductor device, And etching the first stop film on which the first under cut is formed by using the exposed second stop film as a mask to expose the metal wires. The method of claim 7, wherein Etching the second interlayer insulating layer exposed on the sidewalls of the via hole, and etching the first stop layer on which the first undercut is formed to expose the metal wiring, is performed simultaneously. Forming method. The method of claim 3, The metal line forming method of the semiconductor device, characterized in that the metal wiring is not exposed when forming the second under cut. A first interlayer insulating layer on which first metal wirings are formed; A first stop film, a second interlayer insulating layer, a second stop film, and a third interlayer insulating layer stacked on the first interlayer insulating layer; A via hole formed through the third interlayer insulating layer, the second stop layer, and the second interlayer insulating layer to expose the first stop layer; A first under cut formed in the first stop layer exposed on the bottom of the via hole A trench formed in a third interlayer insulating layer around the via hole; And And a second metal wire embedded in the trench and the via hole in which the first under cut is formed. The method of claim 10, The first under cut is a metal wire of a semiconductor device, characterized in that the round (round).
KR1020080137727A 2008-12-31 2008-12-31 A metal line of semiconductor device and method of manufacturing the same KR20100079297A (en)

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