KR20100079195A - Structure of flash memory - Google Patents

Abstract

PURPOSE: A structure of a flash memory is provided to increase a source/drain current without increasing a gate voltage by implementing an additional control gate on the drain. CONSTITUTION: A tunnel oxide layer(102) is formed in on a gate region of a semiconductor substrate. A floating gate(104) is formed on the tunnel oxide film with poly-crystal silicon. A blocking insulation layer(106) is formed on the floating gate. A first control gate(108) is formed on the blocking insulation layer. The first control gate is formed within the active region of the semiconductor substrate of the floating gate. A second control gate(114) having the same height of the floating gate is formed on the drain to induce the charge inside the floating gate to a drain direction.

Description

Flash memory structure {STRUCTURE OF FLASH MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory, and in particular, to implement a control gate by implementing an additional control gate at a position adjacent to a floating gate above a drain in a structure of a flash memory device. By applying a voltage opposite to the above, the charge in the floating gate is induced in the drain direction to increase the pinch-off voltage of the drain to increase the source / drain current. It relates to a flash memory structure.

In general, the flash memory is started to simultaneously realize the advantages of conventional erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM). Programming and erasing are possible, but a simple manufacturing process and a small chip size can be realized.

In addition, the flash memory is a nonvolatile semiconductor memory that does not lose data even when the power supply is interrupted. However, since the flash memory is electrically easy to program and erase information in the system, it is a random access memory (RAM). It is used for the memory device which replaces the hard disk of a memory card or a portable office automation equipment.

The programming of data in such flash memory is by injection of hot electrons. That is, when hot electrons are generated in the channel due to the potential difference between the source and the drain, some electrons having energy of 3.1 eV or more, which is a potential barrier between the polycrystalline silicon that forms the gate and the oxide layer, are formed. The electrons are moved to the floating gate and stored by the high electric field across the control gate.

Meanwhile, in the flash memory device as described above, pinch-off occurs as the drain voltage increases, and the current flowing from the source to the drain no longer increases due to the occurrence of the pinch-off. Accordingly, in order to increase the drain voltage at which pinch-off occurs, the gate voltage must be increased. However, increasing the gate voltage has a limitation in terms of device reliability.

Accordingly, the present invention implements an additional control gate at a position adjacent to the floating gate on the drain in the structure of the flash memory device to apply a voltage opposite to the control gate, thereby inducing charge in the floating gate in the drain direction to drain A flash memory architecture is provided to increase the pin-off voltage of the circuit to increase the source / drain current.

The present invention described above includes a tunnel oxide film formed in a gate formation region on a semiconductor substrate, a floating gate formed of polycrystalline silicon on the tunnel oxide film, a blocking insulating film formed on the floating gate, and a first insulating film formed on the blocking insulating film. A control gate, a source and a drain formed through ion implantation of impurities in the active regions of the semiconductor substrates on both sides of the floating gate, and formed on the drain at the same height as the floating gate to drain the charge in the floating gate. And a second control gate leading in the direction.

The present invention implements an additional control gate at a position adjacent to the floating gate above the drain in the flash memory structure to apply a voltage opposite to the control gate, thereby inducing charge in the floating gate in the drain direction to reduce the pinch-off voltage of the drain. This increases the source-drain current without increasing the gate voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be made based on the contents throughout the specification.

1 is a cross-sectional view of a flash memory according to an embodiment of the present invention. Hereinafter, a flash memory structure capable of increasing the drain current by increasing the pinch-off voltage of the drain without increasing the gate voltage will be described in detail with reference to FIG. 1.

First, a tunnel oxide layer 102 is formed on the semiconductor substrate 100, and then poly-silicon is deposited thereon to form a floating gate 104.

Next, a blocking insulating film 106 having an oxide film / nitride film / oxide (hereinafter referred to as ONO) structure is formed on the floating gate.

In this case, in order to form the blocking insulating film 106 having the ONO structure, a polycrystalline silicon layer of the floating gate 104 is thermally oxidized to form a lower oxide film on the floating gate 104, and then silicon is thermally formed on the lower oxide film. The nitride film is formed, and the upper oxide film is formed on the thermal process again, and then annealed.

Subsequently, the first control gate 108 is formed by depositing a polycrystalline silicon layer on the gate insulating layer 106 to serve as a substantial electrode, and then impurities are implanted into the active region on the semiconductor substrate through an ion implantation process. Injecting to form a source (110) and drain (112).

Subsequently, the second control gate 114 is formed on the drain 112 at the same height as the floating gate 104.

In this case, an insulating film 116 is formed between the second control gate 114 and the drain 112 in the range of 300 to 400 kV to be applied to the second control gate 114 when a voltage is applied to the second control gate 114. The voltage does not affect the drain 112.

In addition, an insulating film 116 is formed between the second control gate 114 and the floating gate 104 to a thickness in the range of 100 to 150 kV to drain the charge in the floating gate 104 when a voltage is applied to the second control gate 114. The direction of 112 increases the pinch-off voltage of the drain to increase the current between the source 110 and the drain 112 without increasing the voltage applied to the first control gate 108.

FIG. 2 illustrates an electrical concept in which charge in the floating gate is directed toward the drain through a second control gate formed adjacent to the floating gate on the drain according to an embodiment of the present invention.

As shown in FIG. 2, a voltage "-" opposite to the first control gate 108 is applied to the second control gate 114 formed at a position adjacent to the floating gate 104 on the drain 112. In this case, it can be seen that + ions in the floating gate 104 are directed toward the drain 112.

Accordingly, the pinch-off voltage of the drain 114 may be increased by the charge in the floating gate 104 induced by the second control gate 114 in the drain 112 direction as described above, and thus the first control gate 108 may be increased. It is possible to increase the current between the source 110 / drain 112 without increasing the voltage to be applied to).

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

1 is a cross-sectional view of a structure of a flash memory device according to an embodiment of the present invention;

2 is a conceptual diagram of charge transfer in a floating gate according to an exemplary embodiment of the present invention.

<Brief description of the major symbols in the drawings>

100 semiconductor substrate 102 tunnel oxide film

104: floating gate 106: gate insulating film

108: first control gate 110: source

112: drain 114: second control gate

Claims (4)

A tunnel oxide film formed in a gate formation region on a semiconductor substrate, A floating gate formed of polycrystalline silicon on the tunnel oxide film; A blocking insulating layer formed on the floating gate; A first control gate formed on the blocking insulating layer; A source and a drain formed through ion implantation of impurities into the active regions of both semiconductor substrates of the floating gate; A second control gate formed on the drain at the same height as the floating gate to induce charge in the floating gate in the drain direction; Flash memory structure comprising a. The method of claim 1, The second control gate, And a voltage opposite to the first control gate is applied. The method of claim 1, The second control gate, And a drain and an insulating film having a thickness of 300 to 400 Å interposed therebetween. The method of claim 1, The second control gate, And a floating gate and an insulating film having a thickness of 100 to 150 Å interposed therebetween.

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