JP2010062359A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device having a nonvolatile memory. <P>SOLUTION: A first protective film pt1 is formed while covering a memory gate insulating film MI1 and a memory gate electrode MG1 formed in order on a principal surface s1 of a silicon substrate 1. Then an n-type ion implantation region n1 is formed by performing ion implantation dp01 on the principal surface s1 below the side of the memory gate insulating electrode MG1. Successively, the n-type ion implantation region n1 is diffused and activated through a heat treatment to form an n-type memory extension region. In the ion implantation dp01, the memory gate electrode MG1 and the first protective film pt1 formed on a side wall thereof serve as an ion implantation mask, and the n-type ion implantation region n1 is formed at a distance of the thickness of the first protective film p1 from the memory gate electrode MG1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing method of a semiconductor device having a nonvolatile memory.

  EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a nonvolatile semiconductor memory element (nonvolatile memory cell) that can be electrically written and erased. These nonvolatile memory cells include a floating (floating) conductor portion under the gate electrode of a MIS (Metal Insulator Semiconductor) type field effect transistor (also referred to as FET) (hereinafter simply referred to as MIS transistor). The structure includes an insulating film having a function of accumulating charge carriers (carriers) and a structure (floating gate electrode structure). Data writing and data erasing are realized by accumulating charges in these floating gate electrodes and charge accumulating films, and controlling the injection or emission of charges to the charge accumulating region by the MIS structure.

  As described above, when charge is injected (or released) into the charge storage region, the threshold voltage of the MIS transistor changes. In the MIS transistor, the change in the threshold voltage appears as a difference in drain current flowing according to the applied gate voltage. The charge accumulation state, that is, the data holding state can be read by the amount of drain current of the MIS transistor. The memory operation is realized by the data writing, erasing and reading functions as described above.

  As an insulating film having a charge storage function, an insulating film mainly composed of silicon nitride (hereinafter simply referred to as a silicon nitride film) is known. The silicon nitride film formed over the semiconductor substrate becomes a film containing many defects inside depending on the formation conditions. Such a defect in the film functions as a carrier trap level. Such charges trapped in the trap level of the silicon nitride film are difficult to leak out. Therefore, a nonvolatile memory using a silicon nitride film as a charge storage film is excellent in data retention for a long time.

  Further, a structure in which both sides of the silicon nitride film are sandwiched between other insulating films is useful so that carriers trapped in the silicon nitride film do not easily leak into the upper electrode or the lower substrate. For example, a so-called ONO (oxide / Nitride / oxide) insulating film in which both sides of a silicon nitride film are sandwiched between insulating films mainly composed of silicon oxide (hereinafter simply referred to as silicon oxide film) is used. There is a nonvolatile memory cell that realizes a read operation by regarding the ONO insulating film as a gate insulating film of a MIS transistor. This has a basic configuration of a gate electrode (Metal) / ONO insulating film / semiconductor substrate (Semiconductor), and is called a so-called MONOS type nonvolatile memory cell (hereinafter simply referred to as a MONOS type memory cell).

For example, Japanese Patent Laying-Open No. 2005-332502 (Patent Document 1) discloses a structure of a flash memory including a MONOS type nonvolatile memory and an operation method.
JP-A-2005-332502

  The MONOS type memory cells as described above are arranged and used in a two-dimensional matrix form (memory cell array) as in a normal nonvolatile memory. Then, the memory cells arranged on the substrate are electrically accessed to arbitrary memory cells by wiring from two directions, and a write operation and an erase operation are performed. In addition, it is possible to perform a batch operation on a plurality of memory cells electrically connected to the wiring by using the wiring in one direction. This is effective when it is desired to erase all the nonvolatile memory cells in an arbitrary area.

  However, as a result of studies by the present inventors, it has been clarified that the MONOS type memory cells arranged in a two-dimensional matrix have the following problems depending on the operating conditions. That is, it has been found that when a write operation is performed on a desired memory cell, a so-called disturb phenomenon occurs in which another cell is erroneously erased.

  Further examination by the present inventor has revealed that one cause of the above problem is due to junction leakage between the diffusion layer constituting the MONOS type memory cell and the semiconductor substrate.

  Furthermore, it has also been clarified that such a problem becomes more conspicuous as a result of higher functionality and higher integration due to device miniaturization. As described above, it has been found that the semiconductor device including such a MONOS type memory cell is a cause of hindering further improvement in reliability and lowering reliability.

  Therefore, an object of the present invention is to provide a technique for improving the reliability of a semiconductor device having a nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  A step of forming a non-volatile memory cell on a semiconductor substrate, wherein a first gate electrode is formed on a main surface of the semiconductor substrate with a first gate insulating film having a function of accumulating charges, and the first gate electrode is covered therewith. Forming a first protective film, and then implanting impurity ions into a region below the side of the first gate electrode on the main surface of the semiconductor substrate, and diffusing and activating it by heat treatment to thereby form the first semiconductor region Form. In the step of implanting impurity ions, the thickness of the first protective film is increased from the side wall of the first gate electrode by performing ion implantation using the first gate electrode and the first protective film formed on the side wall as an ion implantation mask. Impurity ions are implanted at positions separated by a distance.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the reliability of a semiconductor device having a nonvolatile memory can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
In the following, first, the configuration and operation of a MONOS type nonvolatile memory cell investigated by the present inventors will be described. These are the same as the configuration of the non-volatile memory included in the semiconductor device of the first embodiment except for a part to be noted later. After describing the configuration and operation, problems found by the present inventors in the memory operation will be described.

  FIG. 1 shows the structure of a MONOS type nonvolatile memory cell NVMa studied by the present inventors. The components included in the nonvolatile memory cell NVMa studied by the present inventors will be described in detail below. FIG. 1 is a cross-sectional view of a main part of a nonvolatile memory cell NVMa examined by the present inventors. The semiconductor device examined by the present inventor has a plurality of nonvolatile memory cells NVMa formed on a silicon substrate (semiconductor substrate) 1.

  The silicon substrate 1 is a thin plate-like semiconductor material made of single crystal silicon (Si), and may be p-type conductivity type or n-type conductivity type. Here, the conductivity type of the silicon substrate 1 is assumed to be p-type. In the silicon substrate 1 and various semiconductor regions described below, the p-type conductivity type represents a conductivity type of a semiconductor material that contains more acceptor impurities than donor impurities and has majority carriers as holes. . On the other hand, the n-type conductivity type represents a conductivity type of a semiconductor material that contains more donor impurities than acceptor impurities and whose majority carriers are electrons. Thus, the p-type conductivity type and the n-type conductivity type have opposite polarities (reverse conductivity types).

  An isolation n well nw1 which is an isolation n-type semiconductor region is formed on the main surface s1 of the silicon substrate 1. Further, an element p-well pw1, which is a p-type semiconductor region for element formation, is formed on the main surface s1 of the silicon substrate 1 and is shallower than the separation n-well nw1. On the main surface s1 of the silicon substrate 1, a memory gate electrode (first gate electrode) MG1 is formed with a memory gate insulating film (first gate insulating film) MI1 therebetween. The memory gate insulating film MI1 and the memory gate electrode MG1 are disposed on the main surface s1 of the silicon substrate 1 at a position that is planarly included in the element p-well pw1.

  The memory gate insulating film MI1 is a film having a function of accumulating charges such as electrons and holes. For example, it may be a conductor film (floating conductor film) surrounded by an insulating film or an ONO structure insulating film. Here, the memory gate insulating film MI1 will be described as an insulating film having an ONO structure. That is, the memory gate insulating film MI1 is composed of a lower barrier film bb1, a charge storage film st1, and an upper barrier film bt1 formed in order from the side closer to the silicon substrate 1, and both barrier films bb1 are formed above and below the charge storage film st1. , Bt1.

Here, the charge storage film st1 is an insulating film having a function of capturing charges. As such an insulating film, an insulating film having a large number of charge trapping centers (also simply referred to as traps) in the film is suitable. For example, an insulating film mainly containing silicon nitride (SiN), hafnium silicate (HfSiO), hafnium aluminate (HfAlO), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like can be given. Here, an insulating film mainly composed of silicon nitride (hereinafter simply referred to as a silicon nitride film) is applied as the charge storage film st1.

Further, the lower and upper barrier films bb1 and bt1 sandwiching the charge storage film st1 are insulating films having a function of preventing the charge trapped in the charge storage film st1 from leaking to the outside. As such an insulating film, an insulating film having a sufficiently high energy barrier (barrier) as viewed from the charges trapped in the trap in the charge storage film st1 is suitable. In other words, an insulating film having a band gap larger than that of the silicon nitride film and having a sufficiently high band offset between the conductive band side and the valence band side with respect to the silicon nitride film is suitable. As such lower and upper barrier films bb1 and bt1, insulating films (hereinafter simply referred to as silicon oxide films) mainly composed of silicon oxide (SiO ₂ ) are applied. Thus, the memory gate insulating film MI1 has an ONO structure in which a silicon nitride film having trapping properties is sandwiched between silicon oxide films having barrier properties.

  The memory gate electrode MG1 is made of a conductor film mainly composed of polycrystalline silicon (or polysilicon).

  As described above, the nonvolatile memory cell NVMa has the MONOS structure including the memory gate electrode MG1 that is the conductor region, the memory gate insulating film MI1 that is the insulator region of the ONO structure, and the element p-well pw1 that is the semiconductor region. have. This can be said to have the MIS structure when the memory gate insulating film MI1 having the ONO structure is regarded as one insulator region. Further, the nonvolatile memory cell NVMa has the following charge supply mechanism.

  The nonvolatile memory cell NVMa has a charge supply mechanism including an n-type memory extension region (first semiconductor region) xn1 and a memory source / drain region sd1 on the main surface s1 of the silicon substrate 1 below the side of the memory gate electrode MG1. Have. The n-type memory extension region xn1 and the memory source / drain region sd1 are formed on the main surface s1 of the silicon substrate 1 in the element p-well pw1. In particular, the n-type memory extension region xn1 is disposed at the lower side of the memory gate electrode MG1, and the memory source / drain region sd1 is disposed outside the memory gate electrode MG1 when viewed in plan. The n-type memory extension region xn1 and the memory source / drain region sd1 are the same n-type semiconductor region and are electrically connected to each other.

  Since the n-type memory extension region xn1 is an n-type semiconductor region for supplying charges to the MONOS structure, the impurity concentration and depth are determined by the characteristics required for the nonvolatile memory NVMa. The memory source / drain region sd1 is an n-type semiconductor region for smoothly transferring and receiving external charges to the n-type memory extension region xn1. Therefore, the lower the resistivity of the memory source / drain region sd1, the better. For this reason, the memory source / drain region sd1 has a higher n-type impurity concentration and a deeper depth than the n-type memory extension region xn1.

  As described above, the nonvolatile memory cell NVMa includes the memory gate insulating film MI1 and the memory gate electrode MG1, and the n-type source / drain structure formed in the p-type element p-well pw1. This can also be regarded as an n-channel type MIS transistor (hereinafter simply referred to as an n-type MIS transistor).

  Further, a sidewall spacer sw made of, for example, a silicon oxide film is formed so as to cover the sidewall of the memory gate electrode MG1 and the silicon substrate 1 at the lower side thereof. This is a component for isolating a memory gate electrode from other conductive parts such as a contact plug (not shown). The sidewall spacer sw is formed so as not to cover at least a part of the memory source / drain region sd1 in the main surface s1 of the silicon substrate 1 at the lower side from the side wall of the memory gate electrode MG1.

  In addition, there is a technique for improving characteristics as a MIS transistor by applying a stress to the silicon substrate 1 (particularly a channel region). For this purpose, the sidewall spacer sw may be formed using a material having a large stress action on the silicon substrate 1. In this case, for example, a silicon nitride film or the like may be used in addition to the silicon oxide film, and the sidewall spacer sw may be configured as the n stacked structure. In the following description, it is assumed that the sidewall spacer sw is made of only silicon oxide.

  In the semiconductor device studied by the present inventors, the nonvolatile memory NVMa having the above structure is formed on the silicon substrate 1 in a two-dimensional matrix. Various wirings are applied to the plurality of nonvolatile memory cells NVMa arranged in this way, and the elements are energized during operation. FIG. 2 shows a circuit diagram thereof. A method for energizing the memory cell array will be described with reference to FIG. 2 while referring to the structure of the nonvolatile memory cell NVMa in FIG.

  The memory gate electrodes MG1 of the nonvolatile memory cells NVMa arranged in the same row direction are connected by one word line WL. By energizing the word line WL, the nonvolatile memory cell NVMa having the memory gate electrode MG1 connected to the corresponding word line WL can be turned on. That is, in the memory arranged in a two-dimensional matrix, the nonvolatile memory cells NVMa arranged in the row direction are switched on / off at once by one word line WL.

  Further, the memory source / drain regions sd1 of the nonvolatile memory cell NVMa are formed at two symmetrical positions with respect to the memory gate electrode MG1. These two memory source / drain regions sd1 have the same configuration and are paired. In the operation of the nonvolatile memory cell NVMa, one pair of the memory source / drain regions sd1 functions as a charge supply source (source) and the other functions as a charge discharge destination (drain). In the nonvolatile memory cells NVMa arranged in the same column direction, the memory source / drain region sd1 that functions as the source is connected to one source line SL. Similarly, the memory source / drain region sd1 that functions as a drain is connected to one data line DL.

  The back gates of the plurality of nonvolatile memory cells NVMa arranged in a two-dimensional matrix are connected to the element p-well pw1.

  Here, a method of performing a write operation on the nonvolatile memory cell NVMa in the cell region c01 and the cell region c02 in FIG. 2 will be described. A gate voltage Vg of 6.5 V is applied to the word line WL for energizing the cell regions c01 and c02, and −6 V is applied to the source and data lines SL and DL as source and drain voltages Vs and Vd. . Further, −6V is applied as the substrate voltage Vsub to the back gate. An explanatory diagram of the nonvolatile memory cell NVMa in the cell regions c01 and c02 in such a write state is shown in FIG.

  A gate voltage Vg of 6.5 V is applied to the memory gate electrode MG1, and the nonvolatile memory cell NVMa having the MIS structure is turned on. In other words, an inversion layer is formed on the surface of the element p-well pw1 under the memory gate insulating film MI1, and electrons e are generated abundantly. Further, the source and drain voltages Vs and Vd of −6 V are applied to the memory source / drain region sd1 that is conductive to the channel region. Therefore, a potential difference of 12.5 V is generated between the memory gate electrode MG1 and the channel region. In particular, when viewed from the electrons e generated in the channel region, the potential is positive in the direction of the memory gate electrode MG1, and the electrons e are injected into the memory gate insulating film MI1 due to this potential difference.

  As described above, in the non-volatile memory cell NVMa that is an n-type MIS transistor, when the memory gate insulating film MI1 is negatively charged by the injection of electrons e, the gate voltage Vg higher than usual is set to turn on. Cost. More specifically, in the n-type MIS transistor, the channel region is strongly inverted by the positive gate voltage Vg to generate electrons e. Therefore, when the memory gate insulating film MI1 is negatively charged, the electric field effect exerted on the channel region by the positive gate voltage Vg is reduced. That is, in the nonvolatile memory NVMa as described above, the threshold voltage Vth rises due to the injection of electrons e into the memory gate insulating film MI1. This state is referred to as a write state.

  As shown in FIG. 2, among the memory cells connected to the same word line WL as the memory cell that performs the write operation, those that do not perform the write operation are connected to the source and data lines SL and DL with the source and The drain voltages Vs and Vd are applied with 1.5V. Further, among the memory cells connected to the same source and data lines SL and DL as the memory cell that performs the write operation, those that do not perform the write operation are supplied with −6 V as the gate voltage Vg to the word line WL. .

  Next, a method for performing an erasing operation on the nonvolatile memory cell NVMa in the cell region c03 in FIG. 4 will be described. A gate voltage Vg of −4.5 V is applied to the word line WL for energizing the cell region c03, and 6.5 V is applied to the source and data lines SL and DL as source and drain voltages Vs and Vd. . In addition, a substrate voltage Vsub of 6.5 V is applied to the back gate. An explanatory diagram of the nonvolatile memory cell NVMa in the cell region c03 in such an erased state is shown in FIG.

  A gate voltage Vg of −4.5 V is applied to the memory gate electrode MG1, and a substrate voltage Vsub of 6.5 V is applied to the element p-well pw1. As a result, a potential difference of 11 V is generated between the two. In particular, when viewed from the electrons e injected into the memory gate insulating film MI1, it has a positive potential in the direction of the element p-well pw1, and due to this potential difference, the electrons e are emitted from the memory gate insulating film MI1. The Similarly, holes h in the element p-well pw1 are injected into the memory gate insulating film MI1. Thus, under the bias conditions as described above, the memory gate insulating film MI1 is positively charged due to the emission of electrons e or the injection of holes h. In the nonvolatile memory cell NVMa that is an n-type MIS transistor, when the memory gate insulating film MI1 is positively charged, the threshold voltage is lowered contrary to the above-described write operation. This state is referred to as an erased state.

  As shown in FIG. 4, 6.5 V is applied as the gate voltage Vg to the word line WL connected to the memory cell not subjected to the erase operation. As a result, no potential difference occurs between the element p-well pw1 to which the same substrate voltage Vsub of 6.5 V is applied and the memory gate electrode MG1, and no charge transfer occurs.

  As described above, a write operation and an erase operation are performed on the nonvolatile memory cells NVMa arranged in a two-dimensional matrix. Here, the storage state of the nonvolatile memory cell NVMa is realized by changing the threshold voltage Vth by transferring charges to the memory gate insulating film MI1. Then, the nonvolatile memory cell NVMa is operated as an n-type MIS transistor, and the magnitude of the threshold voltage Vth is determined by measuring the current value between the source and drain when a predetermined gate voltage Vg is applied. In this way, the storage state of the nonvolatile memory cell NVMa can be read.

  On the other hand, according to further studies by the present inventor, the operation method of the non-volatile memory cell NVMa as described above has the following problems in the write operation described with reference to FIGS. I understood.

  As shown in FIG. 6, in the write operation to the nonvolatile memory cells NVMa arranged in a two-dimensional matrix, the cell regions c01 and c02 to which the write operation is performed do not share the word line WL, and the source and There are cell regions c04 and c05 that do not share the data lines SL and DL. As described above, −6V gate voltage Vg is applied to the nonvolatile memory cells NVMa in the cell regions c04 and c05 through the word line WL, and 1.5V source and drain are supplied through the source and data lines SL and DL. Voltages Vs and Vd are applied. An explanatory view of the nonvolatile memory cell NVMa in the cell regions c04 and c05 under such a bias condition is shown in FIG.

  Under the bias conditions as described above, a voltage of −6 V is applied to both the memory gate electrode MG1 and the element p-well pw1, there is no potential difference between them, and no charge is transferred in the memory gate insulating film MI1. it is conceivable that. However, due to the following phenomenon investigated by the present inventors, charge is actually transferred to the memory gate insulating film MI1.

  A voltage of 1.5 V is applied to the n-type memory extension region xn1 through the memory source / drain region sd1, and a voltage of −6 V is applied to the element p-well pw1. In this state, the reverse bias of 7.5 V is applied to the pn junction. In such a pn junction to which a high reverse bias is applied, electron-hole pairs can be generated by electric field concentration, particularly in the vicinity of the junction. Of the generated electron-hole pairs, the electron e is attracted and transported by the source or drain voltages Vs and Vd, and becomes a junction leakage current.

  On the other hand, the holes h are attracted to the gate voltage Vg, which is a negative voltage, or the substrate voltage Vsub, which is a negative voltage having the same magnitude. A part of the holes h drawn to the memory gate electrode MG1 can be injected into the memory gate insulating film MI1. Such injection of holes h into the memory gate insulating film MI1 is similar to the above-described erase operation. That is, during the write operation, it was found that an unintended erase operation is performed in the nonvolatile memory cell NVMa that is not the operation target. However, the electric field is gentle compared to the normal erase operation described above, and the amount of holes h injected into the memory gate insulating film MI1 is small. However, this is a phenomenon that occurs every write operation, and the injected holes h accumulate as the number of write operations is accumulated. As a result, it was confirmed that the threshold voltage Vth of the non-volatile memory cell NVMa that was not erased decreased to the erased state. This is called erroneous erasure or data disturb phenomenon. As a result, a problem has been found that the reliability of the semiconductor device having the non-volatile memory cell NVMa as described above is lowered.

  The structure of the nonvolatile memory cell NVM of Embodiment 1 that can solve the above-described problems will be described with reference to FIG. The structure and operation method of the nonvolatile memory cell NVM included in the semiconductor device of the first embodiment are the same as those of the nonvolatile memory cell NVMa described with reference to FIGS. 1 to 7 except for the following points. .

  The nonvolatile memory cell NVM of Embodiment 1 is different from the nonvolatile memory cell NVMa described in FIG. 1 with respect to the arrangement of the n-type memory extension region xn1. In the nonvolatile memory cell NVMa of FIG. 1 examined by the present inventors, the n-type memory extension region xn1 has a portion overlapping the memory gate electrode MG1 in a plane. On the other hand, in the nonvolatile memory cell NVM of the first embodiment, the planarly overlapping portion between the n-type memory extension region xn1 and the memory gate electrode MG1 is small. With such a structure, the electric field concentration at the junction between the n-type memory extension region xn1 and the element p-well pw1 as described with reference to FIGS. It can be set as the structure which is easy to suppress. Thereby, erroneous erasure in the nonvolatile memory cell NVM that does not perform a desired operation can be made more difficult to occur. As a result, the reliability of the semiconductor device having a nonvolatile memory can be improved.

  Further, it is more preferable that the n-type memory extension region xn1 and the memory gate electrode MG1 do not have a planar overlap portion, and the n-type memory extension region xn1 and the memory gate electrode MG1 are not separated from each other. That is, it is more preferable that the end portions of the n-type memory extension region xn1 and the memory gate electrode MG1 are arranged so as to be in the same position in plan view. This is because when the nonvolatile memory cell NVM is operated as a MIS transistor, the inversion layer in the channel region is formed immediately below the memory gate electrode MG1. At this time, if the n-type memory extension region xn1 is away from the memory gate electrode MG1, it cannot be electrically connected to the inversion layer, and the resistance value increases. As a result, the driving force of the element is reduced. Therefore, by arranging the end portion of the n-type memory extension region xn1 at the same position as the end portion of the memory gate electrode MG1, it is possible to prevent erroneous erasure without reducing the current driving capability. . As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  Hereinafter, a method for manufacturing the nonvolatile memory cell NVM included in the semiconductor device of the first embodiment will be described. The semiconductor device according to the first embodiment has a plurality of nonvolatile memory cells NVM on the main surface of a silicon substrate (semiconductor substrate) 1, and in the following, a process of forming one of the nonvolatile memory cells NVM is representative. To explain. Note that, among the components used in the process, those described in FIGS. 1 to 8 are the same unless otherwise specified, and redundant description is omitted.

  First, as shown in FIG. 9, an n-type n well for separation nw1, which is an n-type semiconductor region, is formed on the main surface s1 side of the silicon substrate 1. For this purpose, impurity ions serving as donors are introduced into the silicon substrate 1 by ion implantation, and then the semiconductor region is formed by diffusing and activating the impurities by performing heat treatment. Hereinafter, the method for forming the semiconductor region is the same. However, when the p-type semiconductor region is formed by ion implantation and heat treatment, impurity ions serving as acceptors are implanted into the silicon substrate 1. Subsequently, an element p-well pw1 which is a p-type semiconductor region is formed on the main surface s1 side of the silicon substrate 1 so as to have a depth smaller than that of the separation n-well nw1.

  Here, the heat treatment for forming the separation n well nw1 and the element p well pw1 may be performed in the same process, or may be shared with other processes involving heating (for example, thermal oxidation). Also good. By doing so, the number of steps can be reduced. Hereinafter, a heat treatment step is always required after the ion implantation step, and the same applies to these unless otherwise specified.

  Although not shown in the drawing, if other peripheral circuits are formed on the main surface s1 of the silicon substrate 1 and these elements need to be insulated and isolated on the main surface s1, an isolation portion is formed. You may do it.

  Thereafter, ion implantation is performed on the main surface s1 of the silicon substrate 1 in order to adjust the impurity concentration of the main surface s1 of the silicon substrate 1 to be a channel region later. The impurity concentration of the channel region is mainly a parameter of the threshold voltage of the MIS transistor. For example, in the case of an n-type MIS transistor, the threshold voltage decreases as the p-type impurity concentration in the channel region decreases. As described above, the threshold voltage is a main parameter for the operation of the nonvolatile memory NVM according to the first embodiment, and is adjusted to the threshold voltage required for its characteristics. For this purpose, the above-described ion implantation is performed in this step.

Subsequently, a lower barrier film bb1, a charge storage film st1, and an upper barrier film bt1 are formed on the main surface s1 of the silicon substrate 1 in order from the side closer to the silicon substrate 1. Here, as described above, silicon oxide films are formed as the lower barrier film bb1 and the upper barrier film bt1. These are formed by a thermal oxidation method or a chemical vapor deposition (CVD) method. Further, a silicon nitride film is formed as the charge storage film st1. This is formed by a CVD method. However, as the charge storage film st1, an insulating film mainly composed of hafnium silicate (HfSiO), hafnium aluminate (HfAlO), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), or the like is formed. Also good. Also in this case, it is formed by the CVD method.

  Thereafter, a first conductor film E1 is formed so as to cover the upper barrier film bt1. As the first conductor film E1, a semiconductor film mainly composed of polycrystalline silicon (hereinafter simply referred to as a polycrystalline silicon film) is formed, and impurities are introduced by an ion implantation method or the like so as to obtain a desired conductivity type after the formation. Conductor with. Here, the polycrystalline silicon film as the first conductor film E1 is formed by a CVD method or the like, and is then made n-type conductivity by introducing an impurity serving as a donor.

  Next, as shown in FIG. 10, the first conductor film E1 is processed to form a memory gate electrode (first gate electrode) MG1. Here, an unnecessary portion of the first conductor film E1 is anisotropically etched and removed using a photoresist film (not shown) formed by a photolithography method or the like as an etching mask. Subsequently, similarly, the upper barrier film bt1, the charge storage film st1, and the lower barrier film bb1 are processed to form the memory gate insulating film (first gate insulating film) MI1. Through the above steps, the memory gate electrode MG1 is formed on the main surface s1 of the silicon substrate 1 with the memory gate insulating film MI1 interposed therebetween.

  Here, in the above process, an ONO structure including the lower barrier film bb1 (silicon oxide film), the charge storage film st1 (silicon nitride film), and the upper barrier film bt1 (silicon oxide film) is used as the memory gate insulating film MI1. The step of forming the insulating film has been described. Here, as the nonvolatile memory cell NVM of the first embodiment, any film having a function of accumulating charges may be used as the memory gate insulating film MI1. For example, unlike the structure in which the ONO structure insulating film is formed, a floating conductor film may be formed.

  However, in the process of forming the nonvolatile memory cell NVM of the first embodiment, it is more preferable to form the memory gate insulating film MI1 having the above ONO structure. This is because the gate voltage Vg (see FIG. 3 and the like) for transferring charges to the insulating film having the ONO structure can be lower than the gate voltage for transferring charges to the conductive film in the floating state. It is. Thereby, in a semiconductor device having a nonvolatile memory, effects such as reduction in memory area and improvement in reliability are brought about.

  Next, as shown in FIG. 11, a first protective film pt1 is formed so as to cover the main surface s1 of the silicon substrate 1 and the memory gate electrode MG1. Here, a silicon oxide film is formed as the first protective film pt1. Subsequently, n-type impurity ions are implanted by ion implantation dp01 in a region below the side surface of the memory gate electrode MG1 in the main surface s1 of the silicon substrate 1. A region of the main surface s1 of the silicon substrate 1 on which the ion implantation dp01 has been performed is referred to as an n-type ion implantation region n1.

  In this step, the first protective film pt1 is formed on the silicon substrate 1 without embedding the memory gate electrode MG1. In other words, the first protective film pt1 is formed on the silicon substrate 1 so as to have a surface along the outer shape of the memory gate electrode MG1. Accordingly, the first protective film pt1 is formed to have a shape having a surface along the side wall of the memory gate electrode MG1.

  In the ion implantation dp01, the impurity ions to be implanted pass through the thickness of the first protective film pt1 as viewed from the main surface s1 of the silicon substrate 1, and the energy condition does not pass through the thickness of the memory gate electrode MG1. Then, ion implantation dp01 is performed. In other words, ion implantation dp01 is performed so that the first protective film pt1 becomes a transmission film and the memory gate electrode MG1 becomes an ion implantation mask.

  Here, as described above, the first protective film pt1 is formed to have a surface along the side wall of the memory gate electrode MG1. That is, in the first protective film pt1, at the side wall portion of the memory gate electrode MG1, the thickness viewed from the main surface s1 of the silicon substrate 1 is equal to or greater than the thickness of the memory gate electrode MG1. Therefore, when the above-described ion implantation dp01 is performed on the main surface s1 of the silicon substrate 1, the first protective film pt1 covering the side wall portion in addition to the memory gate electrode MG1 also serves as an ion implantation mask.

  As a result, the end of the n-type ion implantation region n1 is formed away from the end of the memory gate electrode MG1 when the main surface s1 of the silicon substrate 1 is viewed in plan. More details are as follows. FIG. 12 is an enlarged view showing an enlarged main portion p01 in the vicinity of the side end portion of the memory gate electrode MG1 in FIG. By applying the first protective film pt1 and performing the ion implantation dp01 as described above, the main surface s1 of the silicon substrate 1 is viewed in plan, and the thickness of the first protective film pt1 is measured from the side wall of the memory gate electrode MG1. The ion implantation dp01 is performed at a position separated by t01. In this way, the n-type ion implantation region n1 is formed by being offset from the memory gate electrode MG1 by a position separated by the thickness t01 of the first protective film pt1.

  Next, as shown in FIG. 13, the first protective film pt1 is removed by etching or the like. Thereafter, the impurity ions introduced as the n-type ion implantation region n1 are diffused and activated by heat treatment, thereby forming the n-type memory extension region (first semiconductor region) xn1.

  As described above, when the n-type memory extension region xn1 is formed by applying the first protective film pt1, the planarity between the n-type memory extension region xn1 and the memory gate electrode MG1 is larger than when the n-type memory extension region xn1 is not applied. The overlapping area becomes smaller. Thereby, the nonvolatile memory cell NVM of the first embodiment having the effect described with reference to FIG. 8 can be formed. That is, the electric field concentration on the n-type memory extension region xn1 described with reference to FIG. 7 can be alleviated, and the erroneous erasing operation can be made difficult to occur. As a result, the reliability of the semiconductor device having a nonvolatile memory can be improved.

  Furthermore, in FIG. 8, it has been described that the end of the memory gate electrode MG1 and the end of the n-type memory extension region xn1 are more preferably arranged at the same position as viewed in plan. That is, in the process described with reference to FIG. 13, the n-type ion implantation region n1 into which impurity ions are implanted reaches the side wall as the end of the memory gate electrode MG1 when the main surface s1 of the silicon substrate 1 is viewed in plan. It is more preferable to perform the heat treatment so as to diffuse to the position. Thereby, the nonvolatile memory cell NVM according to the first embodiment having the effect described with reference to FIG. 8 can be formed. That is, it is possible to form a structure that is unlikely to cause erroneous erasure without reducing the current driving force. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  In the case where the ion implantation dp01 is performed without applying the first protective film pt1 as described in FIG. 11 above, the end of the n-type ion implantation region n1 is already at the end of the ion implantation dp01. The gate electrode MG1 is disposed at the same position as the end of the gate electrode MG1. After the ion implantation dp01, it is necessary to activate at least the n-type ion implantation region n1, and thus heat treatment is an essential process. Therefore, the n-type ion implantation region n1 is diffused to the lower part of the memory gate electrode MG1 by the heat treatment. That is, in a process in which the first protective film pt1 is not applied, it is difficult to form a structure in which the memory gate electrode MG1 and the n-type memory extension region xn1 do not overlap in plan view.

  Further, as described with reference to FIG. 12, the n-type ion implantation region n1 is formed away from the side wall, which is the end of the memory gate electrode MG1, by the thickness t01 of the first protective film pt1. . The offset amount from the end of the memory gate electrode MG1 in the n-type ion implantation region n1 is a distance to be diffused later by heat treatment. Here, since the thermal diffusion is isotropic, the n-type ion implantation region n1 is diffused in the depth direction as well as the planar direction to form the n-type memory extension region xn1. Therefore, the initial offset amount is an important setting value for the characteristics of the nonvolatile memory cell NVM.

  From this viewpoint, according to the verification by the present inventors, the thickness of the first protective film pt1 is more preferably about 10 to 20 nm. This is because if the first protective film pt1 is thinner than 10 nm, the n-type ion implantation region n1 diffuses to the lower part of the memory gate electrode MG1 due to the influence of various heat treatments during the process, and it becomes difficult to obtain a clear effect. . Further, if the first protective film pt1 is thicker than 20 nm, diffusion in the depth direction equivalent to thermal diffusion in the plane direction becomes excessive, meeting the original functional requirement as the n-type memory extension region xn1. It becomes impossible. Therefore, in the manufacturing method of the first embodiment, it is more preferable that the thickness of the first protective film pt1 is 10 to 20 nm.

  Further, when the thickness of the first protective film pt1 is set to 10 to 20 nm as described above, in order to transmit the first protective film pt1 and make the n-type ion implantation region n1 have a desired depth, The present inventors have verified that it is preferable to implant phosphorus or arsenic ions at 20 to 40 keV as the ion implantation dp01.

  In the manufacturing method according to the first embodiment, the first protective film pt1 is formed for the purpose of providing an offset at the position where the n-type ion implantation region n1 is formed with respect to the memory gate electrode MG1. Therefore, for this purpose, the material is not limited to the silicon oxide film. However, as described with reference to FIG. 13, the first protective film pt1 needs to be removed. At this time, it is desirable that the memory gate electrode MG1 made of polycrystalline silicon, the silicon substrate 1 and the like can be selectively etched. From this viewpoint, in the manufacturing method of the first embodiment, it is more preferable to form a silicon oxide film as the first protective film pt1.

  In the subsequent process, as shown in FIG. 14, sidewall spacers sw made of a silicon oxide film are formed so as to cover the sidewalls of the memory gate electrode MG1. As described above, the sidewall spacer sw may be a stacked film of a silicon oxide film and a silicon nitride film. For this, first, a desired insulating film is deposited by a thermal oxidation method or a CVD method so as to cover the memory gate electrode MG1. Thereafter, the deposited film is etched back to leave the deposited film on the side wall portion of the memory gate electrode MG1, which is a stepped portion, and the others are removed. In this way, the sidewall spacer sw is formed.

  Thereafter, by using the memory gate electrode MG1 and the side wall spacer sw as an ion implantation mask, ion implantation is performed on the main surface of the silicon substrate 1, thereby forming a memory source / drain region sd1 at a lateral lower portion of the side wall spacer sw.

  As described above, the nonvolatile memory cell NVM of Embodiment 1 can be formed on the silicon substrate 1. Thereafter, an interlayer insulating film, a contact plug, or a wiring metal is formed, and a plurality of memory cells and peripheral circuit elements are connected to form a desired circuit configuration.

  The inventor has verified the effect of the nonvolatile memory cell NVM formed by the manufacturing method of the first embodiment. In the memory cells belonging to the cell regions c04 and c05 of FIG. 6, the time change of the threshold voltage when the bias state of FIG. 7 was continued was examined. The result is shown in FIG. The horizontal axis represents elapsed time, and the vertical axis represents threshold voltage.

  In the initial state, the threshold voltage Vth is a high value in the memory cell that has been written. Thereafter, in the cell regions c04 and c05 in FIG. 6, the bias condition is set such that no memory operation occurs, but the above-described erroneous erase operation occurs. As a result, holes h are injected into the memory gate insulating film MI1, and the threshold voltage Vth decreases with time.

  In FIG. 15, the characteristic of the nonvolatile memory cell NVM formed by the manufacturing method of the first embodiment is shown as characteristic r01. On the other hand, the characteristic of the nonvolatile memory cell NVMa formed by the method previously examined by the present inventor as described in FIG. 1 is shown as characteristic r02. As shown in the figure, in the characteristic r01 of the nonvolatile memory cell NVM according to the first embodiment, the threshold voltage Vth decreases more slowly with time. Thus, the effect of the manufacturing method according to the first embodiment was verified by the present inventor.

  Next, a more effective operation method in the memory in which the nonvolatile memory cells NVM of the first embodiment described above are arranged in a two-dimensional matrix will be described. FIG. 16 shows a voltage application method during a write operation for a plurality of nonvolatile memory cells NVM arranged in a two-dimensional matrix. For example, according to a prior study by the present inventors, there is a voltage application method as described with reference to FIGS. 2 and 6 in the cell regions c01 and c02 on which the write operation is performed. Also in the voltage application method of the first embodiment, the same voltage application method is used for the cell regions c01 and c02 subjected to the write operation.

  Here, as described above, an erroneous erase operation may occur in the cell regions c04 and c05 where the write operation is not performed. As described with reference to FIG. 7, this is because the holes h of the electron-hole pairs generated by the electric field concentration at the junction between the n-type memory extension region xn1 and the element p-well pw1 are the memory gate electrode MG1. This is caused by being pulled by the negative gate voltage Vg and injected into the memory gate insulating film MI1. According to the nonvolatile memory cell NVM of the first embodiment described above, this electric field concentration can be alleviated and a structure in which erroneous erasure hardly occurs can be obtained.

  Here, the erroneous erasure can be more effectively suppressed by further setting the gate voltage Vg applied to the nonvolatile memory cells NVM in the cell regions c04 and c05 as follows. That is, among the non-volatile memory cells NVM that are not subjected to the write operation, the word lines WL of the cell regions c04 and c05 that do not share the word line WL with the cell regions c01 and c02 that perform the write operation have a gate voltage Vg of −5V. Apply voltage. This is equivalent to changing the gate voltage Vg (−6V in the above) of the corresponding cell regions c04 and c05 by 1V in the positive direction as compared with the bias condition described in FIG.

  By setting the voltage application conditions as described above, as shown in FIG. 17, the negative electric field of the memory gate electrode MG1 viewed from the holes h of the generated electron-hole pairs is weakened, and the memory gate insulating film MI1 is formed. The hole h injection is reduced. Further, since the substrate voltage Vsub (−6 V), which is a negative voltage higher than the memory gate voltage Vg (−5 V), is applied to the element p-well pw1, the hole h is more element than the memory gate electrode MG1. It becomes easy to transport to the p-well pw1 side. Accordingly, the injection of holes h into the memory gate insulating film MI1 is further reduced. As described above, by setting the bias condition for the cell regions c04 and c05 where the write operation is not performed, erroneous erasure to the nonvolatile memory cell NVM is less likely to occur. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  The inventor verified this effect in the same manner as the method described with reference to FIG. The result is shown in FIG. A change in threshold voltage Vth over time when the nonvolatile memory cell NVM of Embodiment 1 is used and a voltage is applied under the bias conditions shown in FIGS. 16 and 17 is shown as a characteristic r03. As shown in the figure, compared with the characteristic r02 (detailed in FIG. 15) in which the decrease in the threshold voltage Vth is improved, in this characteristic r03, the decrease in the threshold voltage Vth is further suppressed. Thus, the effect of the voltage application method of the first embodiment was verified by the present inventor.

(Embodiment 2)
In the second embodiment, as a method for forming the nonvolatile memory cell NVM described in the first embodiment, a nonvolatile memory cell is shared while sharing a process of forming a MIS transistor (field effect transistor) applied to a peripheral circuit. A method for forming the NVM will be described. The configuration and effects of the nonvolatile memory cell NVM included in the semiconductor device of the second embodiment are the same as those described in the first embodiment with reference to FIG. Is omitted. A method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

  FIG. 19 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment. The left side shows a region for forming a nonvolatile memory cell, and the right side shows a region for forming a MIS transistor applied to a peripheral circuit. Indicates. As the MIS transistors applied to the peripheral circuits, a total of four types of MIS transistors are used for high-speed applications (low breakdown voltage) and high-voltage applications (low speed) for n-channel and p-channel MIS transistors, respectively. The formation process is shown. In the drawing, a region where a nonvolatile memory cell is formed on the silicon substrate 1 is denoted as a memory region Rm. Similarly, a region for forming an n-type MIS transistor for high-speed use is a high-speed nMIS region Rsn, a region for forming a p-type MIS transistor for high-speed use is a high-speed pMIS region Rsp, and a region for forming an n-type MIS transistor for high withstand voltage is high. The breakdown voltage nMIS region Rvn and a region where a p-type MIS transistor for high breakdown voltage applications is formed are referred to as a high breakdown voltage pMIS region Rvp.

  First, in the same manner as described with reference to FIG. 9, the isolation n well nw1 is formed on the entire main surface s1 of the silicon substrate 1, and the element p well pw1 is formed in the memory region Rm. Thereafter, an isolation portion 2 having a so-called STI (Shallow Trench Isolation) structure in which an insulating film is buried in a shallow trench is formed.

  Subsequently, a photoresist film 3 is formed on the main surface s1 of the silicon substrate 1, and is patterned by a photolithography method or the like so as to cover the main surface s1 of the silicon substrate 1 other than the memory region Rm. Then, by performing ion implantation dp02 using the photoresist film 3 as an ion implantation mask, impurity ions are implanted into the main surface s1 of the silicon substrate 1 in the memory region Rm. This is a process for adjusting the channel concentration of the nonvolatile memory formed in the memory region Rm. After the ion implantation dp02 step, the implanted impurities are diffused and activated by heat treatment. This heat treatment step may be performed immediately after the main ion implantation dp02, or may be performed by sharing another heat treatment step. Hereinafter, unless otherwise specified, the heat treatment for impurity diffusion and activation after ion implantation is the same. In addition, a photoresist film used as a mask in the following various processes is patterned by photolithography.

  Next, as shown in FIG. 20, on the main surface s1 of the silicon substrate 1, an opening is made in a desired region among the MIS regions Rsn, Rsp, Rvn, and Rvp so as to cover other regions including the memory region Rm. A photoresist film 4 is formed. Then, ion implantation dp03 is performed using the photoresist film 4 as an ion implantation mask, followed by heat treatment, thereby forming an n well nws or the like on the main surface s1 of the silicon substrate 1 in the opening. Further, another ion implantation is performed with the same ion implantation mask to implant an impurity for adjusting the channel concentration. The figure shows a process of forming a photoresist film 4 having an opening in the high-speed pMIS region Rsp and forming an n-well region nws in the region Rsp.

  Prior to this step, a p well pwv and a n well nwv are formed in the high breakdown voltage nMIS region Rvn and the high breakdown voltage pMIS region Rvp, respectively, by a similar method, and ion implantation for adjusting the channel concentration is performed. After this step, a p-well pws (see FIG. 21 below) is formed in the high-speed nMIS region Rsn by the same method, and ion implantation for channel concentration adjustment is performed. Note that the order of forming the n wells nws and nwv and the p wells pws and pwv is not limited to the above, and may be switched.

  Next, as shown in FIG. 21, a silicon oxide film 5 is formed on the main surface s1 of the silicon substrate 1 by a thermal oxidation method or the like. This silicon oxide film 5 is used as a gate insulating film of a MIS transistor for high withstand voltage by later processing. Therefore, in the subsequent process, the silicon oxide film 5 in the high-speed nMIS region Rsn and the high-speed pMIS region Rsp is removed. First, a photoresist film 6 that opens in both high-speed MIS regions Rsn and Rsp is formed. Subsequently, using the photoresist film 6 as an etching mask, the silicon oxide film 5 in both high-speed MIS regions Rsn and Rsp is removed by etching or the like.

  Next, as shown in FIG. 22, a silicon oxide film 5 is formed again on the main surface s1 of the silicon substrate 1 by a thermal oxidation method or the like. Here, the silicon oxide film 5 has already been formed in both high breakdown voltage MIS regions Rvn and Rvp by the previous process, and the silicon oxide film 5 has been removed in both high speed MIS regions Rsn and Rsp. Therefore, by this step, the silicon oxide film 5 formed in both high breakdown voltage MIS regions Rvn and Rvp becomes thicker than the silicon oxide film 5 formed in both high speed MIS regions Rsn and Rsp. In this step, the silicon oxide film 5 is formed as much as the gate insulating film thickness required for the high-speed MIS transistor. In the process of FIG. 21, the silicon oxide film 5 is formed so that the thickness of the silicon oxide film 5 combined with the process of FIG. 22 becomes the gate insulating film thickness required for the MIS transistor for high voltage application. Form.

  Subsequently, a polycrystalline silicon film 7 is formed by CVD or the like so as to cover the silicon oxide film 5. This polycrystalline silicon film 7 is to be used as a gate electrode of a MIS transistor for peripheral circuits by later processing. Therefore, in the subsequent process, the polycrystalline silicon film 7 in the memory region Rm is removed. First, a photoresist film 8 is formed so as to cover the main surface s1 of each MIS region Rsn, Rsp, Rvn, Rvp of the silicon substrate 1. Then, using the photoresist film 8 as an etching mask, the polycrystalline silicon film 7 in the memory region Rm is etched and removed. Subsequently, using the photoresist film 8 as an etching mask, the silicon oxide film 5 in the memory region Rm is etched and removed.

  Next, as shown in FIG. 23, a lower barrier film bb1, a charge storage film st1, and an upper barrier film bt1 are formed on the entire main surface s1 of the silicon substrate 1. Each is formed in the same manner as the process described in FIG. At this time, in the previous step, the memory region Rm is processed so that the main surface s1 of the silicon substrate 1 is exposed. However, in each MIS region Rsn, Rsp, Rvn, Rvp, the silicon oxide film 5 is used for many. A crystalline silicon film 7 is formed. Accordingly, in this step, the lower barrier film bb1, the charge storage film, on the main surface s1 of the silicon substrate 1 in the memory region Rm, and on the polycrystalline silicon film 7 in each MIS region Rsn, Rsp, Rvn, Rvp. st1 and the upper barrier film bt1 are formed.

  Subsequently, a first conductor film E1 is formed on the entire main surface s1 of the silicon substrate 1 so as to cover the upper barrier film bt1. The first conductor film E1 is formed in the same manner as the process described with reference to FIG.

  As described with reference to FIG. 9 above, the first conductor film E1 formed in this step becomes a memory gate electrode of the nonvolatile memory in a later step. Therefore, in the subsequent process, ion implantation dp04 impurity ions are implanted into the first conductor film E1 to obtain a desired conductivity type. Here, the same ion implantation dp04 is performed on the entire first conductor film E1 without using an ion implantation mask or the like.

  Next, as shown in FIG. 24, the first conductor film E1 is processed in the same manner as in the process of FIG. 10 to form a memory gate electrode (first gate electrode) MG1. Here, a photoresist film 9 patterned so as to cover a portion of the first conductor film E1 that is desired to remain as the memory gate electrode MG1 is formed, and the first conductor film E1 is etched using this as an etching mask. Thereafter, the photoresist film 9 is removed.

  Next, as shown in FIG. 25, the upper barrier film bt1, the charge storage film st1, and the lower barrier film bb1 that are not covered with the memory gate electrode MG1 are removed, whereby the memory made of these insulating films is removed. A gate insulating film (first gate insulating film) MI1 is formed. More specifically, in the insulating film on the silicon substrate 1 in the memory region Rm and on the polycrystalline silicon film 7 in each MIS region Rsn, Rsp, Rvn, Rvp, a portion that is not covered with the memory gate electrode MG1. Is removed by wet etching or the like to form the memory gate insulating film MI1. The aspect of the memory gate insulating film MI1 is the same as that described with reference to FIG. In this step, the first conductor film E1, the upper barrier film bt1, the charge storage film st1, and the lower barrier film bb1 in each MIS region Rsn, Rsp, Rvn, Rvp are also removed. That is, in each MIS region Rsn, Rsp, Rvn, Rvp, the polycrystalline silicon film 7 is exposed.

  Subsequently, different ion implantations dp05 are applied to the polycrystalline silicon film 7 in each of the MIS regions Rsn, Rsp, Rvn, Rvp. As described above, the polycrystalline silicon film 7 serves as a gate electrode of a MIS transistor for peripheral circuit use. In this step, ion implantation dp05 or the like is applied to the polycrystalline silicon film 7 in each region so as to obtain a conductivity type required for the gate electrode of the MIS transistor. For example, the gate electrode of an n-type MIS transistor is n-type conductivity, and the gate electrode of a p-type MIS transistor is p-type conductivity.

  In the figure, for example, a photoresist film 10 having a pattern that opens in the high-speed and high-breakdown-voltage nMIS regions Rsn and Rvn is formed. Then, ion implantation dp05 is performed on the polycrystalline silicon film 7 in the regions Rsn and Rvn using the photoresist film 10 as an ion implantation mask. Here, by implanting n-type impurity ions, the polycrystalline silicon 7 is changed to n-type polycrystalline silicon 7n. In the subsequent process, the polycrystalline silicon film 7 in the high-speed and high-breakdown-voltage pMIS regions Rsp and Rvp is similarly changed to p-type polycrystalline silicon 7p (see FIG. 26 below) by another photoresist film and other ion implantation. . Note that the order of forming these n-type polycrystalline silicon 7n and p-type polycrystalline silicon 7p is not limited to the above, and may be interchanged.

  Next, as shown in FIG. 26, the n-type and p-type polycrystalline silicon films 7n and 7p are processed, and an n-type high-speed gate electrode (second gate electrode) Gn1 and a high-speed pMIS are formed in the high-speed nMIS region Rsn, respectively. The region Rsp is a p-type high-voltage gate electrode (second gate electrode) Gp1, the high-voltage nMIS region Rvn is an n-type high-voltage gate electrode (second gate electrode) Gn2, and the high-voltage pMIS region Rvp is a p-type high-voltage gate. An electrode (second gate electrode) Gp2 is formed. Here, first, a photoresist film 11 patterned so as to cover a portion to be left as each gate electrode of n-type and p-type polycrystalline silicon films 7n and 7p is formed. Then, using this photoresist film 11 as an etching mask, anisotropic etching is performed on the exposed n-type and p-type polycrystalline silicon films 7n and 7p to remove them. Thereafter, the photoresist film 11 is removed.

  Next, as shown in FIG. 27, portions of the silicon oxide film 5 not covered with the gate electrodes Gn1, Gp1, Gn2, Gp2 are removed by wet etching or the like. Thus, the high-speed gate insulating film (second gate insulating film) GI1 made of the silicon oxide film 5 is formed in both the high-speed MIS regions Rsn and Rsp, and the high-voltage MIS regions Rvn and Rvp are formed from the silicon oxide film 5 in both. A high breakdown voltage gate insulating film (second gate insulating film) GI2 is formed.

  Through the above-described steps, in the main surface s1 of the silicon substrate 1, the high-speed nMIS region Rsn is separated from the high-speed gate insulating film GI1 by the n-type high-speed gate electrode Gn1 and the high-speed pMIS region Rsp. The gate insulating film GI1 is separated from the p-type high-speed gate electrode Gp1, and the high-breakdown-voltage nMIS region Rvn is separated from the high-breakdown-voltage gate insulating film GI2 by the n-type high-breakdown-voltage gate electrode Gn2 and high-breakdown-voltage pMIS region Rvp. A p-type high breakdown voltage gate electrode Gp2 is formed across the breakdown voltage gate insulating film GI2.

  In the subsequent process, in the high breakdown voltage nMIS region Rvn, an n-type ion implantation region n2 is formed on the main surface of the silicon substrate 1 on the lower side of the n-type high breakdown voltage gate electrode Gn2. For this, first, a photoresist film 12 having an opening in the high breakdown voltage nMIS region Rvn is formed, and ion implantation dp06 is performed. At this time, in addition to the photoresist film 12, the n-type high breakdown voltage gate electrode Gn2 also functions as an ion implantation mask, and the n-type ion implantation region n2 can be formed in the above region.

  Next, as shown in FIG. 28, a first protective film pt1 is formed so as to cover the main surface s1 of the silicon substrate 1 and each gate electrode. Here, the gate electrodes are the memory gate electrode MG1, the n-type and p-type high-speed gate electrodes Gn1, Gp1, and the n-type and p-type high voltage gate electrodes Gn2, Gp2. In other words, in this step, on the main surface s1 of the silicon substrate 1, the memory gate electrode MG1 and the gate electrodes Gn1, Gp1, Gn2, Gp2 for the MIS transistors in the peripheral region are covered in the same step. First protective film pt1 is formed. Here, the first protective film pt1 is formed in the same manner as described with reference to FIG.

  Subsequently, a photoresist film 13 patterned so as to be opened in the memory region Rm in the main surface s1 of the silicon substrate 1 is formed. Then, by performing ion implantation dp07 using the photoresist film 13 as an ion implantation mask, n-type impurity ions (first impurity ions) are implanted into the main surface s1 of the silicon substrate 1 in the memory region Rm. An ion implantation region n1 is formed.

  Here, the first protective film pt1 is applied and the ion implantation similar to the ion implantation dp01 is performed in the same manner as the manufacturing method of the first embodiment, in particular, the method and its embodiment described with reference to FIG. An n-type ion implantation region n1 is formed by dp07. That is, the n-type ion implantation region n1 and the memory gate electrode MG1 do not have a planar overlapping portion at this point, and are offset by the thickness of the first protective film pt1. The effect is the same as that described in the first embodiment.

  Next, as shown in FIG. 29, the first protective film pt1 is left so as to cover the sidewalls of the gate electrodes Gn1, Gp1, Gn2, and Gp2 for the MIS transistors in the peripheral circuit, and the others are removed by etching. First spacer sp1 is formed. Here, the first protective film pt1 is subjected to so-called etch back in which anisotropic etching is performed without applying an etching mask or the like. As a result, the first protective film pt1 remains on the side wall portions of the gate electrodes Gn1, Gp1, Gn2, Gp2 that are apparently thick when viewed from the main surface s1 of the silicon substrate 1, and the other portions are removed, A first spacer sp1 made of the first protective film pt1 having the above structure can be formed. According to this method, the first spacer sp1 is also formed on the side wall of the memory gate electrode MG1.

  Subsequently, a photoresist 14 having a pattern opening in the high-speed pMIS region Rsp is formed, and ion implantation dp08 is performed using this as an ion implantation mask. Here, p-type ion implantation region p1 is formed by implanting p-type impurity ions (second impurity ions). At this time, in the high-speed pMIS region Rsp, the p-type high-speed gate electrode Gp1 serves as an ion implantation mask, and the ion implantation dp08 is performed on the lower side of the p-type high-speed gate electrode Gp1 in the main surface s1 of the silicon substrate 1. Is done. Further, in the method of the second embodiment, the first spacer sp1 is formed on the side wall of the p-type high speed gate electrode Gp1, which also serves as an ion implantation mask. Therefore, the p-type ion implantation region p1 formed by the ion implantation dp08 does not have a portion overlapping the p-type high-speed gate electrode Gp1 when the main surface s1 of the silicon substrate 1 is viewed in plan, and the first spacer The film is formed at a position (offset position) separated by the thickness of.

  As a comparison, for example, consider the n-type ion implantation region n2 formed in the step of FIG. In the process of FIG. 27, the ion implantation dp06 is performed using only the n-type high breakdown voltage gate electrode Gn2 as the ion implantation mask in the high breakdown voltage nMIS region Rvn without applying the offset spacer such as the first spacer sp1. Therefore, when the ion implantation dp06 is performed, the end portion of the n-type ion implantation region n2 and the side wall of the end portion of the n-type high breakdown voltage gate electrode Gn2 are arranged so as to be at the same position in plan view. . On the other hand, the p-type ion implantation region p1 formed in the high-speed pMIS region Rsp by the ion implantation dp08 subjected to the first spacer sp1 in this step has an offset from the p-type high-speed gate electrode Gp1 as described above. Formed.

  In FIG. 29, before this step, other p-type impurity ions (second impurity ions) are implanted into the lower side portion of the p-type high breakdown voltage gate electrode Gp2 in the same manner as described above. A state in which the p-type ion implantation region p2 is formed is shown. Further, after this step, other n-type impurity ions (second impurity ions) are implanted into the lower side portion of the n-type high-speed gate electrode Gn1 in the same manner as described above, and the ion implantation region n3 (see FIG. 30 below). Reference). Note that the order in which the p-type ion implantation regions p1 and p2 and the n-type ion implantation region n3 are formed is not limited to the above, and may be switched.

  Next, as shown in FIG. 30, the n-type ion implantation region n1 formed in the step of FIG. 28 and the n-type and p-type ion implantation regions formed in the step of FIG. n2, n3, p1, and p2 are diffused and activated. As a result, an n-type memory extension region (first semiconductor region) xn1 is formed in the memory region Rm by the n-type ion implantation region n1. In addition, an n-type high-speed extension region (second semiconductor region) xn2 is formed by the n-type ion implantation region n3 in the high-speed nMIS region Rsn, and a p-type high-speed extension by the p-type ion implantation region p1 is formed in the high-speed pMIS region Rsp. A region (second semiconductor region) xp1 is formed. Further, an n-type high breakdown voltage extension region xn3 is formed by the n-type ion implantation region n2 in the high breakdown voltage nMIS region Rvn, and a p-type high breakdown voltage extension region (by the p-type ion implantation region p2) is formed in the high breakdown voltage pMIS region Rvp. Second semiconductor region xp2 is formed.

  Through the above steps, in the silicon substrate 1, the nonvolatile memory cell NVM, the high-speed nMIS region Rsn, the high-speed n-type MIS transistor (field effect transistor) Qsn, and the high-speed pMIS region Rsp, the high-speed p-type MIS transistor, respectively. (Field effect transistor) The basic configuration of the high breakdown voltage n-type MIS transistor Qvn in the high breakdown voltage nMIS region Rvn, the high breakdown voltage p-type MIS transistor (field effect transistor) Qvp in the high breakdown voltage pMIS region Rvp is formed.

  Here, at the time when the steps of FIG. 28 and FIG. 29 are finished, as described above, there is a planar offset between the n-type ion implantation region n1 and the memory gate electrode MG1 in the memory region Rm. . Similarly, for example, an offset is generated in a plane between the p-type ion implantation region p1 and the p-type high-speed gate electrode Gp1 in the high-speed pMIS region Rsp. Then, by performing the heat treatment step described with reference to FIG. 30, the ion implantation regions n1, n3, p1, and p2 are diffused so as to approach the side walls of the gate electrodes MG1, Gn1, Gp1, and Gp2, and the extension regions are formed. xn1, xn2, xp1, and xp2 are formed.

  On the other hand, in the high breakdown voltage nMIS region Rvn, the n-type ion implantation region n2 is formed so that there is no offset from the n-type high breakdown voltage gate electrode Gn2. Therefore, in this heat treatment step, the n-type ion implantation region n2 is diffused so as to wrap around the lower portion of the n-type high breakdown voltage gate electrode Gn2, and the n-type high breakdown voltage extension region xn3 is formed.

  As a result, for example, compared with the case where the n-type high breakdown voltage extension region xn3 is formed without applying the first protective film pt1 or the first spacer sp1, like the high breakdown voltage nMIS region Rvn, for example, the high-speed pMIS region Rsp As described above, when the p-type high-speed extension region xp1 is formed by applying the first spacer sp1, the planar overlap with the gate electrode becomes smaller.

  In the nonvolatile memory cell NVM, the effect of forming the n-type memory extension region xn1 by applying the first protective film pt1 as described above is as described in the first embodiment.

  On the other hand, as described above, it is also effective to apply the offset spacer (first spacer sp1) also in the process of forming the MIS transistor and reduce the area where the extension region and the gate electrode overlap in a plane. is there. This technique is described in, for example, Japanese Patent Application No. 2008-47400 filed previously by the present applicants.

  Then, according to the manufacturing method of the second embodiment, the effective nonvolatile memory cell NVM described in the first embodiment is shared by using the offset spacer applied to the step of forming the MIS transistor as the peripheral circuit. Can be formed. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved. In addition, the number of processes can be reduced.

  In the manufacturing method of the second embodiment, the first protective film pt1 is applied to the formation of the n-type memory extension region xn1 of the nonvolatile memory cell NVM. In contrast, for example, the first spacer sp1 is applied to form the n-type high-speed extension region xn2 of the high-speed n-type MIS transistor Qsn. Here, since the first spacer sp1 is formed by etching back the first protective film pt1 in the thickness direction of the silicon substrate 1, the thickness seen from the side wall of each gate electrode is not substantially changed.

  However, in the manufacturing method according to the second embodiment, when the first protective film pt1 is etched back, the anisotropic etching conditions are adjusted so that the first protective film pt1 also extends in the direction along the main surface s1 of the silicon substrate 1. It is more preferable to form the first spacer sp1 so as to be slightly etched. Accordingly, the first protective film pt1 used for forming the n-type memory extension region xn1 of the nonvolatile memory cell NVM and the first spacer sp1 used for forming the n-type high-speed extension region xn2 of the high-speed n-type MIS transistor Qsn, for example. And the thickness can be changed. More specifically, the thickness of the first spacer sp1 seen from the side wall of the p-type high speed gate electrode Gp1 can be made thinner than the thickness of the first protective film pt1 seen from the side wall of the memory gate electrode MG1. The reason why such an embodiment is more effective will be described below.

  As described above, the nonvolatile memory cell NVM can function as an n-type MIS transistor. However, the operation is applied, for example, as a memory read operation and is often different from the n-type MIS transistor of the peripheral circuit. Therefore, the required characteristics are different, and the structure as a MIS transistor is also different. That is, it is desirable that the n-type memory extension region xn1 of the nonvolatile memory cell NVM and the n-type high-speed extension region xn2 of the high-speed n-type MIS transistor Qsn can be formed in different shapes by different processes. In particular, the process of applying the offset spacer as in the second embodiment is applied to the process of forming a miniaturized and high-performance MIS transistor. That is, it is more preferable that the n-type high-speed extension region xn2 of the high-speed n-type MIS transistor Qsn can be formed by finer processing than the n-type memory extension region xn1 of the nonvolatile memory cell NVM.

  From this point of view, as described above, the first protective film pt1 is applied to the formation process of the n-type memory extension region xn1, and the first spacer sp1 obtained by thinning the first protective film pt1 by etching is used as the n-type high-speed extension region. By applying to xn2, it becomes easy to form a desired shape. Thus, according to the manufacturing method of the second embodiment, the nonvolatile memory having the effect described in the first embodiment while applying the process of forming a higher performance MIS transistor as a peripheral circuit. A cell NVM can be formed. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  In the process described with reference to FIG. 30, the n-type and p-type ion implantation regions n3, p1, and p2 of the MIS regions Rsn, Rsp, and Rvp are viewed in plan view of the main surface s1 of the silicon substrate 1. More preferably, the extension regions xn2, xp1, and xp2 are formed by performing heat treatment so as to diffuse to the positions reaching the side walls of the gate electrodes Gn1, Gp1, and Gp2, respectively. This is because if the extension region does not reach at least under the gate electrode, the inversion layer of the channel region and the extension region cannot be connected when the MIS transistor is turned on, the resistance value increases, and the current driving force decreases. Therefore, by adjusting the process so that the extension region reaches below the gate electrode, a semiconductor device having the above-described effects can be formed without reducing the current driving force. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In the process described with reference to FIG. 30, it is assumed that the heat treatment for diffusing and activating the plurality of n-type and p-type ion implantation regions n1, n2, n3, p1, and p2 is performed in the same process. did. More specifically, the heat treatment for forming the n-type memory extension region xn1 of the nonvolatile memory cell NVM and the heat treatment for forming, for example, the n-type high-speed extension region xn2 of the high-speed n-type MIS transistor Qsn are the same process. As explained. Here, in order to obtain the above-described effect, it is necessary to perform a heat treatment for diffusing an ion-implanted region formed by ion implantation to a desired range, and the specification is not limited. .

  However, in the manufacturing method of the second embodiment, as described above, a plurality of extensions are obtained by diffusing and activating the plurality of n-type and p-type ion implantation regions n1, n2, n3, p1, and p2, respectively. It is more preferable that the heat treatment for forming the regions xn1, xn3, xn2, xp1, and xp2 is performed in the same process. This is because the heat treatment step can be reduced and the thermal load on other components can be reduced. As a result, the performance of the semiconductor device having a nonvolatile memory can be further improved.

  In the subsequent process, as shown in FIG. 31, the sidewall spacer sw is formed in the same manner as the process described with reference to FIG. Here, the side wall spacer sw having different specifications may be formed in the memory region Rm and the peripheral MIS regions Rsn, Rsp, Rvp. Subsequently, the memory source / drain region sd1, the peripheral n-type source / drain region sd2, and the peripheral p-type source / drain region sd3 are formed in the same manner as described with reference to FIG.

  The semiconductor device having the nonvolatile memory cell NVM can be formed by the manufacturing method of the second embodiment as described above.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied, for example, to the semiconductor industry necessary for performing information processing in personal computers, mobile devices, and the like.

It is principal part sectional drawing of the semiconductor device which this inventor examined. It is a circuit diagram for demonstrating operation | movement of the semiconductor device which this inventor examined. It is explanatory drawing for demonstrating the operation | movement shown in FIG. 2, and its one part enlarged view. It is a circuit diagram for demonstrating other operation | movement of the semiconductor device which this inventor examined. It is explanatory drawing for demonstrating the operation | movement shown in FIG. 4, and its one part enlarged view. It is a circuit diagram for demonstrating other operation | movement of the semiconductor device which this inventor examined. It is explanatory drawing for demonstrating the operation | movement shown in FIG. It is principal part sectional drawing of the semiconductor device which is Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; 12 is a partial enlarged view of a cross-sectional view of the main part in the manufacturing process of the semiconductor device shown in FIG. FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; It is a graph which shows the characteristic of the semiconductor device which is Embodiment 1 of this invention. FIG. 6 is a circuit diagram for explaining an operation of the semiconductor device according to the first embodiment of the present invention. It is explanatory drawing for demonstrating the operation | movement shown in FIG. It is a graph which shows the characteristic of the semiconductor device which performed the operation | movement shown in FIG. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30;

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Separating part 3, 4, 6, 8-14 Photoresist film 5 Silicon oxide film 7 Polycrystalline silicon film bb1 Lower barrier film bt1 Upper barrier film c01-c05 Cell region DL Data line dp01-dp08 Ion implantation e Electron E1 1st Conductor film GI1 High-speed gate insulating film (second gate insulating film)
GI2 High voltage gate insulating film (second gate insulating film)
Gn1 n-type high-speed gate electrode (second gate electrode)
Gn2 n-type high breakdown voltage gate electrode (second gate electrode)
Gp1 p-type high-speed gate electrode (second gate electrode)
Gp2 p-type high breakdown voltage gate electrode (second gate electrode)
h Hole
MG1 Memory gate electrode (first gate electrode)
MI1 memory gate insulating film (first gate insulating film)
n1, n2, n3 n-type ion implantation region nw1 separation n-well nws, nwv n-well NVM nonvolatile memory cell p1, p2 p-type ion implantation region pt1 first protective film pw1 p-well for device pws, pwv p-well Qsn high speed n-type MIS transistor (field effect transistor)
Qsp high-speed p-type MIS transistor (field effect transistor)
Qvn high voltage n-type MIS transistor Qvp high voltage p-type MIS transistor (field effect transistor)
r01-r03 Characteristics Rm Memory region Rsn High speed nMIS region Rsp High speed pMIS region Rvn High breakdown voltage nMIS region Rvp High breakdown voltage pMIS region s1 Main surface sd1 Memory source / drain region sd2 Peripheral n-type source / drain region sd3 Peripheral p-type source / drain region SL source line sp1 first spacer st1 charge storage film sw sidewall spacer Vd drain voltage Vg gate voltage Vs source voltage Vsub substrate voltage Vth threshold voltage WL word line xn1 n-type memory extension region (first semiconductor region)
xn2 n-type high-speed extension region (second semiconductor region)
xn3 n-type high breakdown voltage extension region xp1 p-type high-speed extension region (second semiconductor region)
xp2 p-type high breakdown voltage extension region (second semiconductor region)

Claims (12)

A method of manufacturing a semiconductor device including a step of forming a plurality of nonvolatile memory cells on a main surface of a semiconductor substrate,
The step of forming the nonvolatile memory cell includes:
(A) forming a first gate electrode on the main surface of the semiconductor substrate across a first gate insulating film;
(B) forming a first protective film so as to cover the main surface of the semiconductor substrate and the first gate electrode;
(C) implanting impurity ions into a region below a side of the first gate electrode in the main surface of the semiconductor substrate;
(D) diffusing and activating the impurity ions by heat treatment to form a first semiconductor region,
In the step (a), the first gate insulating film having a function of accumulating charges is formed,
In the step (b), the first protective film is formed so as to have a shape having a surface along the side wall of the first gate electrode.
In the step (c), the impurity ions are implanted by performing ion implantation on the semiconductor substrate using the first protective film that covers the first gate electrode and the sidewall thereof as an ion implantation mask.
In the step (c), the impurity ions are implanted into a position separated from the side wall of the first gate electrode by the thickness of the first protective film when the main surface of the semiconductor substrate is viewed in plan. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), the first protective film having a thickness of 10 to 20 nm is formed. The method of manufacturing a semiconductor device according to claim 2.
In the step (b), an insulating film mainly comprising silicon oxide is formed as the first protective film. In the manufacturing method of the semiconductor device according to claim 3,
In the step (d), the impurity ions implanted into the semiconductor substrate in the step (c) are diffused to a position reaching the side wall of the first gate electrode when the main surface of the semiconductor substrate is viewed in a plan view. In this way, the heat treatment is performed to form the first semiconductor region. In the manufacturing method of the semiconductor device according to claim 4,
In the step (a), as the first gate insulating film having a function of storing charges, a lower barrier film, a charge storage film, and an upper barrier film are formed in order from the side closer to the semiconductor substrate,
A method of manufacturing a semiconductor device, wherein an insulating film mainly composed of silicon oxide is formed as the lower and upper barrier films. A method for manufacturing a semiconductor device comprising a step of forming a plurality of nonvolatile memory cells and a plurality of field effect transistors in different regions of a main surface of a semiconductor substrate,
The step of forming the nonvolatile memory cell includes:
(A) forming a first gate electrode on the main surface of the semiconductor substrate across a first gate insulating film;
(B) forming a first protective film so as to cover the main surface of the semiconductor substrate and the first gate electrode;
(C) implanting first impurity ions into a region below the side surface of the first gate electrode in the main surface of the semiconductor substrate;
(D) diffusing and activating the first impurity ions by heat treatment to form a first semiconductor region,
In the step (a), the first gate insulating film having a function of accumulating charges is formed,
In the step (b), the first protective film is formed so as to have a shape having a surface along the side wall of the first gate electrode.
In the step (c), the first impurity ions are implanted by ion-implanting the semiconductor substrate using the first protective film covering the first gate electrode and the side wall thereof as an ion implantation mask.
In the step (c), when the main surface of the semiconductor substrate is viewed in plan, the first impurity ions are located at a position away from the side wall of the first gate electrode by the thickness of the first protective film. Inject and
The step of forming the field effect transistor comprises:
(E) forming a second gate electrode on the main surface of the semiconductor substrate across a second gate insulating film;
(F) forming the first protective film so as to cover the main surface of the semiconductor substrate and the second gate electrode;
(G) forming the first spacer by leaving the first protective film so as to cover the sidewall of the second gate electrode and removing the other by etching;
(H) implanting second impurity ions into a region below a side of the second gate electrode in the main surface of the semiconductor substrate;
(I) forming a second semiconductor region by diffusing and activating the second impurity ions by heat treatment;
In the step (h), the second impurity ions are implanted by performing ion implantation on the semiconductor substrate using the second gate electrode and the first spacer as an ion implantation mask.
In the step (h), when the main surface of the semiconductor substrate is viewed in a plan view, the second impurity ions are placed at a position away from the side wall of the second gate electrode by the thickness of the first spacer. Inject,
In the step (b) and the step (f), the first protective film is formed by the same step,
The method of manufacturing a semiconductor device, wherein the step (c) is performed before the step (g). The method of manufacturing a semiconductor device according to claim 6.
In the step (g), the thickness of the first spacer viewed from the side wall of the second gate electrode is the first thickness when the first protective film is formed in the steps (b) and (f). A method of manufacturing a semiconductor device, wherein the etching is performed so as to be thinner than a thickness seen from a side wall of the gate electrode. The method of manufacturing a semiconductor device according to claim 7.
In the steps (b) and (f), an insulating film mainly composed of silicon oxide is formed as the first protective film. The method of manufacturing a semiconductor device according to claim 8.
In the step (d), until the first impurity ions implanted into the semiconductor substrate in the step (c) reach the side wall of the first gate electrode when the main surface of the semiconductor substrate is viewed in a plan view. A method of manufacturing a semiconductor device, wherein the first semiconductor region is formed by performing the heat treatment so as to diffuse. In the manufacturing method of the semiconductor device according to claim 9,
In the step (i), the position where the second impurity ions implanted into the semiconductor substrate in the step (h) reach at least the side wall of the second gate electrode when the main surface of the semiconductor substrate is viewed in a plan view. The method of manufacturing a semiconductor device, wherein the second semiconductor region is formed by performing the heat treatment so as to diffuse. The method of manufacturing a semiconductor device according to claim 10.
In the step (d) and the step (i), the heat treatment is performed in the same step. The method of manufacturing a semiconductor device according to claim 11.
In the step (a), as the first gate insulating film having a function of storing charges, a lower barrier film, a charge storage film, and an upper barrier film are formed in order from the side closer to the semiconductor substrate,
A method of manufacturing a semiconductor device, wherein an insulating film mainly composed of silicon oxide is formed as the lower and upper barrier films.

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