KR20100079188A - Circuit for delay locked loop - Google Patents

Circuit for delay locked loop Download PDF

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Publication number
KR20100079188A
KR20100079188A KR1020080137604A KR20080137604A KR20100079188A KR 20100079188 A KR20100079188 A KR 20100079188A KR 1020080137604 A KR1020080137604 A KR 1020080137604A KR 20080137604 A KR20080137604 A KR 20080137604A KR 20100079188 A KR20100079188 A KR 20100079188A
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South Korea
Prior art keywords
output
signal
delay
harmonic
input clock
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KR1020080137604A
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Korean (ko)
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김정민
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주식회사 동부하이텍
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Priority to KR1020080137604A priority Critical patent/KR20100079188A/en
Publication of KR20100079188A publication Critical patent/KR20100079188A/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: A circuit for a delay locked loop is provided to verify the state of a normal operation by continuously comparing the edges of an input clock and a delayed feedback clock. CONSTITUTION: A harmonic lock detector(300) continuously generates up signal or down signal by detecting the generation of abnormal states. The harmonic lock detector includes an up signal generator(310) and a down signal generator. The up signal generator includes a flip-flop unit and a first logical operation unit. The down signal generator includes a part of flip-flops, inverters, NAND-gates, and NOR gates.

Description

Delay locked loop circuit {Circuit for Delay Locked Loop}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a delay locked loop (DLL) circuit.

Currently, the design purpose of DLL is to increase the display speed of the display device and increase the speed of the high speed serial interface without the memory device being used for the display driver IC (DDI). Low Voltage Differential Signal) interface, which usually contains a DLL.

     In general, a function of a delay locked loop (DLL) is a circuit existing to prevent abnormal locking due to a delay change of a voltage controlled delayed line (VCDL).

The harmonic lock detector depends a lot on the characteristics of the phase detector. Different phase detectors require different harmonic lock detectors, but the general detection concept is the same.

Because DLL is mainly used for receiver of high speed serial interface, many functions of harmonic lock detector are added to cope with various kinds of clock and data format. have. A typical phase detector does not take into account clock duty ratios, only a typical harmonic lock.

The operating spec of the DLL is determined by the input clock specification of the LVDS. The duty ratio specification of the clock of the LVDS is different for each TCON. For example, if the high section is 57.14% in one period, the low section is 42.86%. Alternatively, if the high section is 42.86% in one period, the low section is 57.14%. Since the clock is not applied while the 50%: 50% duty ratio is maintained, the locking of the DLL is required regardless of the position of the falling edge of the clock.

1 shows a schematic diagram of a general phase detector, and FIGS. 2A and 2B show an abnormal harmonic state of the phase detector in FIG. 1. 1, 2A, and 2B, RCLK is an input clock, and FCLK is a clock coming from the 14th delay stage DA14 of the VCDL. RCLK_B and FCLK_B are inverted signals. The rising edges of RCLK and FCLK are compared to generate an UP signal or a down signal DN based thereon.

Abnormal operation causes the bias voltage of the VCDL to remain unchanged. In detail, FIG. 2A illustrates a phenomenon in which the UPB and the DNB are the same, and FIG. 2B illustrates a phenomenon in which the UPB and the DNB are not generated.

An object of the present invention is to provide a DLL circuit that can be locked regardless of the position of the poly edge, and can cope with various clock formats.

According to an embodiment of the present invention, a DLL circuit includes a phase detector for comparing an rising edge of an input clock and a feedback clock delayed by the input clock and generating an up signal or a down signal based on a result of the comparison. And a corresponding one of the input clock and the feedback clock in response to any one of an input clock, an inverted input clock in which the input clock is inverted, the feedback clock, and an inverted feedback clock in which the feedback clock is inverted. A flip-flop unit, and a logic operation unit for outputting the harmonic up signal and harmonic down signal by performing a logic operation on the input clock and feedback clock output from the flip-flop unit, and the up signal and the down signal output from the phase detector.

DLL circuit according to an embodiment of the present invention can be locked (lock) regardless of the position of the poly edge, there is an effect that can correspond to various clock formats.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

3A and 3B illustrate a harmonic lock detector 300 according to an embodiment of the present invention. 3A and 3B, the harmonic lock detector 300 continuously compares the edges of the input clock RCLK and the delayed feedback clock FCLK to determine whether normal operation is performed.

The harmonic lock detector 300 detects an abnormal case as shown in FIGS. 2A and 2B and continuously generates an up signal UP or a down signal DN, thereby leaving the harmonic state.

The harmonic lock detector 300 includes an up signal generator 310 and a down signal generator 360.

The up signal generator 310 includes a flip-flop unit and a first logic operator.

The flip-flop portion includes first to fourth flip flops 312 to 318. The first to fourth flip flops 312 to 318 may receive an input clock RCLK in response to any one of an input clock RCLK, an inverted input clock RCLKB, a feedback clock FCLK, and an inverted feedback clock FCLKB. And a corresponding one of the feedback clocks. The first to fourth flip flops 312 to 318 may be D flip flops.

For example, the first flip flop 312 outputs a feedback clock FCLK to the first output Q1 in response to the input clock RCLK. The second flip flop 314 outputs the input clock FCLK to the second output Q2 in response to the feedback clock RCLK. The third flip flop 316 outputs a feedback clock FCLK to the third output Q3 in response to the inverted input clock RCLKB. The fourth flip flop 318 outputs the input clock RCLK to the fourth output Q4 in response to the inverted feedback clock RCLKB.

The first logical operation unit performs a logical operation on the first output Q1, the second output Q2, the third output Q3, the fourth output Q4, and the up signal UPB. The harmonic up signal HUP is output based on the result.

The first logic operation unit may include first to fourth inverters 322 to 328, first to fifth Noah gates 332, 334, 342, 344 and 348, first and second exclusive Noah gates 336 and 338, and first NAND gate 344. ).

Each of the first to fourth inverters 322 to 328 inverts a corresponding one of the first to fourth outputs Q1 to Q4. For example, a first inverter 322 inverts the first output Q1, a second inverter 324 inverts the second output Q2, and a first inverter 326 converts the third output ( Invert Q3), and the fourth inverter 328 inverts the fourth output Q4.

 The first NOR gate 332 performs a logic operation on the outputs of the first inverter 322 and the second inverter 324. The second NOR gate 334 performs a logic operation on the outputs of the third inverter 326 and the fourth inverter 328.

The fifth inverter 340 inverts the output of the first NOR gate 332. The sixth inverter 341 inverts the output of the second NOR gate 334.

The first exclusive NOR gate 336 logically operates the first output Q1 and the second output Q2. The second exclusive NOR gate 338 logically operates the third output Q3 and the fourth output Q4.

The third NOR gate 342 logically operates an output of the fifth inverter 340 and an output of the first exclusive NOR gate 336. The fourth NOR gate 344 performs a logic operation on the output of the sixth inverter 341 and the output of the second exclusive NOR gate 338.

The first NAND gate 344 logically operates the third NOR gate 342 and the fourth NOR gate 344. The seventh inverter 346 inverts the output of the first NAND gate 344. The fifth NOR gate 348 performs a logic operation on the output of the first signal UBP and the seventh inverter 346, and generates the up signal UP based on a result of the logic operation.

The down signal generator 360 may include fifth to eighth flip flops 362 to 368, eighth to sixteenth inverters 372 to 378, 381, 383, 385, 387, and 395, and second to sixth NAND gates 382, 384, 392, 394, and 396. , Third and fourth exclusive Noah gates 386 and 388, and sixth Noah gate 391.

The fifth to eighth flip flops 362 to 368 perform the same operations as the first to fourth flip flops described above, and output the fifth to eighth outputs Q5 to Q8.

Each of the eighth to eleventh inverters 372 to 378 inverts a corresponding one of the fifth to eighth outputs.

The second NAND gate 382 logically operates the outputs of the eighth and ninth inverters 372 and 374. The third NAND gate 384 logically operates the outputs of the tenth and eleventh inverters 376 and 378.

The third exclusive NOR gate 386 logically operates the fifth and sixth outputs Q5 and Q6. The fourth exclusive NOR gate 388 logically operates the seventh and eighth outputs Q7 and Q8.

The twelfth to fifteenth inverters 381, 383, 385, and 387 may include the second NAND gate 382, the third exclusive NOR gate 386, the third NAND gate 384, and the fourth exclusive NOR gate 388. Inverts the output of any of the corresponding outputs. For example, the twelfth inverter 381 inverts the output of the second NAND gate 382, the thirteenth inverter 383 inverts the output of the third exclusive NOR gate 386, and the fourteenth inverter 383. The inverter 385 inverts the output of the third NAND gate 384, and the fifteenth inverter 387 inverts the output of the fourth exclusive NOR gate 388.

The fourth NAND gate 392 logically operates on the output of the twelfth inverter 381 and the output of the thirteenth inverter 383, and the fifth NAND gate 394 is used to output the output of the fourteenth inverter 385. The output of the fifteenth inverter 387 is logically operated.

The sixth NOR gate 391 logically operates an output of the fourth NAND gate 392 and an output of the fifth NAND gate 394. The sixteenth inverter 395 inverts the output of the sixth NOR gate 391.

The sixth NAND gate 396 performs a logical operation on the output of the second signal DNB and the sixteenth inverter 395, and generates the down signal DN based on a result of the logical operation.

4 illustrates a voltage controlled delay line 400 for generating a feedback clock for an input clock. Referring to FIG. 4, the voltage control delay line 400 delays the input clock RCLK to output delay signals DA1 to DA14 having different phases. One of the delay signals DA1 to DA14 may be the feedback clock FCLK.

The voltage controlled delay line 400 includes a plurality of delay cell blocks 401 to 414 connected in series, and each of the plurality of delay cell blocks 401 to 414 delays a phase of an input clock. Therefore, each of the plurality of delay cell blocks 401 to 414 outputs delay signals DA1 to DA14 having different phases. The delay signals DA1 to DA14 are signals in which the input clock RCLK is phase delayed.

FIG. 5 is a circuit diagram of a unit delay cell block shown in FIG. 4. Referring to FIG. 5, the input clock RCLK is input to the input terminal N1, and the first delay signal DA1 is output through the output terminal N2 by the operation of the delay cell block. The first delay signal is input to the delay cell block 402 of the next stage.

FIG. 6 illustrates waveforms of the fourteenth delay signal DA14 of the fourteenth delay cell block 414 illustrated in FIG. 4. As illustrated in FIG. 6, the waveform of the fourteenth delay signal DA14 may change due to an operation characteristic of the delay cell block. So, in general, the phase comparison is performed only on the rising edge.

7 is a conceptual diagram illustrating a harmonic lock detection scheme according to an embodiment of the present invention.

The meaning shown in FIG. 7 is indicated for generalization because a detection edge must be taken separately according to the case where the difference in specifications of the duty ratio is the greatest.

An edge is selected to detect the harmonic up signal HUP. If N is determined instead of an integer, the edge for detecting the harmonic up signal HUP is an integer closest to N, and an integer greater than N may be selected. The integer is equal to the value of the edge.

The harmonic up HUP is not generated when all edges smaller than the point detected by N_I are high, and HUP is generated when any one of edges less than or equal to N_I is detected as low.

Considering four cases when selecting an edge below N_I, it should be limited to occur only when the actual harmonic up signal (HUP) should be generated.

In the case of the harmonic down signal HDN, when N is determined, N_I closest to N is determined in a spec when N is largest. N_I is an integer. The harmonic down signal (HDN) is opposite to the harmony up signal (HUP). If the harmonic down signal (HDN) is generated only when all of N_I or less are high, and there is a signal falling low among the edges of N_I or less, then the harmonic down signal (HDN) HDN) does not occur.

8 illustrates a harmonic lock detector 800 according to an embodiment of the present invention. Referring to FIG. 8, the harmonic lock detector 800 includes a delay prevention unit 810 and a harmonic signal generator 820.

The delay prevention unit 810 prevents the frequency of the feedback signal FCLK from being delayed twice. That is, when the frequency of the feedback signal FCLK is doubled, the harmonic up signal HUP is unconditionally generated.

The delay preventing unit 810 includes a ninth flip flop 812, a tenth flip flop 814, and a seventh noah gate 816. The ninth flip-flop 812 outputs the first power voltage VDD to the ninth output Q9 in response to the third delay signal DA03, which is an output of the third delay cell block 403. The tenth flip-flop 814 receives the ninth output Q9 as an input and outputs the ninth output Q9 to the tenth output Q10 in response to the third delay signal DA03. The ninth flip flop 812 and the tenth flip flop 814 are reset based on a fourteenth delay signal DA14.

The seventh NOR gate 816 performs a logic operation on the tenth output Q10 and the first harmonic control signal HUP_N1 and outputs a second harmonic control signal HUP_N2 based on the logical operation result.

The harmonic signal generator 820 includes eleventh flip flops to eighteen flip flops 821 to 828, seventeenth to twentieth inverters 832, 833, 834, 859, seventh to twelfth NAND gates 842 to 844, 856, 858, 862, Seventh to twelfth Noah gates 852, 854, 872, 882, 884, 886, a first inverter chain 864, and a second inverter chain 874.

Each of the eleventh flip flops to 18 flip flops 821 to 828 includes a second delay signal DA02, a third delay signal DA03, an inverted third delay signal DA03B, a fourth delay signal DA04, An eleventh through eighteenth output of the input clock RCLK in response to any one of the eighth delay signal DA08, the tenth delay signal DA10, the eleventh delay signal DA11, and the twelfth delay signal. Output to any one of (Q11-Q18).

For example, the eleventh flip-flop 821 outputs the input clock RCLK to the eleventh output Q11 in response to the second delay signal DA02. The remaining flip flops may perform an operation as shown in FIG. 8. In this case, the eleventh flip flops to 18 flip flops 821 to 828 are reset by an inversion reset signal.

A seventeenth inverter 832 inverts the thirteenth output Q13. An eighteenth inverter 833 inverts the sixteenth output Q16. The nineteenth inverter 834 inverts the seventeenth output Q17.

The seventh NAND gate 842 logically operates on the eleventh output Q11 and the twelfth output Q12. The eighth NAND gate 843 performs a logic operation on the output of the seventeenth inverter 832 and the fourteenth output Q14.

The seventh NOR gate 852 performs a logical operation on the output of the seventh NAND gate 842 and the output of the eighth NAND gate 843, and outputs a third harmonic control signal HUP_IN3 based on a result of the logical operation. .

The twelfth NAND gate 862 logically operates the second harmonic control signal HUP_IN2 and the third harmonic control signal HUP_IN3.

The first inverter chain 864 is connected to three inverters in series, the output of the twelfth NAND gate 862 is input to the first inverter chain 864, the first inverter chain 864 is Outputs the harmonic up signal HUP.

The ninth Nad gate 844 logically operates on the fourteenth output Q14 and the fifteenth output Q15. The eighth NOR gate 854 logically operates an output of the inverted harmonic up signal HUPB and the ninth Nad gate 844. The tenth NAND gate 856 logically operates the harmonic up signal HUP and the sixteenth output Q16. The twentieth inverter 859 inverts the output of the eighth NOR gate 854.

The ninth NOR gate 872 logically operates the output of the twentieth inverter 859 and the output of the tenth NAND gate 856. In the second inverter chain 874, two inverters are connected in series, and receive an output of the ninth NOR gate 872 to output a harmonic down signal HDN.

The eleventh NAND gate 858 logically operates the eighteenth inverter 833 and the nineteenth inverter 834. The tenth NOR gate 882 logically operates on the output of the eleventh NAND gate and the eighteenth output Q18. The eleventh NOR gate 884 performs a logical operation on the output of the ninth Nad gate 844 and the output of the eighteenth inverter 833.

The twelfth NOR gate 886 performs a logic operation on the output of the tenth Noah gate 882 and the output of the eleventh Noah gate 884, and based on a result of the logic operation, the first harmonic control signal HUP_IN1. Outputs

When N is the smallest, it is 21.42% and it is 3 in the edge. And when N is the largest, 78.57% and 11 is the edge.

Therefore, the harmonic up edge (HUP) is set to 4 and the harmonic down edge (HDN) is set to 10. In addition, the frequency of the feedback signal FCLK is set so as not to be delayed by 2 times. When the frequency of the feedback signal FCLK is delayed by 2 times, the delay prevention unit 810 shown in FIG. 8 generates the harmonic up signal HUP. Do not cause it to be delayed unconditionally.

9A and 9B show a harmonic detection scheme of the harmonic detector shown in FIG. 9A and 9B, when the second delayed signal DA02, the third delayed signal DA03, and the fourth delayed signal DA04 are all high, the harmonic up signal HUP is not generated. . On the other hand, if any one of the second delay signal DA02, the third delay signal DA03, and the fourth delay signal DA04 is LOW, the harmonic up signal is generated.

In addition, when the fourth delay signal DA04, the eighth delay signal DA08, and the tenth delay signal DA10 are all high, a harmonic down signal is generated. However, if any one of the fourth delay signal DA04, the eighth delay signal DA08, and the tenth delay signal DA10 is low, the harmonic down signal is not generated.

In another embodiment, a delay locked loop (DLL) circuit compares an rising edge of an input clock RCLK and a feedback clock FCLK in which the input clock RCLK is delayed, and based on a result of the comparison, an up signal UPB. Or a phase detector for generating a down signal DNB, an input clock RCLK, and a feedback clock FCLK, and an input clock RCLK, an inverted input clock RCLKB in which the input clock is inverted, and the feedback clock. A flip-flop unit 312 which outputs a corresponding one of the received input clock RCLK and the feedback clock FCLK in response to any one of FCLK and an inverted feedback clock FCLKB in which the feedback clock is inverted. 318, 362 to 368, and an input clock RCLK and a feedback clock FCLK output from the flip-flop units 312 to 318, 362 to 368, an up signal UPB output from the phase detector, and Logic operation of down signal (DNB) (HUP) and a logical operation unit for outputting a harmonic-down signal (HDN).

The flip-flop unit may include a first flip-flop 312 that outputs a feedback clock FCLK to a first output Q1 in response to an input clock RCLK, and the input clock (FCLK) in response to the feedback clock FCLK. A second flip flop 314 for outputting RCLK to a second output Q2 and a third flip for outputting the feedback clock FCLK to a third output Q3 in response to the inverted input clock RCLKB. And a fourth flip flop 318 for outputting the input clock RCLK to a fourth output Q4 in response to the flop 316 and the inverted feedback clock FCLKB. Logic operation is performed on the first output Q1, the second output Q2, the third output Q3, the fourth output Q4, and the up signal UPB, and the harmonic up signal is based on the logical operation result. Outputs (HUP).

The logical operation unit performs a logical operation on the first output Q1, the second output Q2, the third output Q3, the fourth output Q4, and the down signal DNB, and performs a logical operation on the result. And outputs the harmonic down signal HDN.

A delay locked loop (DLL) circuit according to another embodiment of the present invention receives an input clock RCLK, delays the received input signal RCLK, and provides a plurality of delay signals DA01 to DA14 having different phases. A delay unit 400 for outputting the delay signal 400 and receiving the input clock RCLK and delay signals DA02, DA03, DA04, DA08, DA10, and DA1 selected from the plurality of delay signals DA1 to DA14. In response to DA12, the flip-flop units 821 to 828 for outputting the received input clock RCLK and the outputs Q11 to Q18 of the flip-flop units 821 to 828 are logically operated. A first logic operation unit outputting a first harmonic control signal HUP_IN1 based on a result, delay signals DA03 and DA14 of the second group selected from the plurality of delay signals DA01 to DA14, and the first harmony Logic operation of the control signal HUP_IN1, and the second harmonic control based on the logical operation result A second logical operation unit outputting an arc HUP_IN2, outputs Q11 to Q18 of the flip-flop units 821 to 828, and the second harmonic control signal HUP_IN2 based on a logical operation and a logical operation result By performing a logic operation on the outputs of the third logic operation unit and the flip-flop unit and outputting the harmonic up signal HUP, and the harmonic up signal HUP, and outputting the harmonic down signal HDN based on the logical operation result. And a fourth logical operation unit.

The delay unit 400 outputs the first to fourteenth delay signals DA01 to DA14 whose phase increases or decreases constantly, and the delay signals of the first group include the second delay signal DA02 and the third. Delay signal DA03, fourth delay signal DA04, eighth delay signal DA08, tenth delay signal DA10, eleventh delay signal DA11, twelfth delay signal DA12, and inverted th The third signal DA03B and the second group of delay signals include a third delay signal DA03.

The DLL including the harmonic lock detector according to an embodiment of the present invention can cope with various clock formats and implement a duty free DLL.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows a block diagram of a general phase detector.

2A and 2B show an abnormal harmonic state of the phase detector in FIG. 1.

3A and 3B illustrate a harmonic lock detector according to an embodiment of the present invention.

4 shows a voltage controlled delay line that generates a feedback clock for the input clock.

FIG. 5 is a circuit diagram of a unit delay cell block shown in FIG. 4.

6 illustrates waveforms of a fourteenth delay signal of the fourteenth delay cell block illustrated in FIG. 4.

7 is a conceptual diagram illustrating a harmonic lock detection scheme according to an embodiment of the present invention.

8 illustrates a harmonic lock detector according to an embodiment of the present invention.

9A and 9B show a harmonic detection scheme of the harmonic detector shown in FIG.

Claims (5)

A phase detector for comparing an rising edge of an input clock and a feedback clock delayed by the input clock and generating an up signal or a down signal based on a result of the comparison; And A flip-flop that outputs a corresponding one of the input clock and the feedback clock in response to any one of an input clock, an inverted input clock in which the input clock is inverted, the feedback clock, and an inverted feedback clock in which the feedback clock is inverted part; And Delay Locked Loop (DLL) including a logic operation unit outputting a harmonic up signal and a harmonic down signal by performing a logic operation on an input clock and a feedback clock output from the flip-flop unit, and an up signal and a down signal output from the phase detector. Circuit. The method of claim 1, The flip flop portion, A first flip flop that outputs a feedback clock to a first output in response to an input clock RCLK; A second flip flop that outputs the input clock to a second output in response to the feedback clock; A third flip flop that outputs the feedback clock to a third output in response to the inverted input clock; And A fourth flip flop that outputs the input clock to a fourth output in response to the inverted feedback clock; The logical operation unit, A delay-locked loop (DLL), wherein the first output, the second output, the third output, the fourth output, and the up signal are logically operated, and the harmonic up signal is output based on a result of the logical operation. Circuit. The method of claim 2, wherein the logical operation unit, A delay locked loop (DLL), wherein the first output, the second output, the third output, the fourth output, and the down signal are logically operated, and the harmonic down signal is output based on a result of the logical operation. Circuit. A delay unit for receiving an input clock and delaying the received input signal to output a plurality of delay signals having different phases; A flip-flop unit which receives the input clock and outputs the received input clock in response to delay signals of a first group selected from the plurality of delay signals; A first logic calculator configured to logically output the flip-flop units and to output a first harmonic control signal based on a logically calculated result; A second logic operation unit configured to perform a logic operation on the selected second group of delay signals and the first harmony control signal among the plurality of delay signals, and output a second harmonic control signal based on a result of the logic operation; A third logic operation unit configured to perform a logic operation on the outputs of the flip flop unit and the second harmonic control signal and output a harmonic up signal based on a result of the logic operation; And And a fourth logic operation unit configured to perform a logic operation on the outputs of the flip flop unit and the harmonic up signal, and output a harmonic down signal based on a result of the logic operation. The method of claim 4, wherein The delay unit, Outputting first to fourteenth delayed signals whose phase increases or decreases constantly; The delay signals of the first group are a second delay signal, a third delay signal, a fourth delay signal, an eighth delay signal, a tenth delay signal, an eleventh delay signal, a twelfth delay signal, and an inverted third signal. , And delay delay signals of the second group include a third delay signal.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347762A (en) * 2010-07-30 2012-02-08 三星半导体(中国)研究开发有限公司 Locking detection circuit of phase-locked loop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347762A (en) * 2010-07-30 2012-02-08 三星半导体(中国)研究开发有限公司 Locking detection circuit of phase-locked loop circuit

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