KR20100079188A - Circuit for delay locked loop - Google Patents
Circuit for delay locked loop Download PDFInfo
- Publication number
- KR20100079188A KR20100079188A KR1020080137604A KR20080137604A KR20100079188A KR 20100079188 A KR20100079188 A KR 20100079188A KR 1020080137604 A KR1020080137604 A KR 1020080137604A KR 20080137604 A KR20080137604 A KR 20080137604A KR 20100079188 A KR20100079188 A KR 20100079188A
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- KR
- South Korea
- Prior art keywords
- output
- signal
- delay
- harmonic
- input clock
- Prior art date
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- 230000003111 delayed effect Effects 0.000 claims abstract description 15
- 230000000630 rising effect Effects 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000001514 detection method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001934 delay Effects 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 101001062854 Rattus norvegicus Fatty acid-binding protein 5 Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a delay locked loop (DLL) circuit.
Currently, the design purpose of DLL is to increase the display speed of the display device and increase the speed of the high speed serial interface without the memory device being used for the display driver IC (DDI). Low Voltage Differential Signal) interface, which usually contains a DLL.
In general, a function of a delay locked loop (DLL) is a circuit existing to prevent abnormal locking due to a delay change of a voltage controlled delayed line (VCDL).
The harmonic lock detector depends a lot on the characteristics of the phase detector. Different phase detectors require different harmonic lock detectors, but the general detection concept is the same.
Because DLL is mainly used for receiver of high speed serial interface, many functions of harmonic lock detector are added to cope with various kinds of clock and data format. have. A typical phase detector does not take into account clock duty ratios, only a typical harmonic lock.
The operating spec of the DLL is determined by the input clock specification of the LVDS. The duty ratio specification of the clock of the LVDS is different for each TCON. For example, if the high section is 57.14% in one period, the low section is 42.86%. Alternatively, if the high section is 42.86% in one period, the low section is 57.14%. Since the clock is not applied while the 50%: 50% duty ratio is maintained, the locking of the DLL is required regardless of the position of the falling edge of the clock.
1 shows a schematic diagram of a general phase detector, and FIGS. 2A and 2B show an abnormal harmonic state of the phase detector in FIG. 1. 1, 2A, and 2B, RCLK is an input clock, and FCLK is a clock coming from the 14th delay stage DA14 of the VCDL. RCLK_B and FCLK_B are inverted signals. The rising edges of RCLK and FCLK are compared to generate an UP signal or a down signal DN based thereon.
Abnormal operation causes the bias voltage of the VCDL to remain unchanged. In detail, FIG. 2A illustrates a phenomenon in which the UPB and the DNB are the same, and FIG. 2B illustrates a phenomenon in which the UPB and the DNB are not generated.
An object of the present invention is to provide a DLL circuit that can be locked regardless of the position of the poly edge, and can cope with various clock formats.
According to an embodiment of the present invention, a DLL circuit includes a phase detector for comparing an rising edge of an input clock and a feedback clock delayed by the input clock and generating an up signal or a down signal based on a result of the comparison. And a corresponding one of the input clock and the feedback clock in response to any one of an input clock, an inverted input clock in which the input clock is inverted, the feedback clock, and an inverted feedback clock in which the feedback clock is inverted. A flip-flop unit, and a logic operation unit for outputting the harmonic up signal and harmonic down signal by performing a logic operation on the input clock and feedback clock output from the flip-flop unit, and the up signal and the down signal output from the phase detector.
DLL circuit according to an embodiment of the present invention can be locked (lock) regardless of the position of the poly edge, there is an effect that can correspond to various clock formats.
Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.
3A and 3B illustrate a
The
The
The up
The flip-flop portion includes first to
For example, the
The first logical operation unit performs a logical operation on the first output Q1, the second output Q2, the third output Q3, the fourth output Q4, and the up signal UPB. The harmonic up signal HUP is output based on the result.
The first logic operation unit may include first to
Each of the first to
The first NOR
The
The first exclusive NOR
The third NOR
The first NAND
The
The fifth to
Each of the eighth to
The
The third exclusive NOR
The twelfth to
The
The sixth NOR
The
4 illustrates a voltage controlled
The voltage controlled
FIG. 5 is a circuit diagram of a unit delay cell block shown in FIG. 4. Referring to FIG. 5, the input clock RCLK is input to the input terminal N1, and the first delay signal DA1 is output through the output terminal N2 by the operation of the delay cell block. The first delay signal is input to the
FIG. 6 illustrates waveforms of the fourteenth delay signal DA14 of the fourteenth
7 is a conceptual diagram illustrating a harmonic lock detection scheme according to an embodiment of the present invention.
The meaning shown in FIG. 7 is indicated for generalization because a detection edge must be taken separately according to the case where the difference in specifications of the duty ratio is the greatest.
An edge is selected to detect the harmonic up signal HUP. If N is determined instead of an integer, the edge for detecting the harmonic up signal HUP is an integer closest to N, and an integer greater than N may be selected. The integer is equal to the value of the edge.
The harmonic up HUP is not generated when all edges smaller than the point detected by N_I are high, and HUP is generated when any one of edges less than or equal to N_I is detected as low.
Considering four cases when selecting an edge below N_I, it should be limited to occur only when the actual harmonic up signal (HUP) should be generated.
In the case of the harmonic down signal HDN, when N is determined, N_I closest to N is determined in a spec when N is largest. N_I is an integer. The harmonic down signal (HDN) is opposite to the harmony up signal (HUP). If the harmonic down signal (HDN) is generated only when all of N_I or less are high, and there is a signal falling low among the edges of N_I or less, then the harmonic down signal (HDN) HDN) does not occur.
8 illustrates a
The
The
The seventh NOR
The
Each of the eleventh flip flops to 18
For example, the eleventh flip-
A seventeenth inverter 832 inverts the thirteenth output Q13. An
The
The seventh NOR
The
The
The
The ninth NOR
The
The twelfth NOR
When N is the smallest, it is 21.42% and it is 3 in the edge. And when N is the largest, 78.57% and 11 is the edge.
Therefore, the harmonic up edge (HUP) is set to 4 and the harmonic down edge (HDN) is set to 10. In addition, the frequency of the feedback signal FCLK is set so as not to be delayed by 2 times. When the frequency of the feedback signal FCLK is delayed by 2 times, the
9A and 9B show a harmonic detection scheme of the harmonic detector shown in FIG. 9A and 9B, when the second delayed signal DA02, the third delayed signal DA03, and the fourth delayed signal DA04 are all high, the harmonic up signal HUP is not generated. . On the other hand, if any one of the second delay signal DA02, the third delay signal DA03, and the fourth delay signal DA04 is LOW, the harmonic up signal is generated.
In addition, when the fourth delay signal DA04, the eighth delay signal DA08, and the tenth delay signal DA10 are all high, a harmonic down signal is generated. However, if any one of the fourth delay signal DA04, the eighth delay signal DA08, and the tenth delay signal DA10 is low, the harmonic down signal is not generated.
In another embodiment, a delay locked loop (DLL) circuit compares an rising edge of an input clock RCLK and a feedback clock FCLK in which the input clock RCLK is delayed, and based on a result of the comparison, an up signal UPB. Or a phase detector for generating a down signal DNB, an input clock RCLK, and a feedback clock FCLK, and an input clock RCLK, an inverted input clock RCLKB in which the input clock is inverted, and the feedback clock. A flip-
The flip-flop unit may include a first flip-
The logical operation unit performs a logical operation on the first output Q1, the second output Q2, the third output Q3, the fourth output Q4, and the down signal DNB, and performs a logical operation on the result. And outputs the harmonic down signal HDN.
A delay locked loop (DLL) circuit according to another embodiment of the present invention receives an input clock RCLK, delays the received input signal RCLK, and provides a plurality of delay signals DA01 to DA14 having different phases. A
The
The DLL including the harmonic lock detector according to an embodiment of the present invention can cope with various clock formats and implement a duty free DLL.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
1 shows a block diagram of a general phase detector.
2A and 2B show an abnormal harmonic state of the phase detector in FIG. 1.
3A and 3B illustrate a harmonic lock detector according to an embodiment of the present invention.
4 shows a voltage controlled delay line that generates a feedback clock for the input clock.
FIG. 5 is a circuit diagram of a unit delay cell block shown in FIG. 4.
6 illustrates waveforms of a fourteenth delay signal of the fourteenth delay cell block illustrated in FIG. 4.
7 is a conceptual diagram illustrating a harmonic lock detection scheme according to an embodiment of the present invention.
8 illustrates a harmonic lock detector according to an embodiment of the present invention.
9A and 9B show a harmonic detection scheme of the harmonic detector shown in FIG.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020080137604A KR20100079188A (en) | 2008-12-30 | 2008-12-30 | Circuit for delay locked loop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020080137604A KR20100079188A (en) | 2008-12-30 | 2008-12-30 | Circuit for delay locked loop |
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KR20100079188A true KR20100079188A (en) | 2010-07-08 |
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Family Applications (1)
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KR1020080137604A KR20100079188A (en) | 2008-12-30 | 2008-12-30 | Circuit for delay locked loop |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102347762A (en) * | 2010-07-30 | 2012-02-08 | 三星半导体(中国)研究开发有限公司 | Locking detection circuit of phase-locked loop circuit |
-
2008
- 2008-12-30 KR KR1020080137604A patent/KR20100079188A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102347762A (en) * | 2010-07-30 | 2012-02-08 | 三星半导体(中国)研究开发有限公司 | Locking detection circuit of phase-locked loop circuit |
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