KR20100076806A - Data output apparatus for semiconductor memory - Google Patents

Data output apparatus for semiconductor memory Download PDF

Info

Publication number
KR20100076806A
KR20100076806A KR1020080134976A KR20080134976A KR20100076806A KR 20100076806 A KR20100076806 A KR 20100076806A KR 1020080134976 A KR1020080134976 A KR 1020080134976A KR 20080134976 A KR20080134976 A KR 20080134976A KR 20100076806 A KR20100076806 A KR 20100076806A
Authority
KR
South Korea
Prior art keywords
data
output
signal
driver
high frequency
Prior art date
Application number
KR1020080134976A
Other languages
Korean (ko)
Inventor
김용미
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080134976A priority Critical patent/KR20100076806A/en
Publication of KR20100076806A publication Critical patent/KR20100076806A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Abstract

PURPOSE: A data output apparatus for a semiconductor memory is provided to secure a tCK property by improving a valid data window(tDV) in high frequency operation conditions. CONSTITUTION: A pre-drive control unit(110) transmit rising data and falling data. The rising data and falling data are synchronized with a rising DLL clock and a falling DLL clock. A data output buffer unit(114) outputs data. The pre-driver unit(112) drives a data output buffer. The pre-drive control unit controls the driving performance of the data output buffer unit by using a high frequency control information.

Description

Data output device of semiconductor memory {DATA OUTPUT APPARATUS FOR SEMICONDUCTOR MEMORY}

The present invention relates to a semiconductor memory, and more particularly to a data output device for controlling the output operation of the data.

In modern society, most electronic products use semiconductor memory. For example, semiconductor memories are used in many electronic products such as personal computers (PCs), televisions, audio devices, and communication devices. As described above, semiconductor memories used in various fields receive and store data from other electronic devices or electronic devices, and provide the stored data to other electronic devices or electronic devices on demand. Accordingly, semiconductor memories require circuits or devices related to the input and output of data between other electronic devices and the semiconductor memory. That is, a circuit or device for exchanging data with other electronic devices or electronic devices is required.

Fig. 1 shows a block diagram of a data output device used in a conventional semiconductor memory.

As shown in the drawing, the conventional data output apparatus includes a predriver control unit 10 (PREDRV_CTRL), a predriver driver 12 (PREDRV), a data output buffer 14 (DOUT BUFFER), and an output terminal pad 16. Lose.

That is, the data written to the cell according to the read command is loaded on the GIO data line and output through the pre-driver controller, the predriver, the data output buffer, and the pad through the mux through the pipe latch.

As shown in FIG. 2, the predriver controller 10 applies rising data RDO and polling data FDO, which are data read from a cell by a read command, to the transmission gates 20 and 21. In synchronization with the rising DLL clock RCLKDLL and the falling DLL clock FCLKDLL, the output terminal UP1 is loaded with high or low. Inverters 30 and 31 here represent latch portions.

In addition, as shown in FIG. 3, the predriver control unit 10 applies the rising data RDO and the falling data FDO to the transmission gates 22 and 23, and the rising DLL clock RCLKDLL and the like. In synchronization with the polling DLL clock FCLKDLL, a high or low is applied to the output DN1B. Inverters 33 and 34 here represent latch portions.

That is, when the signal of the rising data RDO is the high level data, the transmission gate 20 is turned on in the high state of the rising DLL clock RCLKDLL. Accordingly, the low state signal UP0B is generated in accordance with the rising DLL clock timing, and the low state signal is inverted by the inverter 32 to output a high state signal to the output terminal UP1.

The low state signal UP0B is input to the noar gate 40, but is enabled or disabled by the weak signal WEAK.

When the signal of the polling data FDO is low level data, the transmission gate 23 is turned on in the high state of the polling DLL clock FCLKDLL. Accordingly, the high state signal DN0 is generated in accordance with the polling DLL clock timing, and the high state signal is inverted by the inverter 35 to output a low state signal to the output terminal DN1B.

The high signal DN0 is input to the AND gate 50, but is enabled or disabled by the weak signal.

The pre-driver driver 12 is a driver for driving the data output buffer 14, as shown in FIG. The PMOS transistors 60 and 61 are turned on or off using the UP1 and UP2_WEAK signals output from the pre-driver controller 10, and the PMOS transistors 60 and 61 are turned on and off. The inverted UP1B / UP2 B_WEAK signal is generated for the input signal.

In addition, the pre-driver driver 12 turns on or off the PMOS transistors 62 and 63 by using the DN1B and DN2B_WEAK signals output from the pre-driver control unit 10, and the PMOS transistor 62. The turn-on / off operation of (63) generates the inverted DN1 and DN2_WEAK signals with respect to the input signal.

The detailed configuration of the data output buffer 14 is shown in FIG. As illustrated, the UP1B signal generated by the pre-driver driver 12 turns on / off the PMOS transistor group 80. The UP2B_WEAK signal generated by the pre-driver driver 12 turns on / off the PMOS transistor group 85. The DN1 signal generated by the predriver driver 12 turns on / off the NMOS transistor group 90, and the DN2_WEAK signal generated by the predriver driver 12 turns the NMOS transistor group 95 on / off. Turn off

That is, when the UP1B / UP2B_WEAK signal is turned on and the PMOS transistors 80 and 85 in the pull-up configuration in the data output buffer 14 are turned on, a high signal is output through the pad 16. On the contrary, when the DN1B / DN2B_WEAK signal is turned high and the NMOS transistors 90 and 95 having the pull-down configuration in the data output buffer 14 are turned on, a low signal is output through the pad 16.

On the other hand, when the WEAK signal used in the conventional data output device is HIGH as the address A1 information in the EMRS (1) code, the output driver impedance control signal OUTPUT DRIVER IMPEDANCE CONTROL SIGNAL is weak. State (enables only 50% to 60% of the power output of the data output buffer). When the address A1 information in the EMRS (1) code is low, the output driver impedance control signal operates in a full state (a state of enabling 100% of the power of the data output buffer).

Therefore, the conventional data output device has a pre-driver 12 and a data output buffer 14 by UP1 and DN1B signals which are always operated by default, and UP2 / DN2B signals that can be enabled or disabled by weak information. ) Outputs high or low data through the pad 16.

On the other hand, when outputting data in a read operation from the semiconductor memory, a valid data window DATA VALID WINDOW corresponding to a frequency is generated and output. For example, when 1tCK is 5ns in the semiconductor memory operation, a valid data window is generated within 1 / 2tCK. However, this operation decreases the data transmission time that must be guaranteed in tCK as the frequency is increased, and when the time for generating the valid data window decreases, the VOH (high output voltage) or data, which is a level when the data is output high, Guaranteed is also difficult for VOL (low output voltage), which is the level when output low. This problem gets worse and worse with higher frequencies.

However, the conventional data output device has a problem in that the tDV improvement method, which can be worsened at an actual high frequency, has not been prepared since only the operation control of the weak state or the full state is performed according to the control amount of the weak signal.

Accordingly, an object of the present invention is to provide a data output device of a semiconductor memory capable of ensuring an effective data window even in a high frequency operating condition.

According to another aspect of the present invention, there is provided a data output apparatus of a semiconductor memory, comprising: pre-driver control means for transmitting rising data and polling data according to a read signal in synchronization with a rising DLL clock and a falling DLL clock; Data output buffer means for outputting data; And a pre-driver means for driving the data output buffer by using the output signal of the pre-driver control means, and adjusting the driving capability of the data output buffer means by using high frequency control information.

The pre-driver control means of the present invention includes a data transmission unit for transmitting the rising data and the falling data in synchronization with the rising DLL clock and the falling DLL clock; It characterized in that it comprises a high frequency control signal generator for generating a control signal according to the high frequency control information.

The high frequency control signal generator of the present invention is characterized by generating a signal by calculating the high frequency control information and the output signal of the data transmission unit.

The pre-driver control means of the present invention is characterized in that it further comprises a weak control signal generator for generating a control signal according to the weak information.

The pre-driver means of the present invention comprises: a first switching unit for switching the output of the data transmission unit to a CMOS level; A second switching unit for switching the output of the weak control signal generator to a CMOS level; And a third switching unit for switching the output of the high frequency control signal generator to a CMOS level.

The data output buffer means of the present invention comprises: a first driver driven by an output signal of the first switch; A second driver driven by an output signal of the second switch; And a third driving unit driven by an output signal of the third switching unit.

The data output buffer means of the present invention is characterized by being configured in a pull-up / pull-down configuration.

In the present invention, the high frequency control information is characterized by using CL information.

The present invention has an effect of ensuring the tCK characteristic by improving the effective data window tDV under high frequency operating conditions. Furthermore, the present invention achieves the effect of improving the reliability of the product by providing a better SI to the customer.

Hereinafter, a data output apparatus of a semiconductor memory according to the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram of a data input / output path of a semiconductor memory device.

The mat 210 shown is a cell array portion of a semiconductor memory device. The portion indicated by 220 is the ferry area. In the ferry region 220, a ferry voltage VPERI is used.

The ferry area 220 is provided with an input / output sense amplifier (IOSA) 222 that is activated by an IOSTB control signal and amplifies reading data read from the mat 210. Data read from the mat 210 is input to the input / output sense amplifier 222 through a local data line LIO / LIOB.

A global data line (GIO), which is an input / output data line for data transmission, is connected between the input / output sense amplifier 222 and a mux and pipe (MUX &PIPE; 224), and the global data line (GIO) and the mux end Pipe 224 is also located in ferry region 220.

The mux and pipe 224 is configured to select and output data for output to the DQ pad side among data input from the global data line GIO.

The data selected by the mux and pipe 224 is output to the outside through the DQ control unit 227 and the DQ pad 230. The DQ control unit 227 outputs the data input from the mux and pipe 224 to the DQ pad 230 in synchronization with the DLL clock output from the delay locked loop (DLL: 226). That is, the ferry region 220 controls the output of data in synchronization with the DLL clock generated by the delay lock loop 226.

The delay locked loop 226 generates various DLL clock signals to be used in the ferry region 220 by using the reference clock signal generated by the clock generator 212.

Accordingly, the data written to the cell according to the read command is loaded on the GIO data line, and the DQ control unit 227 and the DQ pad 230 which are composed of a predriver control unit, a predriver, and a data output buffer via the mux and the pipe latch 224. Is output via

7 is a configuration diagram of a data output device of a semiconductor memory according to the present invention. The data output device illustrated in FIG. 7 may be described in relation to the DQ controller 227, the delay loop circuit 226, and the DQ pad 230 among the input / output paths of the semiconductor memory described above.

As shown, the data output apparatus of the present invention includes a predriver controller 110 (PREDRV_CTRL), a predriver driver 112 (PREDRV), a data output buffer 114 (DOUT BUFFER), and an output terminal pad 116. It is constructed.

As illustrated in FIG. 8, the predriver controller 110 applies rising data RDO and polling data FDO, which are data read from a cell by a read command, to the transmission gates 120 and 121. The output terminal UP1 is driven high or low in synchronization with the DLL clock RCLKDLL and the falling DLL clock FCLKDLL. Here, the inverters 130 and 131 represent latch portions.

In addition, as shown in FIG. 9, the predriver controller 110 applies the rising data RDO and the falling data FDO to the transmission gates 122 and 123, and the rising DLL clock RCLKDLL and the falling DLL. In synchronization with the clock FCLKDLL, a high or low is applied to the output terminal DN1B. Inverters 133 and 134 denote latch portions.

That is, when the signal of the rising data RDO is the high level data, the transmission gate 120 is turned on in the high state of the rising DLL clock RCLKDLL. Accordingly, the low state signal UP0B is generated in accordance with the rising DLL clock timing, and the low state signal is inverted by the inverter 132 to output the high state signal to the output terminal UP1.

In addition, the low signal UP0B is input to the noar gate 140, but is enabled or disabled by the weak signal WEAK. The low level signal UPOB and the high level HSCL signal inverted by the inverter 137 are inputted to the noble gate 141 to output a low signal. Here, the HSCL signal is high level operating frequency information. In other words, a high signal is provided at a high frequency, and a low signal at a high frequency. Therefore, when the low signal is output from the noble gate 141, the low signal is not a high frequency.

When the signal of the falling data FDO is low level data, the transmission gate 123 is turned on in the high state of the falling DLL clock FCLKDLL. Accordingly, the high state signal DN0 is generated in accordance with the polling DLL clock timing, and the high state signal is inverted by the inverter 135 to output a low state signal to the output terminal DN1B.

In addition, the high signal DN0 is input to the AND gate 150, but is enabled or disabled by the weak signal. The low signal UPOB and the low level HSCL signal are input to the NAND gate 151 to output a high signal. The case where the high signal is output from the Nantuit 151 is not the high frequency.

Therefore, the predriver control unit 110 of the present invention, in the data output buffer 114 to be described later, the operation unit is turned on / off controlled by the weak information and the turn-on / off control by the high-level operating frequency information The operation part is provided. That is, when the high level operating frequency information (HSCL) is in a high state, the operation unit which is turned on / off controlled by the high level operating frequency information in the data output buffer performs a control according to the high frequency operating conditions to drive capability To increase. When the high level operating frequency information is in a low state, the operation unit controlled to be turned on / off by the high level operating frequency information in the data output buffer is controlled to have a lower driving capability than the former case. This part will be described in detail below.

The pre-driver driver 112 is a driver for driving the data output buffer 114, as shown in FIG. The PMOS transistors 160, 161 and 164 are turned on or off using the UP1, UP2_WEAK and UPHSB signals output from the pre-driver controller 110, and the input signals are turned on / off by the PMOS transistors 160, 161 and 164. UP1B / UP2 B_WEAK / UPHS signals are inverted with respect to.

In addition, the pre-driver driver 112 turns on or off the PMOS transistors 162, 163, and 165 using the DN1B, DN2B_WEAK, and DNHS signals output from the pre-driver controller 110, and the PMOS transistors 162, 163, and 165. ), The inverted DN1, DN2_WEAK, and DNHSB signals are generated with respect to the input signal.

The detailed configuration of the data output buffer 114 is shown in FIG.

As illustrated, the UP1B signal generated by the pre-driver driver 112 turns on / off the PMOS transistor group 180. The UP2B_WEAK signal generated by the pre-driver driver 112 turns on / off the PMOS transistor group 185. Similarly, the UPHS signal generated by the pre-driver driver 112 turns on / off the PMOS transistor group 187.

The DN1 signal generated by the predriver driver 112 turns on / off the NMOS transistor group 190, and the DN2_WEAK signal generated by the predriver driver 112 turns the NMOS transistor group 195 on / off. Turn off Similarly, the DNHSB signal generated by the pre-driver driver 112 turns on / off the NMOS transistor group 197.

That is, when the UP1B / UP2B_WEAK signal is turned on and the PMOS transistors 180 and 185 of the pull-up configuration in the data output buffer 114 are turned on, a high signal is output through the pad 116. On the contrary, when the DN1B / UP2B_WEAK signal is turned high and the NMOS transistors 190 and 195 having the pull-down configuration in the data output buffer 114 are turned on, a low signal is output through the pad 116.

Here, the UP1B signal and the DN1B signal are default signals for data output. Therefore, the transistor groups 180 and 190 are unconditionally driven for data output by the UP1B signal and the DN1B signal. However, the UP2B_WEAK signal and the UP2B_WEAK signal are signals that control whether the data output buffer is driven to the full state or the wick state based on the weak information. Accordingly, the driving capability of the transistor groups 185 and 195 is adjusted according to the weak information.

On the other hand, the present invention also controls according to the operating frequency information in addition to the weak information. That is, the turn-on / off of the PMOS transistor group 187 and the NMOS transistor group 197 is controlled by the UPHS signal and the DNHSB signal to increase the driving capability of the data output buffer 114 or increase the driving capability. Adjust. In particular, the PMOS transistor group 187 in the pull-up configuration and the NMOS transistor group 197 in the pull-down configuration are turned on with the UPHS information and the DNHSB information enabled under high frequency operating conditions, thereby turning on the data output buffer. Improve tDV by increasing the IDS value of.

And FIG. 12 illustrates a circuit for generating high frequency information (HSCL) according to an embodiment of the present invention.

In the illustrated embodiment, high frequency enable signals are generated using the CL information. That is, when the CL6 signal and the CL7 signal are input, the high frequency information generates a high signal.

The above-described preferred embodiment of the present invention has been disclosed for the purpose of illustration, and may be applied to the case of controlling the operation of the data output driver to ensure a valid data window in a high frequency operating condition. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a block diagram of a data output device of a semiconductor memory according to the prior art;

2 to 5 are detailed circuit diagrams of a conventional data output apparatus;

6 is a conceptual diagram illustrating a data input / output path of a semiconductor memory according to the present invention;

7 is a block diagram of a data output apparatus of a semiconductor memory according to the present invention;

9 to 12 are detailed circuit diagrams of the data output apparatus of the present invention.

Explanation of symbols on the main parts of the drawings

110: predriver control unit 112; Free drag

114; Data output buffer 116: pad

Claims (8)

Pre-driver control means for transmitting the rising data and the falling data according to the read signal in synchronization with the rising DLL clock and the falling DLL clock; Data output buffer means for outputting data; And a pre-driver means for driving the data output buffer by using the output signal of the pre-driver control means, and adjusting the driving capability of the data output buffer means by using high frequency control information. Output device. The method of claim 1, The pre-driver control means includes: a data transmission unit for transmitting the rising data and the falling data in synchronization with the rising DLL clock and the falling DLL clock; And a high frequency control signal generator for generating a control signal according to the high frequency control information. The method of claim 2, And the high frequency control signal generator generates a signal by calculating the high frequency control information and an output signal of the data transmitter. The method of claim 2, The pre-driver control means further comprises a weak control signal generator for generating a control signal according to the weak information. The method of claim 4, wherein The pre-driver means includes: a first switching unit for switching the output of the data transmission unit to a CMOS level; A second switching unit for switching the output of the weak control signal generator to a CMOS level; And a third switcher for switching the output of the high frequency control signal generator to a CMOS level. The method of claim 5, The data output buffer means may include: a first driver driven by an output signal of the first switch; A second driver driven by an output signal of the second switch; And a third driving unit driven by an output signal of the third switching unit. The method of claim 6, And said data output buffer means comprises a pull-up / pull-down configuration. The method of claim 1, The high frequency control information uses CL information.
KR1020080134976A 2008-12-26 2008-12-26 Data output apparatus for semiconductor memory KR20100076806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080134976A KR20100076806A (en) 2008-12-26 2008-12-26 Data output apparatus for semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080134976A KR20100076806A (en) 2008-12-26 2008-12-26 Data output apparatus for semiconductor memory

Publications (1)

Publication Number Publication Date
KR20100076806A true KR20100076806A (en) 2010-07-06

Family

ID=42638456

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080134976A KR20100076806A (en) 2008-12-26 2008-12-26 Data output apparatus for semiconductor memory

Country Status (1)

Country Link
KR (1) KR20100076806A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8780646B2 (en) 2011-11-07 2014-07-15 Hynix Semiconductor Inc. Semiconductor memory device
US9355706B2 (en) 2013-08-01 2016-05-31 Samsung Electronics Co., Ltd. Output circuit for implementing high speed data transmition

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8780646B2 (en) 2011-11-07 2014-07-15 Hynix Semiconductor Inc. Semiconductor memory device
US9355706B2 (en) 2013-08-01 2016-05-31 Samsung Electronics Co., Ltd. Output circuit for implementing high speed data transmition

Similar Documents

Publication Publication Date Title
US10490254B2 (en) Semiconductor integrated circuit system with termination circuit
KR100506976B1 (en) synchronous semiconductor memory device having on die termination circuit
KR100656470B1 (en) Apparatus and method for controlling driver of semiconductor memory
US7064989B2 (en) On-die termination control circuit and method of generating on-die termination control signal
JP4930875B2 (en) On-die termination control device
US7919978B2 (en) Control circuit for controlling on-die termination impedance
US20060255830A1 (en) On-die termination apparatus
US7919988B2 (en) Output circuit and driving method thereof
US9041436B2 (en) Semiconductor device having pull-up circuit and pull-down circuit
KR100533384B1 (en) Semiconductor Memory Device including Global IO line driven by Low Amplitude Voltage Signal
US5835449A (en) Hyper page mode control circuit for a semiconductor memory device
KR20100076806A (en) Data output apparatus for semiconductor memory
US7821847B2 (en) Circuit and method for controlling slew rate of data output circuit in semiconductor memory device
US8107271B2 (en) Termination circuits and semiconductor memory devices having the same
US8102722B2 (en) Data output device for semiconductor memory apparatus
KR100703887B1 (en) Data output driver having at least two operation types and semiconductor device including the same
US8284618B2 (en) Data input device of semiconductor memory appartus and control method thereof
KR100915810B1 (en) Multi Chip Package Sharing Pad
US9564191B1 (en) Signal compensation circuit and semiconductor apparatus using the same
US20060280025A1 (en) Semiconductor memory device
US7005890B2 (en) Device for generating a bit line selection signal of a memory device
KR20110076498A (en) Integrated circuit

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination