KR20100076761A

KR20100076761A - Output driver circuit

Info

Publication number: KR20100076761A
Application number: KR1020080134920A
Authority: KR
Inventors: 김경훈
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-12-26
Filing date: 2008-12-26
Publication date: 2010-07-06

Abstract

PURPOSE: An output driver of a semiconductor device is provided to reduce mismatch generated in a pull-up and pull down path by controlling the pull-up and pull-down simultaneously. CONSTITUTION: A data Input unit(210) generates a driving signal. The level of the driving signal changes according to a logic level. A plurality of pull-up drivers(230) pull-ups a data output terminal using different resistance. A plurality of pull-down drivers(240) pulls down the data output terminal using different resistance. A mode controller(220) receives resistance setting information and mode information. The mode controller controls the operation of the pull-down driver and pull-up driver.

Description

Output driver circuit {OUTPUT DRIVER CIRCUIT}

The present invention relates to an output driver for outputting data from a semiconductor chip, and more particularly, to a technique for reducing mismatch and loading of an output driver.

A typical semiconductor device includes a data input unit for receiving data, a core region for processing data signals transmitted through the data input unit, and a data output unit for outputting data processed in the core region to the outside.

A data input pad and a data output pad are provided for data input and output, and the data input unit and the data output unit are connected to the data input pad and the data output pad, respectively. Recently, in order to reduce pads of a semiconductor device, data input / output pads capable of inputting and outputting data into one pad have been widely used.

When the data is delivered to the semiconductor device, the signal is transmitted with a sufficiently large signal. However, since the data processed and output in the core region is output as a very small signal, the data output unit is externally loaded according to the data transmitted from the core region. You must have high driving capability to pull up or pull down the load).

Therefore, an output driver is provided in the data output unit. The driving capability of the output driver is determined by the impedance applied to the data pad. If the output driver has a driving capability less than the impedance applied to the data pad, it takes a lot of time to output the data. On the contrary, if the output driver has a driving capability that is too large than the impedance applied to the data pad, unnecessary power is consumed. Therefore, it is important that the output driver has a driving capability suitable for the magnitude of the impedance applied to the data pad in the current operating state. Recently, the output driver is manufactured to have various driving capabilities, and the driving capability can be adjusted by internal control, thereby making it possible to have an optimal driving capability during operation of the semiconductor device.

1 is a configuration diagram of an output driver circuit according to the prior art.

As shown in the figure, the conventional output driver circuit, the pull-up data input unit 110_PU, pull-down data input unit 110_PD, pull-up mode control unit 120_PU, pull-down mode control unit 120_PU, a plurality of pull-up driver unit ( 130 to 150, and a plurality of pull-down driver units 160 to 180 are configured.

The pull-up data input unit 110_PU outputs rising data (RDO, data to be output in the 'high' section of the clock) in the 'high' level section (CLK = 'high' and CLKB = 'low') of the clock CLK. In the 'low' level section of the clock CLK, polling data (FDO, data to be output in the 'low' section of the clock) is output to the A_PU node. Similarly, the pull-down data input unit 110_PD outputs the rising data RDO to the A_PU node in the 'high' level section of the clock CLK and the polling data FDO in the 'low' level section of the clock CLK. Will output

The plurality of pull-up drivers 130 to 150 have different resistance values. The pull-up driver 130 has a resistance of 60 Ω, the pull-up driver 140 has a resistance of 120 Ω, and the pull-up driver 150 has a resistance of 240 Ω. The pull-up drivers 130 to 150 operate only when the resistance value setting signals 60EN, 120EN, and 240EN indicating that the corresponding resistance value is set. The pull-up driver 130 operates when 60EN is enabled, and the pull-up driver 140 operates when 120EN is enabled, and the pull-up driver 150 operates when 240EN is enabled.

The pull-up drivers 130 to 150 are turned on when the logic level of the A_PU node is 'high' and pulls up the data pad DQ PAD, and is turned off when the logic level of the A_PU node is 'low' (data pad). Do not drive). Of course, in order for the pull-up drivers 130 to 150 to drive the data pad DQ PAD, the resistance value setting signals 60EN, 120EN, and 240EN that select the corresponding pull-up drivers 130 to 150 must be enabled.

The plurality of pull-down drivers 160 to 180 also have different resistance values as the pull-up drivers 130 to 150. The pull-down driver 160 has a resistance of 60 Ω, the pull-down driver 170 has a resistance of 120 Ω, and the pull-down driver 180 has a resistance of 240 Ω. The pull-down drivers 160 to 180 operate only when the resistance value setting signals 60ENB, 120ENB, and 240ENB indicating that the resistance value is set are enabled. When 60ENB is enabled as 'low', the pulldown driver 160 operates. When 120ENB is enabled, the pulldown driver 170 operates, and when 240ENB is enabled, the pulldown driver 180 operates.

The pull-down drivers 160 to 180 turn on when the logic level of A_PD is 'low' to pull down the data pad DQ PAD, and turn off when the logic level of A_PD is 'high' (drive the data pad). Of course, in order for the pull-down drivers 160 to 180 to drive the data pad DQ PAD, the resistance setting signals 60ENB, 120ENB, and 240ENB for selecting the pull-down drivers 160 to 180 are enabled. Should be

The pull-up mode controller 120_PU and the pull-down mode controller 120_PD are provided to control the mode of the output driver circuit. In termination mode, the ODT signal is enabled 'high'. Accordingly, the pull-up mode controller 120_PU makes the A_PU node a 'high' level, and the pull-down mode controller 120_PD makes the A_PD node a 'low' level. Therefore, the driver whose resistance value is set among the pull-up drivers 130 to 150 and the pull-down drivers 160 to 180 is turned on to perform the termination operation. For example, when the resistance value is set to 60Ω, the pull-up driver 130 and the pull-down driver 160 are simultaneously turned on to terminate the operation. In the floating mode (HI-Z MODE), the HI-Z signal is enabled as 'high'. Accordingly, the pull-up mode controller 120_PU makes the A_PU node a 'low' level, and the pull-down mode controller 120_PD makes the A_PD node a 'high' level. Therefore, at this time, all pull-up drivers 130 to 150 and pull-down drivers 160 to 180 are turned off to make the data pad DQ PAD floating.

As described above, the output driver circuit according to the related art separately controls the pull-up driver 130 to 150 and the pull-down driver 160 to 180. Therefore, the data input unit 110_PU and 110_PD and the mode control unit 120_PU and 120_PD have a disadvantage in that pull-up and pull-down are provided separately. In addition, the NAND gate is used for the pull-up drivers 130 to 150, and the no-gate is used for the pull-down drivers 160 to 180, so that a mismatch occurs in the pull-up and pull-down paths.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and aims to reduce mismatches in the pull-up and pull-down paths of data by simultaneously controlling the pull-up and pull-down drivers of the output driver circuit. .

An output driver circuit according to the present invention for achieving the above object, the data input unit for generating a drive signal whose level is changed in accordance with the logic level of the data; A plurality of pull-up drivers for driving the data output stages with different resistance values; A plurality of pull-down drivers for pulling down the data output stage with different resistance values; And a mode control unit which receives the resistance value setting information and the mode information and controls the pull-up driver and the pull-down driver corresponding to the set resistance value to operate in response to the driving signal in the data output mode.

The mode controller may control the plurality of pull-up drivers and the plurality of pull-down drivers to be turned off in the floating mode. The mode control unit may control the pull-up driver and the pull-down driver corresponding to the set resistance value to be driven in the termination mode.

The output driver circuit according to the present invention controls various modes of the pull-up driver and the pull-down driver in the same manner. Therefore, there is an advantage that the mismatch of pull-up and pull-down passes of data and the mismatch of pull-up and pull-down drivers can be eliminated.

In addition, since the data input unit and the mode elimination unit are unified, there is an advantage that the load of the path through which the data and the clock pass can be reduced.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a configuration diagram of an embodiment of an output driver circuit according to the present invention.

As shown in the figure, the output driver circuit according to the present invention comprises: a data input unit 210 for generating a drive signal A whose level changes in accordance with the logic levels of the data RDO and FDO; A plurality of pull-up drivers 230 <60>, 230 <120>, and 230 <240> for pulling up the data output terminal DQ PAD with different resistance values; A plurality of pull-down drivers 240 <60>, 240 <120>, 240 <240> for pull-down driving the data output terminal DQ PAD with different resistance values; And pull-up drivers 230 <60>, 230 <120>, which correspond to the set resistance values in the data output mode by receiving the resistance value setting information (60EN, 120EN, 240EN) and the mode information (ODT, HI-Z). 230 <240>) and pull-down drivers 240 <60>, 240 <120>, 240 <240> are configured to include a mode control unit 220 for controlling to operate in response to the drive signal (A). In the termination mode, the mode controller 220 may include pull-up drivers 230 <60>, 230 <120>, 230 <240> and pull-down drivers 240 <60>, 240 <120> and 240 <corresponding to the set resistance values. 240>) are all driven, and in floating mode pull-up drivers (230 <60>, 230 <120>, 230 <240>) and pull-down drivers (240 <60>, 240 <120>, 240 <240>) ) Are all turned off.

In the data output mode, the data input unit 210 outputs the rising data RDO as the driving signal A in the 'high' level section CLK = 'high' and CLKB = 'low' of the clock CLK. The polling data FDO is output as the driving signal A in the 'low' level section CLK = 'low' of the clock CLK. Meanwhile, in the termination mode and the floating mode, the data input unit fixes the driving signal A to the 'high' level. While no data is output, the clock CLK does not toggle, and the data RDO and FDO are also not transferred. Therefore, in the termination mode and the floating mode, the clock CLK = 'low', the rising data RDO = 'low', and the polling data FDO = 'low' are fixed, whereby the driving signal A is' Fixed to the high level.

The mode controller 220 pulls down the pull-up control signals B <60>, B <120>, and B <240> corresponding to the pull-up drivers 230 <60>, 230 <120>, and 239 <240>, respectively. The pull-down control signals C <60>, C <120>, and C <240> corresponding to the drivers 240 <60>, 240 <120>, and 240 <240> are generated. The pull-up control signals B <60>, B <120>, and B <240> are different from those in the data output mode (ODT = 'low' and HI-Z = 'low') when the corresponding resistance value is set. Enabled to 'high' in termination mode (ODT = 'high', HI-Z = 'low') and displayed as 'low' in floating mode (ODT = 'low', HI-Z = 'high') If the resistance value is not set, it is 'low' regardless of the mode. The pull-down control signals C <60>, C <120>, and C <240> are enabled as 'high' in the data output mode and the floating mode when their resistance values are set, and in the termination mode. It is disabled as 'low', and is disabled as 'low' regardless of the mode when the corresponding resistance value is not set. The resistance value signals D <60>, D <120>, and D <240> output from the mode control unit correspond to signals buffering the resistance value setting information 60EN, 120EN, and 240EN. By buffering, the D <60>, D <120>, and D <240> signals are pull-up control signals (B <60>, B <120>, B <240>) and pull-down control signals (C <60>, C <). 120>, C <240>) and enable / disable at the same timing.

Each of the pull-up drivers 230 <60>, 230 <120>, and 230 <240> is a drive signal A and a pull-up control signal B <60>, B <120>, and B <240> corresponding to the drive signal A. First NAND gates ND1 <60>, ND1 <120>, and ND1 <240> that receive the inputs; Second NAND gates ND2 <60>, ND2 <120>, which receive the outputs of the first NAND gates ND1 <60>, ND1 <120>, and ND1 <240>, and receive the high-level signal VDDQ. ND2 <240>); First inverters IV1 <60>, IV1 <120>, and IV1 <240> inverting the outputs of the second NAND gates ND2 <60>, ND2 <120>, and ND2 <240>; And pull-up transistors PM <60>, PM <120>, and PM <240> which are turned on / off in response to the first inverters IV1 <60>, IV1 <120>, and IV1 <240>. .

Each of the pull-down drivers 240 <60>, 240 <120>, and 240 <240> is a drive signal A and pull-down control signals C <60>, C <120>, and C <240> corresponding to the drive signal A. Third NAND gates ND3 <60>, ND3 <120>, and ND3 <240> that receive the inputs; Resistor value signals D <60>, D <120>, which are enabled when the outputs of the third NAND gates ND3 <60>, ND3 <120>, and ND3 <240> and the resistance values of the corresponding pull-down driver parts are selected. Fourth NAND gates ND4 <60>, ND4 <120>, and ND4 <240> receiving D <240>; Second inverters IV2 <60>, IV2 <120>, and IV2 <240> which invert the outputs of the fourth NAND gates ND4 <60>, ND4 <120>, and ND4 <240>; And pull-down transistors NM <60>, NM <120>, and NM <240 that are turned on / off in response to the second inverters IV2 <60>, IV2 <120>, and IV2 <240>.

In the data output mode, when a 'high' data is output, a pull-up driver in which resistance values are set among the pull-up drivers 230 <60>, 230 <120>, and 230 <240> is turned on, and all other drivers are turned off. When outputting 'low' data, the pull-down driver in which the resistance value is set among the pull-down drivers 240 <60>, 240 <120>, and 240 <240> is turned on, and all other drivers are turned off. In the termination mode, pull-up drivers (230 <60>, 230 <120>, 230 <240>) and pull-down drivers (240 <60>, 240 <120>, 240 <240>) with resistance values set are turned on. The drivers are off. In the floating mode, all pull-up drivers 230 <60>, 230 <120>, 230 <240> and pull-down drivers 240 <60>, 240 <120>, 240 <240> are turned off.

Table 1 below shows all operations of the output driver circuit shown in FIG. 2.

mode Data output mode (high) Data output mode (low) Termination Mode Floating mode
Resistance value setting 60 120 240 60 120 240 60 120 240 60 120 240 Turned on driver 230 <60> 230 <120> 230 <240> 240 <60> 240 <120> 240 <240> 230 <60>, 240 <60> 230 <120>, 240 <120> 230 <240>, 240 <240> all off
A H H H L L L H H H H H H B <60> H L L H L L H L L L L L B <120> L H L L H L L H L L L L B <240> L L H L H L L L H L L L C <60> H L L H L L L L L H L L C <120> L H L L H L L L L L H L C <240> L L H L L H L L L L L H D <60> H L L H L L H L L H L L D <120> L H L L H L L H L L H L D <240> L L H L L H L L H L L H

The output driver circuit according to the present invention includes pull-up drivers 230 <60>, 230 <120>, 230 <240> and pull-down drivers 240 <60>, 240 <120>, 240 from one data input unit 210. <240> receives data, one mode control unit 220 is pull-up driver (230 <60>, 230 <120>, 230 <240>) and pull-down driver (240 <60>, 240 <120>, 240 <240>). Therefore, the loading of the data FDO and RDO and the clock CLK can be reduced. In addition, since pull-up drivers 230 <60>, 230 <120>, 230 <240> and pull-down drivers 240 <60>, 240 <120>, 240 <240> are designed with the same circuit, pull-up drivers ( It is also possible to reduce mismstch between 230 <60>, 230 <120>, 230 <240>) and pull-down drivers 240 <60>, 240 <120>, 240 <240>.

3 is a diagram illustrating an embodiment of the mode control unit 220 of FIG. 2.

As shown in the figure, the mode control unit 220 is composed of a combination of a plurality of NAND gates, inverters, noah gates. Under certain conditions, the mode controller 220 may control any signal B <60>, B <120>, B <240>, C <60>, C <120>, C <240>, D <60>, or D <120. >, D <240>) is enabled or disabled in detail in Table 1 above, so a detailed description thereof will be omitted here.

4 is a configuration diagram of another embodiment of an output driver circuit according to the present invention.

The output driver circuit of FIG. 4 is basically the same as the output driver circuit of FIG. 1, and has a configuration in which the driving signal controller 410 is included in the circuit of FIG. 1.

The driving signal controller 410 is provided to fix the driving signal to the 'high' level in the termination mode and the floating mode. The driving signal control unit 410 includes an ODT gate and a transistor 413 that receives an output of the OR gate 411 and 412 and an ODT signal and an HI-Z signal. If one or more of the levels are 'high' level, the level of the driving signal A is fixed to the 'high' level.

As described above, when not in the data output mode, the clock CLK is fixed at the 'low' level and the logic levels of the data RDO and FDO are fixed at the 'low', and the driving signal A is 'high'. At the level, the driving signal controller 410 is provided to more securely fix the level of the driving signal A when not in the data output mode.

Since the output driver circuit of FIG. 4 is configured and operated in the same manner as the output driver circuit of FIG. 1 except that the driving signal controller 410 is added, a detailed description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of an output driver circuit according to the prior art.

2 is a block diagram of an embodiment of an output driver circuit according to the present invention;

3 is a configuration diagram of an embodiment of the mode control unit 220 of FIG. 2.

4 is a block diagram of another embodiment of an output driver circuit according to the present invention;

Claims

A data input unit for generating a driving signal whose level changes in accordance with a logic level of data;

A plurality of pull-up drivers for driving the data output stages with different resistance values;

A plurality of pull-down drivers for pulling down the data output stage with different resistance values; And

The mode control unit receives the resistance value setting information and the mode information and controls the pull-up driver and the pull-down driver corresponding to the set resistance value to operate in response to the driving signal in the data output mode.

Output driver circuit comprising a.

The method of claim 1,

The mode control unit,

And outputting the plurality of pull-up drivers and the plurality of pull-down drivers to be turned off in the floating mode.

3. The method of claim 2,

The mode control unit,

The output driver circuit, characterized in that in the termination mode, the pull-up driver and the pull-down driver corresponding to the set resistance value are controlled to be driven.

The method of claim 3, wherein

The data input unit,

And the level of the driving signal is fixed at a constant value in the termination mode and the floating mode.

The method of claim 4, wherein

The mode control unit,

And a pull-up control signal corresponding to each of the pull-up driver units and a pull-down control signal corresponding to each of the pull-down driver units.

The method of claim 5,

Each of the pull-up drivers,

A first NAND gate receiving the driving signal and the pull-up control signal corresponding to the driving signal;

A second NAND gate configured to receive an output of the first NAND gate and a signal having a 'high' level;

A first inverter for inverting the output of the second NAND gate; And

A pull-up transistor turned on / off in response to the first inverter

Output driver circuit comprising a.

The method of claim 6,

Each of the pull-down drivers,

A third NAND gate receiving the driving signal and the pull-down control signal corresponding to the driving signal;

A fourth NAND gate configured to receive a resistance value signal enabled when an output of the third NAND gate and a resistance value of the corresponding pull-down driver unit are selected;

A second inverter for inverting the output of the fourth NAND gate; And

A pull-down transistor turned on / off in response to the second inverter

Output driver circuit comprising a.

The method of claim 7, wherein

The pull-up control signal,

When a resistance value corresponding to the self is set, it is enabled in the data output mode and the termination mode, and disabled in the floating mode.

The output driver circuit is disabled when a resistance value corresponding to the self is not set.

The method of claim 8,

The pulldown control signal,

When a resistance value corresponding to the self is set, it is enabled in the data output mode and the floating mode, and disabled in the termination mode.