KR20100073436A - Metal line and the fabrication method for semiconductor device - Google Patents

Metal line and the fabrication method for semiconductor device Download PDF

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Publication number
KR20100073436A
KR20100073436A KR1020080132107A KR20080132107A KR20100073436A KR 20100073436 A KR20100073436 A KR 20100073436A KR 1020080132107 A KR1020080132107 A KR 1020080132107A KR 20080132107 A KR20080132107 A KR 20080132107A KR 20100073436 A KR20100073436 A KR 20100073436A
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KR
South Korea
Prior art keywords
metal layer
metal
barrier
semiconductor device
region
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KR1020080132107A
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Korean (ko)
Inventor
김승현
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주식회사 동부하이텍
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Priority to KR1020080132107A priority Critical patent/KR20100073436A/en
Publication of KR20100073436A publication Critical patent/KR20100073436A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The metal wiring of the semiconductor device according to the present embodiment may include a first barrier metal formed on a semiconductor substrate; A metal layer formed on the first barrier metal; And a second barrier metal formed on the metal layer, wherein the metal layer has a doped region into which a predetermined element is injected.

Description

Metal wiring of semiconductor device and its formation method {metal line and the fabrication method for semiconductor device}

This embodiment discloses a metal wiring of a semiconductor element.

In recent years, with the rapid spread of information media such as computers, semiconductor devices have also been developed rapidly. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity and information processing capability. In response to these demands, manufacturing techniques have been rapidly developed in the direction of improving integration, reliability, response speed, and the like.

In general, an aluminum metal interconnection film applied to electrically connect an element and an element, or an interconnection and an interconnection in a logic or DRAM semiconductor device is used to improve the aluminum buried characteristics in the fine holes and to reduce the interconnection width of the interconnection. In order to improve the reliability, a laminated wiring film structure in which a titanium film is deposited on the upper and lower portions of the aluminum metal wiring film is used.

1 is a partial cross-sectional view showing an aluminum metal wiring of a conventional semiconductor device, Figure 2 is a partial cross-sectional view showing the aluminum metal wiring formed after the heat treatment of the aluminum metal wiring of FIG.

As shown in FIG. 1, the aluminum metal wire of the conventional semiconductor device includes a first barrier metal layer 121, an aluminum metal layer 110, a second barrier metal layer 122, and an anti-reflection film layer 124.

The aluminum metal wires formed as described above are subjected to sintering at 400 ° C. for about 30 minutes for stabilization of transistor characteristics and grain growth of aluminum metal wires in the final process after the semiconductor device is completed.

In addition, the general logic device is deposited as a multi-layered aluminum metal wiring as described above, and undergoes several heat treatment processes in a subsequent process.

As shown in FIG. 2, in this sintering and heat treatment process, the aluminum metal layer 15 reacts with the first and second barrier metal layers 121 and 122 located at the top and the bottom thereof, and thus the aluminum metal layer 110 and the first and second layers. Reaction precipitates 131 and 132 between the barrier metal layers 121 and 122 are formed.

For example, when the first and second barrier metal layers 121 and 122 are titanium layers Ti, the reaction precipitates 131 and 132 between the aluminum metal layer 110 and the first and second barrier metal layers 121 and 122 may be formed. A tie aluminum layer (TiAl 3 ) is formed.

In the aluminum metal wiring of the final semiconductor element formed as described above, it is most important to improve the electromigration (EM) characteristics of the wiring.

The aluminum metal layer 110 forms voids and hillocks as grains move due to heat generation and electron movement when electron movement characteristics are measured, thereby causing a problem in that the metal wiring is shorted. Therefore, the reliability of the device has a fatal effect.

At this time, the reaction precipitates 131 and 132 between the aluminum metal layer 110 and the first and second barrier metal layers 121 and 122 have high resistance, but in the related art, the thickness of the tie aluminum layer, which is the reaction precipitate, is thin and irregular, Since the resistance to movement is low, short circuits of metal wires are caused by the voids and the heel locks, thereby degrading device reliability.

In this embodiment, even when voids or the like occur in the metal wiring, a metal wiring and a method of forming the semiconductor device capable of ensuring the smooth movement of electrons are proposed.

The metal wiring of the semiconductor device according to the present embodiment may include a first barrier metal formed on a semiconductor substrate; A metal layer formed on the first barrier metal; And a second barrier metal formed on the metal layer, wherein the metal layer has a doped region into which a predetermined element is injected.

In addition, the method of forming a metal wiring of the semiconductor device of the embodiment comprises the steps of sequentially forming a first barrier metal, a metal layer and a second barrier metal on the semiconductor substrate; And a step of injecting impurities into the metal layer, and performing a plurality of impurity implantation processes by varying the implantation energy.

According to the metal wiring and the method of forming the semiconductor device of the embodiment as proposed, there is an advantage that the electrons can be smoothly moved by the doped impurities in the metal wiring even when a defect such as a void occurs in the metal wiring.

Hereinafter, with reference to the accompanying drawings for the present embodiment will be described in detail. However, the scope of the idea of the present invention may be determined from the matters disclosed by the present embodiment, and the idea of the invention of the present embodiment may be performed by adding, deleting, or modifying components to the proposed embodiment. It will be said to include variations.

In the following description, the word 'comprising' does not exclude the presence of other elements or steps than those listed. In addition, in the accompanying drawings, the thickness thereof is enlarged in order to clearly express various layers and regions. In addition, the same reference numerals are used for similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only being another part "on top" but also having another part in the middle.

3 and 4 are views for explaining a method for forming a metal wiring of the semiconductor device according to the present embodiment, Figure 5 is a view for explaining a metal wiring of the semiconductor device according to the present embodiment.

First, referring to FIG. 3, a metal layer is deposited on a substrate 200 on which a predetermined lower structure is formed, and metal wires having a desired pattern are formed through a known photo factory.

The metal wire includes a metal layer 210, a first barrier metal 221 formed under the metal layer 210, and a second barrier metal 222 formed on the metal layer 210.

Here, the metal layer 210 may be made of aluminum, but is not necessarily limited thereto, and may be tungsten or copper.

The first and second barrier metals 221 and 222 may be formed of one material selected from the group of Ta, TaN, TaAlN, TaSiN, Ti, TiN, WN, TiSiN, TCu, and the like.

For reference, the first barrier metal layer 221 is formed on the lower structure by using titanium or the like as a bottom barrier on the lower structure by sputtering or the like, and argon (Ar) is injected into the chamber at about 200 ° C. or less. It can be deposited to a thickness of about 50 kW to 200 kW.

In addition, the metal layer 210 is formed on the first barrier metal layer 221 by sputtering or the like. The metal layer 210 may be formed at a thickness of about 300 kPa to 1000 kPa while being deposited at about 200 ° C. or more.

Thereafter, a second barrier metal layer 222 is formed on the metal layer 210 in the same manner as the first barrier metal layer 221, and the second barrier metal layer 222 is deposited to a thickness of about 50 μs to 200 μs. Can be.

The metal wiring of the semiconductor device formed by the above method may further undergo various heat treatments in a subsequent process.

Next, referring to FIG. 4, a process of injecting impurities into the metal layer 210 is performed.

In detail, the impurity implantation process herein may be performed twice by varying the implantation energy, and according to the variation of the embodiment, another impurity implantation process may be performed.

The impurity implantation process is to form an additional barrier metal in the metal layer 210 and injects Ti-based elements.

Accordingly, the first barrier region 230 formed adjacent to the first barrier metal 221 and the second barrier region 240 formed adjacent to the second barrier metal 222 in the metal layer 210. To form.

The first and second barrier regions 240 are impurity regions formed by injecting Ti-based elements into the metal layer 210, and their formation positions may be determined according to the implantation energy of the elements.

However, even when defects such as voids occur in the metal layer 210, the first layer is formed from the interface where the metal layer 210 is in contact with the first and second barrier metals 221 and 222 so that electrons can move. And the second barrier regions 240 may be formed at predetermined intervals.

For example, as illustrated in FIG. 5, the first barrier region 230 formed in the metal layer 210 may have a predetermined distance from the surface of the metal layer 210 which is in contact with the first barrier metal 230. It is formed inside the metal layer. Thus, even though voids are generated in the metal layer 210, electrons may move through the metal layer positioned between the surface of the metal layer 210 and the first barrier region 230.

This structure also applies to the second barrier region 240.

Thus, even when voids are generated in the metal layer 210, electrons may move through the metal layer between the surface of the metal layer and the first or second barrier regions 230 and 240.

This embodiment described above is a pattern that may be structurally vulnerable to EM (that is, a metal wiring connection between a region where a small width of a metal wiring or a common path is stressed by continuous electron flow and a top / bottom of a single via. In the region, the excessive current can cause the aluminum ions to be diffused excessively, thereby creating a void or bridge.

1 is a partial cross-sectional view showing an aluminum metal wiring of a conventional semiconductor device.

2 is a partial cross-sectional view showing the aluminum metal wiring formed after the heat treatment of the aluminum metal wiring of FIG.

3 and 4 are diagrams for explaining a method for forming a metal wiring of the semiconductor device according to the present embodiment.

5 is a diagram for explaining a metal wiring of a semiconductor device according to the present embodiment.

Claims (8)

A first barrier metal formed on the semiconductor substrate; A metal layer formed on the first barrier metal; And And a second barrier metal formed on the metal layer. And a doped region in which a predetermined element is injected into the metal layer. The method of claim 1, The metal wiring of the semiconductor device, wherein the first barrier region and the second barrier region in which Ti-based impurities are injected are formed in the metal layer. The method of claim 2, And the first barrier region and the second barrier region are formed to have a predetermined distance from the surface of the metal layer. The method of claim 3, wherein And the first barrier region is formed to be adjacent to the first barrier metal relatively to the second barrier region. Sequentially forming a first barrier metal, a metal layer, and a second barrier metal on the semiconductor substrate; And A process of implanting impurities into the metal layer, the method comprising: performing a plurality of impurity implantation processes by varying the implantation energy; The method of claim 5, The method of injecting impurities into the metal layer is a method of forming a metal wiring of a semiconductor device to perform a Ti-based impurities twice with different injection energy. The method of claim 5, The method of implanting impurities into the metal layer is a method for forming a metal wiring of a semiconductor device such that the impurities are doped in a region separated by a predetermined distance from the surface of the metal layer. The method of claim 5, And the metal layer is an aluminum metal layer.
KR1020080132107A 2008-12-23 2008-12-23 Metal line and the fabrication method for semiconductor device KR20100073436A (en)

Priority Applications (1)

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KR1020080132107A KR20100073436A (en) 2008-12-23 2008-12-23 Metal line and the fabrication method for semiconductor device

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KR1020080132107A KR20100073436A (en) 2008-12-23 2008-12-23 Metal line and the fabrication method for semiconductor device

Publications (1)

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KR20100073436A true KR20100073436A (en) 2010-07-01

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