KR20100073398A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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KR20100073398A
KR20100073398A KR1020080132061A KR20080132061A KR20100073398A KR 20100073398 A KR20100073398 A KR 20100073398A KR 1020080132061 A KR1020080132061 A KR 1020080132061A KR 20080132061 A KR20080132061 A KR 20080132061A KR 20100073398 A KR20100073398 A KR 20100073398A
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film
layer
active region
high dielectric
semiconductor device
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Korean (ko)
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심재환
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to reduce a shrinkage effect by using high dielectric layer as a gate insulating layer. CONSTITUTION: A semiconductor substrate(100) comprises first and second active regions(102,104). An element isolation film(110) defines the first and the second active regions. The first and the second active region comprise a first gate pattern(150) and a second gate pattern(151). The first gate pattern is comprised of an interface, a high dielectric layer(122), a metal layer(124), and an amorphous silicon layer. The second gate pattern is comprised of a cap layer(117), the high dielectric layer, the metal layer, and the amorphous silicon layer.

Description

반도체 소자 및 그 제조 방법{Semiconductor device and method for manufacturing the same}Semiconductor device and method for manufacturing the same

본 발명은 반도체 소자에 관한 것으로, 특히 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a method of manufacturing the same.

최근 반도체 소자의 고집적화 및 대용량화의 경향에 따라 반도체 소자 제작에 이용되는 게이트 산화막의 두께는 급속도로 얇아지고 있다. 현재 가장 널리 사용되고 있는 게이트 산화막으로는 실리콘 산화막(SiO2)을 들 수 있다. 게이트 산화막으로서 실리콘 산화막은 열적안정성(thermal stability) 및 신뢰성(reliability)이 우수하며, 제작이 용이하다는 이유로 널리 사용되고 있다. 그러나 상기 실리콘 산화막은 상기 유전상수가 약 3.9로 그다지 높지 않기 때문에, 게이트 산화막의 두께 감소에 따른 게이트 누설전류의 급격한 증가 문제가 대두 되었다. 즉, 기존에 사용하던 실리콘 산화막으로는 반도체 소자의 고집적화에 따른 물리적인 두께 감소에 한계가 있다.In recent years, the thickness of the gate oxide film used for fabricating a semiconductor device is rapidly thinning due to the trend of high integration and large capacity of the semiconductor device. Currently, the most widely used gate oxide film is a silicon oxide film (SiO 2 ). As the gate oxide film, the silicon oxide film is widely used because of its excellent thermal stability and reliability and ease of manufacture. However, since the dielectric constant of the silicon oxide film is not so high as about 3.9, a problem of a sudden increase in gate leakage current due to a decrease in the thickness of the gate oxide film has arisen. In other words, the conventional silicon oxide film has a limitation in physical thickness reduction due to high integration of semiconductor devices.

본 발명이 이루고자 하는 기술적 과제는 게이트 절연막으로 고유전막을 사용함으로써 리키지 커런트(leakage current)를 줄일 수 있고, 반도체 소자의 집적도 향상에 부응하는 전기적인 특성을 위한 반도체 소자 및 그 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method of manufacturing the same for reducing electrical current by using a high-k dielectric layer as a gate insulating film, and for electrical characteristics corresponding to improved integration of semiconductor devices. have.

상기와 같은 과제를 달성하기 위한 본 발명의 실시 예에 따른 반도체 소자는 제 1 및 제 2 활성 영역을 포함하는 반도체 기판과, 상기 제 1 및 제 2 활성 영역들을 한정하는 소자 분리막과, 상기 제 1 활성 영역에 계면막, 고유전막, 금속막 및 아몰퍼스 실리콘층으로 구성된 제 1 게이트 패턴과, 상기 제 2 활성 영역에 계면막, 캡 층, 고유전막, 금속막 및 아몰퍼스 실리콘층으로 구성된 제 2 게이트 패턴을 포함하는 것을 특징으로 한다.In accordance with another aspect of the present invention, a semiconductor device includes a semiconductor substrate including first and second active regions, a device isolation layer defining the first and second active regions, and the first substrate. A first gate pattern composed of an interface film, a high dielectric film, a metal film, and an amorphous silicon layer in an active region, and a second gate pattern composed of an interface film, a cap layer, a high dielectric film, a metal film, and an amorphous silicon layer in the second active region Characterized in that it comprises a.

상기와 같은 과제를 달성하기 위한 본 발명의 실시 예에 따른 반도체 소자의 제조방법은 반도체 기판 상에 제 1 및 제 2 활성 영역들을 한정하는 소자 분리막을 형성하는 단계와, 상기 소자 분리막이 형성된 상기 반도체 기판 상에 계면막 및 캡 층을 순차적으로 형성하는 단계와, 상기 계면막 및 상기 캡 층을 상기 제 1 활성 영역을 노출하는 포토 레지스트 패턴을 이용한 식각 공정을 통해 상기 제 1 활성 영역의 캡 층을 제거하는 단계와, 상기 제 1 활성 영역의 캡 층이 제거된 상기 계면막 상에 금속막, 아몰퍼스 실리콘막을 순차적으로 형성하는 단계와, 상기 아몰퍼스 실리콘막 상에 게이트가 형성될 영역을 노출하는 포토 레지스트 패턴을 이용한 식각 공정을 통해 상기 제 1 활성 영역에 제 1 게이트 패턴과, 상기 제 2 활성 영역에 제 2 게이트 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming an isolation layer defining first and second active regions on a semiconductor substrate, and forming the semiconductor on which the isolation layer is formed Sequentially forming an interfacial film and a cap layer on a substrate, and etching the interfacial film and the cap layer using a photoresist pattern exposing the first active area. Removing, sequentially forming a metal film and an amorphous silicon film on the interface film from which the cap layer of the first active region is removed, and a photoresist exposing a region where a gate is to be formed on the amorphous silicon film. A first gate pattern in the first active region and a second gate pattern in the second active region through an etching process using a pattern Characterized in that it comprises the step of sex.

본 발명의 실시 예에 따른 반도체 소자 및 그 제조방법은 다음과 같은 효과가 있다.A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.

게이트 절연막으로 고유전막을 사용함으로써 쉬링키지 이펙트(shrinkage effect)를 줄임으로써 Sub-100㎚ 트랜지스터를 구현할 수 있다. 또한, 고유전막을 사용함으로써 리키지 커런트(leakage current)를 줄일 수 있고, 반도체 소자의 집적도 향상에 부응하는 전기적인 특성을 만족시킬 수 있다. Sub-100nm transistors can be implemented by reducing the shrinkage effect by using a high dielectric film as the gate insulating film. In addition, by using a high dielectric film, leakage current can be reduced, and electrical characteristics corresponding to improvement in the degree of integration of semiconductor devices can be satisfied.

그리고, 금속 물질의 게이트를 형성함으로써 Sub-100㎚ 트랜지스터에서도 소자의 Speed 향상을 기할 수 있다.By forming a gate of a metal material, the speed of the device can be improved even in a Sub-100 nm transistor.

NMOS 영역 및 PMOS 영역 간에 서로 다른 재료의 캡을 사용함으로써, 소자 내 특정 블럭(block)의 스피드 특성을 조절할 수 있다. By using caps of different materials between the NMOS region and the PMOS region, the speed characteristic of a particular block in the device can be adjusted.

이하, 본 발명의 기술적 과제 및 특징들은 첨부된 도면 및 실시 예들에 대한 설명을 통하여 명백하게 드러나게 될 것이다. 본 발명을 구체적으로 살펴보면 다음과 같다.Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

도 1은 본 발명에 따른 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the present invention.

도 1을 참조하면, 반도체 기판(100)에 제 1 및 제 2 활성 영역들(102, 104)을 한정하는 소자분리막(110)과, 제 1 및 제 2 활성 영역(102, 104)에 각각 형성된 제 1 및 제 2 게이트 패턴(150, 151)을 구비한다. Referring to FIG. 1, a device isolation layer 110 defining first and second active regions 102 and 104 in a semiconductor substrate 100 and formed in the first and second active regions 102 and 104, respectively. First and second gate patterns 150 and 151 are provided.

제 1 활성 영역(102)의 제 1 게이트 패턴(150)은 계면막(115), 고유전막(122), 금속막(124) 및 아몰퍼스 실리콘층(amorohous Si)(130)이 패터닝되어 형성되고, 제 2 활성 영역(104)의 제 2 게이트 패턴(151)은 계면막(115), 캡 층(117), 고유전막(122), 금속막(124) 및 아몰퍼스 실리콘층(amorohous Si)(130)이 패터닝되어 형성된다. The first gate pattern 150 of the first active region 102 is formed by patterning the interfacial film 115, the high dielectric film 122, the metal film 124, and the amorphous Si layer 130. The second gate pattern 151 of the second active region 104 may include an interface film 115, a cap layer 117, a high dielectric film 122, a metal film 124, and an amorphous Si layer 130. Is patterned and formed.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조방법을 나타낸 단면도들이다. 2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 2a를 참조하면, 반도체 기판(100)에 제 1 및 제 2 활성 영역들(102, 104)을 한정하는 소자 분리막(110)을 형성할 수 있다. 제 1 및 제 2 활성 영역들(102, 104)의 상부 표면들 및 소자 분리막(110)의 상부 표면은 실질적으로 동일한 평면상에 노출될 수 있다.Referring to FIG. 2A, an isolation layer 110 may be formed on the semiconductor substrate 100 to define the first and second active regions 102 and 104. The upper surfaces of the first and second active regions 102 and 104 and the upper surface of the device isolation layer 110 may be exposed on substantially the same plane.

반도체 기판(100)은 NMOS 영역 및 PMOS 영역을 포함하며, 실리콘 웨이퍼와 같은 실리콘 기판을 사용한다. 소자 분리막(110)은 얕은 트렌치 소자 분리(shallow trench isolation; STI) 기술을 이용하여 형성한다. 소자 분리막(110)은 실리콘 산화막과 같은 절연막으로 형성할 수 있다.The semiconductor substrate 100 includes an NMOS region and a PMOS region, and uses a silicon substrate such as a silicon wafer. The device isolation layer 110 is formed using a shallow trench isolation (STI) technique. The device isolation layer 110 may be formed of an insulating film, such as a silicon oxide film.

제 1 활성 영역(102)은 NMOS영역에 형성될 수 있으며, 제 2 활성 영역(104)은 PMOS영역에 형성될 수도 있다. 제 1 활성 영역(102)에는 P형 불순물 이온들이 주입될 수 있으며, 제 2 활성 영역(104)에는 N형 불순물 이온들이 주입될 수 있으나, 간략한 설명을 위하여 생략하기로 한다.The first active region 102 may be formed in the NMOS region, and the second active region 104 may be formed in the PMOS region. P-type impurity ions may be implanted into the first active region 102, and N-type impurity ions may be implanted into the second active region 104, which will be omitted for simplicity.

이어서, 소자 분리막(110)이 형성된 반도체 기판(100) 상에 계면막(interfacial layer)(115) 및 캡 층(Cap layer)(117)이 순차적으로 형성된다. Subsequently, an interfacial layer 115 and a cap layer 117 are sequentially formed on the semiconductor substrate 100 on which the device isolation layer 110 is formed.

계면막(115)은 열산화 공정에 의해 실리콘 산화막(SiO2) 또는 실리콘 산화 질화막(SiON)으로 형성된다. The interface film 115 is formed of a silicon oxide film (SiO 2 ) or a silicon oxynitride film (SiON) by a thermal oxidation process.

이어서, 캡 층(117) 상에 포토 레지스트 물질(도시하지 않음)을 도포한 후, 마스크를 이용한 사진 및 식각 공정을 통해 제 1 활성 영역(102)을 노출하는 포토 레지스트 패턴(120)을 형성한다. 포토 레지스트 패턴(120)을 마스크로 한 식각 공정을 통해 노출된 제 1 활성 영역(102)의 캡 층(117)을 제거하여 제 2 활성 영역(104)에만 캡 층(117)이 존재하게 된다. Subsequently, a photoresist material (not shown) is applied on the cap layer 117, and then a photoresist pattern 120 is formed to expose the first active region 102 through a photolithography and an etching process using a mask. . The cap layer 117 of the first active region 102 exposed through the etching process using the photoresist pattern 120 as a mask is removed so that the cap layer 117 exists only in the second active region 104.

여기서, 캡 층(117)은 산화란탄(La2O3) 물질로 형성된다. Here, the cap layer 117 is formed of a lanthanum oxide (La 2 O 3 ) material.

이어서, 도 2b와 같이 제 2 활성 영역(104) 상에 형성된 캡 층(117)을 포함하는 계면막(115) 상에 고유전막(122)을 형성한다. Subsequently, as shown in FIG. 2B, a high dielectric film 122 is formed on the interface film 115 including the cap layer 117 formed on the second active region 104.

여기서, 고유전막(122)은 실리콘 산화막(SiO2)의 유전 상수보다 높은 즉, 실리콘 산화막(SiO2)의 유전 상수 3.9보다 큰 유전 상수를 갖는 유전체 물질을 표현하기 위해 High-K Layer라는 용어로도 사용가능하다. Here, the specific conductive film 122 by the term High-K Layer to represent a dielectric material having a dielectric constant greater than a dielectric constant 3.9 of the high words, silicon oxide (SiO 2) than the dielectric constant of silicon oxide (SiO 2) Also available.

고유전막(122)은 원자층 증착법(atomic layer deposition, ALD)을 통해 하프니움 산화막(HfO2), 하프니움 산질화막(HfON), 하프니움 알루미늄 산화막(HfAlO), 하프니움 알루미늄 산질화막(HfAlON), 지르코늄산화(ZrO)막, 티타늄산화(TiO)막 중 어느 하나로 형성된다. The high dielectric film 122 is formed of hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium aluminum oxide (HfAlO), and hafnium aluminum oxynitride (HfAlON) through atomic layer deposition (ALD). , A zirconium oxide (ZrO) film, or a titanium oxide (TiO) film.

이어서, 도 2c와 같이, 고유전막(122)이 형성된 반도체 기판(100) 상에 금속막(124) 및 아몰퍼스 실리콘층(amorohous Si)(130)을 순차적으로 형성한다. Subsequently, as shown in FIG. 2C, the metal film 124 and the amorphous Si layer 130 are sequentially formed on the semiconductor substrate 100 on which the high dielectric film 122 is formed.

여기서, 금속막(124)은 구리 물질로 형성되지만, 이에 한정하는 것은 아니다.Here, the metal film 124 is formed of a copper material, but is not limited thereto.

이어서, 도 2d와 같이, 아몰퍼스 실리콘층(amorohous Si)(130)이 형성된 반도체 기판(100) 상에 포토 레지스트 물질(도시하지 않음)을 이용한 사진 및 식각 공정을 통해 제 1 및 제 2 활성 영역(102, 104)에 각각 제 1 및 제 2 게이트 패턴(150, 151)을 형성한다. Subsequently, as illustrated in FIG. 2D, the first and second active regions (not shown) may be formed using a photoresist material (not shown) on the semiconductor substrate 100 on which the amorphous silicon layer 130 is formed. First and second gate patterns 150 and 151 are formed on the 102 and 104, respectively.

제 1 활성 영역(102)의 제 1 게이트 패턴(150)은 계면막(115), 고유전막(122), 금속막(124) 및 아몰퍼스 실리콘층(amorohous Si)(130)이 패터닝되어 형성되고, 제 2 활성 영역(104)의 제 2 게이트 패턴(151)은 계면막(115), 캡 층(117), 고유전막(122), 금속막(124) 및 아몰퍼스 실리콘층(amorohous Si)(130)이 패터닝되어 형성된다. 여기서, 제 1 활성 영역(102)의 고유전막(122)이 캡역할을 하게 된다. The first gate pattern 150 of the first active region 102 is formed by patterning the interfacial film 115, the high dielectric film 122, the metal film 124, and the amorphous Si layer 130. The second gate pattern 151 of the second active region 104 may include an interface film 115, a cap layer 117, a high dielectric film 122, a metal film 124, and an amorphous Si layer 130. Is patterned and formed. Here, the high dielectric film 122 of the first active region 102 serves as a cap.

이와 같이, 게이트 절연막으로 고유전막을 사용함으로써 쉬링키지 이펙트(shrinkage effect)를 줄임으로써 Sub-100㎚ 트랜지스터를 구현할 수 있다. 또한, 고유전막을 사용함으로써 리키지 커런트(leakage current)를 줄일 수 있고, 반도체 소자의 집적도 향상에 부응하는 전기적인 특성을 만족시킬 수 있다. As such, by using the high-k dielectric layer as the gate insulating layer, the shrinkage effect may be reduced, thereby realizing a sub-100 nm transistor. In addition, by using a high dielectric film, leakage current can be reduced, and electrical characteristics corresponding to improvement in the degree of integration of semiconductor devices can be satisfied.

그리고, 금속 물질의 게이트를 형성함으로써 Sub-100㎚ 트랜지스터에서도 소 자의 Speed 향상을 기할 수 있다.In addition, by forming the gate of the metal material, the element speed can be improved even in the Sub-100 nm transistor.

NMOS 영역 및 PMOS 영역 간에 서로 다른 재료의 캡을 사용함으로써, 소자 내 특정 블럭(block)의 스피드 특성을 조절할 수 있다. By using caps of different materials between the NMOS region and the PMOS region, the speed characteristic of a particular block in the device can be adjusted.

이상에서 설명한 본 발명은 상술한 실시 예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 종래의 지식을 가진 자에게 있어 명백할 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1은 본 발명에 따른 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device according to the present invention.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조방법을 나타낸 단면도들이다. 2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

100 : 반도체 기판 102, 104 : 활성 영역100: semiconductor substrate 102, 104: active region

110 : 소자 분리막 115 : 계면층110 device isolation layer 115 interface layer

117 : 캡 층 122 : 고유전막117: cap layer 122: high dielectric film

124 : 금속막 130 : 아몰퍼스 실리콘막 124: metal film 130: amorphous silicon film

150, 151 : 게이트 패턴150, 151: Gate Pattern

Claims (5)

제 1 및 제 2 활성 영역을 포함하는 반도체 기판과,A semiconductor substrate comprising first and second active regions, 상기 제 1 및 제 2 활성 영역들을 한정하는 소자 분리막과,An isolation layer defining the first and second active regions; 상기 제 1 활성 영역에 계면막, 고유전막, 금속막 및 아몰퍼스 실리콘층으로 구성된 제 1 게이트 패턴과, A first gate pattern composed of an interface film, a high dielectric film, a metal film, and an amorphous silicon layer in the first active region; 상기 제 2 활성 영역에 계면막, 캡 층, 고유전막, 금속막 및 아몰퍼스 실리콘층으로 구성된 제 2 게이트 패턴을 포함하는 것을 특징으로 하는 반도체 소자.And a second gate pattern including an interface film, a cap layer, a high dielectric film, a metal film, and an amorphous silicon layer in the second active region. 제 1 항에 있어서,The method of claim 1, 상기 캡 층은 산화란탄(La2O3) 물질로 형성되며,The cap layer is formed of a lanthanum oxide (La 2 O 3 ) material, 상기 고유전막은 하프니움 산화막(HfO2), 하프니움 산질화막(HfON), 하프니움 알루미늄 산화막(HfAlO), 하프니움 알루미늄 산질화막(HfAlON), 지르코늄산화(ZrO)막, 티타늄산화(TiO)막 중 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자.The high dielectric film includes a hafnium oxide film (HfO 2 ), a hafnium oxynitride film (HfON), a hafnium aluminum oxide film (HfAlO), a hafnium aluminum oxynitride film (HfAlON), a zirconium oxide (ZrO) film, and a titanium oxide (TiO) film. A semiconductor device, characterized in that formed in any one of. 반도체 기판 상에 제 1 및 제 2 활성 영역들을 한정하는 소자 분리막을 형성하는 단계와,Forming an isolation layer defining a first and second active regions on the semiconductor substrate; 상기 소자 분리막이 형성된 상기 반도체 기판 상에 계면막 및 캡 층을 순차 적으로 형성하는 단계와,Sequentially forming an interface layer and a cap layer on the semiconductor substrate on which the device isolation layer is formed; 상기 계면막 및 상기 캡 층을 상기 제 1 활성 영역을 노출하는 포토 레지스트 패턴을 이용한 식각 공정을 통해 상기 제 1 활성 영역의 캡 층을 제거하는 단계와,Removing the cap layer of the first active region through an etching process using the photoresist pattern exposing the first active region to the interface layer and the cap layer; 상기 제 1 활성 영역의 캡 층이 제거된 상기 계면막 상에 금속막, 아몰퍼스 실리콘막을 순차적으로 형성하는 단계와,Sequentially forming a metal film and an amorphous silicon film on the interface film from which the cap layer of the first active region is removed; 상기 아몰퍼스 실리콘막 상에 게이트가 형성될 영역을 노출하는 포토 레지스트 패턴을 이용한 식각 공정을 통해 상기 제 1 활성 영역에 제 1 게이트 패턴과, 상기 제 2 활성 영역에 제 2 게이트 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a first gate pattern in the first active region and a second gate pattern in the second active region through an etching process using a photoresist pattern exposing a region where a gate is to be formed on the amorphous silicon film; A method for manufacturing a semiconductor device comprising the. 제 3 항에 있어서,The method of claim 3, wherein 상기 캡 층은 산화란탄(La2O3) 물질로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The cap layer is a method of manufacturing a semiconductor device, characterized in that formed of lanthanum oxide (La 2 O 3 ) material. 제 3 항에 있어서,The method of claim 3, wherein 상기 고유전막은 하프니움 산화막(HfO2), 하프니움 산질화막(HfON), 하프니움 알루미늄 산화막(HfAlO), 하프니움 알루미늄 산질화막(HfAlON), 지르코늄산화(ZrO)막, 티타늄산화(TiO)막 중 어느 하나로 형성되는 것을 특징으로 하는 반도 체 소자의 제조방법.The high dielectric film includes a hafnium oxide film (HfO 2 ), a hafnium oxynitride film (HfON), a hafnium aluminum oxide film (HfAlO), a hafnium aluminum oxynitride film (HfAlON), a zirconium oxide (ZrO) film, and a titanium oxide (TiO) film. Method for manufacturing a semiconductor device, characterized in that formed in any one of.
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