CN115332355A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN115332355A CN115332355A CN202211062256.6A CN202211062256A CN115332355A CN 115332355 A CN115332355 A CN 115332355A CN 202211062256 A CN202211062256 A CN 202211062256A CN 115332355 A CN115332355 A CN 115332355A
- Authority
- CN
- China
- Prior art keywords
- dielectric
- dielectric spacer
- gate structure
- gate
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first gate structure, a second gate structure and a second dielectric spacer. The first gate structure and the second gate structure adjacent to each other comprise a first dielectric spacer. The second dielectric spacer is located on the first dielectric spacer on one of the opposing sidewalls of the first gate structure and is not disposed on the first dielectric spacer of the second gate structure.
Description
The present application is a divisional application of the chinese invention patent application (application No. 201410126012.9, application date: 2014 03 and 31, title of the invention: semiconductor structure and its manufacturing method).
Technical Field
The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a metal oxide semiconductor and a method for fabricating the same.
Background
In order to form a designed integrated circuit on a semiconductor chip, a photomask is generally fabricated, a designed layout pattern is formed on the photomask, and the pattern on the photomask is transferred to a photoresist layer on the surface of the semiconductor structure by photolithography, so as to transfer the layout pattern of the integrated circuit to the semiconductor structure. The photolithography process can be said to be a very important critical step in the semiconductor fabrication process.
Since the critical dimension of the patterns that can be formed on the photomask is limited by the resolution limit of the exposure tool, when the integration level is gradually increased and the circuit pattern design is smaller and smaller, the optical proximity effect is easily generated when the exposure process is performed on the high-density arranged photomasks to transfer the patterns, which causes the deviation of the pattern transfer or the pattern deformation to affect the electrical characteristics of the product.
Disclosure of Invention
To solve the above-mentioned problems, according to an embodiment, a semiconductor structure is provided, which includes a first gate structure, a second gate structure, and a second dielectric spacer. The first gate structure and the second gate structure adjacent to each other comprise a first dielectric spacer. The second dielectric spacer is located on the first dielectric spacer on one of the opposing sidewalls of the first gate structure and is not disposed on the first dielectric spacer of the second gate structure.
According to another embodiment, a manufacturing method is proposed, comprising the following steps. Adjacent first and second gate structures are formed, each including a first dielectric spacer. A second dielectric spacer is formed on the first dielectric spacer on one of the opposing sidewalls of the first gate structure, and the second dielectric spacer is not disposed on the first dielectric spacer of the second gate structure.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
Fig. 1 to 4 illustrate a method of fabricating a semiconductor structure according to an embodiment.
Description of the main elements
102: first gate structure
104: second gate structure
106: semiconductor substrate
107: notch (S)
108: gate dielectric
110: gate electrode
112: first dielectric spacer
114: cover layer
116. 118: source/drain electrode
120: isolation structure
122: active region (active region)
124: outer region
126: second dielectric spacer
128: dielectric layer
130: opening of the container
132: masking layer
134. 136: side wall
138: voids
140: conductive contact
142: metal silicide
144: dielectric layer
146: conductive plug
T1, T2: thickness of
Detailed Description
Fig. 1 to 4 illustrate a method of fabricating a semiconductor structure according to an embodiment.
Referring to fig. 1, a first gate structure 102 and a second gate structure 104 are formed on a semiconductor substrate 106. The semiconductor substrate 106 is, for example, but not limited to, a silicon substrate, and other suitable substrate structures such as a silicon-on-insulator (soi) substrate may be selected. The first gate structure 102 and the second gate structure 104 each include a gate dielectric 108 formed on a semiconductor substrate 106, a gate electrode 110 formed on the gate dielectric 108, and a first dielectric spacer 112 formed on the gate electrode 110.
In one embodiment, the first gate structure 102 and the second gate structure 104 are high-k metal gates (high-k metal gates), i.e., the gate dielectric 108 is a high-k material and the gate electrode 110 is a metal material. The gate dielectric 108 is not limited to the flat film shown in fig. 1, and may be formed by a gate-first process, and the gate dielectric 108 may be a U-shaped film having the gate electrode 110 embedded therein, which may be formed by a gate-last process. The high-k material may include hafnium oxide (hafnium oxide), hafnium silicon oxide (hafnium silicon oxide), lanthanum oxide (lanthanum oxide), lanthanum aluminum oxide (lanthanum aluminate oxide), zirconium oxide (zirconium silicon oxide), tantalum oxide (tantalum oxide), titanium oxide (titanium oxide), barium strontium oxide (barium titanate oxide), barium titanium oxide (barium titanate oxide), strontium titanium oxide (strontium titanate oxide), yttrium oxide (yttrium titanate oxide), aluminum oxide (aluminum titanate oxide), lead scandium tantalum oxide (lead titanate oxide), lead zinc oxide (lead titanate oxide), and the like. The metal material of the gate electrode 110 may be a P-type work function metal or an N-type work function metal. For example, the P-type workfunction metal may comprise ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The N-type workfunction metal may include hafnium, zirconium, titanium, tantalum, aluminum, alloys of the above metals, and carbides of the above metals such as hafnium carbide (hafnium carbide), zirconium carbide (zirconia carbide), titanium carbide (titanium carbide), tantalum carbide (tantalum carbide), or aluminum carbide (aluminum carbide).
The first gate structure 102 and the second gate structure 104 may also include a capping layer 114 formed on an upper surface of the gate electrode 110. The first dielectric spacer 112 and the cap layer 114 may be, but are not limited to, the same material, such as a low dielectric constant material with a dielectric constant less than or equal to 7Nitride (Si) x N y E.g. SiN, si 3 N 4 Or SiCN, siCNO, siON, etc.).
Source/drain 116 (e.g., source) and source/drain 118 (e.g., drain) are disposed in or on the semiconductor substrate 106 on opposite sides of the second gate structure 104, respectively. The source/drain 116 and the source/drain 118 are of opposite conductivity type to the semiconductor substrate 106. Source/ drains 116 or 118 and isolation structures 120 are disposed in or on the semiconductor substrate 106 on opposite sides of the first gate structure 102, respectively. For example, the source/ drain 116, 118 may be formed by in-situ doped epitaxy or deposition on the semiconductor substrate 106 in the area where the recess 107 is etched. In other embodiments, the source/ drain 116, 118 may be formed in the semiconductor substrate 106 by doping using the first gate structure 102 and the second gate structure 104 as a mask.
The isolation structures 120 are not limited to trench structures (e.g., shallow trenches or deep trench structures) formed in the semiconductor substrate 106 as shown, and may be formed on the semiconductor substrate 106 using a field oxide process, or using other suitable insulating structures or doping structures of a conductivity type opposite to that of the semiconductor substrate 106.
The isolation structure 120 may be used to isolate the first gate structure 102 from the second gate structure 104 for other semiconductor devices. For example, the region between the inner sidewalls of the isolation structures 120 may be defined as an active region 122, and the region where the isolation structures 120 are located and the region outside the active region 122 may be an outer region 124, which may include, for example, an isolation region, an inactive region, and/or an active region of other semiconductor devices. The first gate structure 102 may be used as a dummy gate structure.
Second dielectric spacers 126 are formed in the active region 122 and the outer region 124. For example, the second dielectric spacers 126 may be conformally formed on the source/ drain 116, 118 and the first dielectric spacers 112, may also be formed on the semiconductor substrate 106, the isolation structure 120, or the capping layer 114 (not shown). The thickness T1 of the first dielectric spacer 112 is greater than the thickness T2 of the second dielectric spacer 126. The thickness T2 of the second dielectric spacer 126 may be less than 5nm. In one embodiment, the second dielectric spacer 126 is a metalOxides or materials with a high dielectric constant (high-k), such as a dielectric constant greater than 7. In one embodiment, the second dielectric spacer 126 is the same material as the gate dielectric 108, such as hafnium oxide (HfO) 2 And k is 25). In other embodiments, alumina (Al) may also be used 2 O 3 K value of 9), yttrium oxide (Y) 2 O 3 K value of 15), tantalum oxide (Ta) 2 O 5 K value of 22), titanium oxide (TiO) 2 K value of 80), lanthanum oxide (La) 2 O 3 K is 30; a-LaAlO 3 K value of 30), strontium titanium oxide (SrTiO) 3 K value of 2000), zirconium oxide (ZrO) 2 K value of 25), hafnium silicon oxide (HfSiO) 4 And k is 11).
A dielectric layer 128, such as an ILD0, is formed on the second dielectric spacers 126. The dielectric layer 128 may be a low dielectric constant (low-k) dielectric material including an oxide such as silicon dioxide (SiO) 2 ) Carbon-doped oxides (carbon-doped oxides; CDO), silicon nitride, organic polymers such as perfluorocyclobutane (perfluorobutane) or polytetrafluoroethylene (polytetrafluoroethylene), fluorosilicate glass (fluorosilicate glass; FSG), or organosilicates such as silsesquioxane (silsequioxane), siloxane (siloxane), or organosilicate glasses. After the formation of the second dielectric spacers 126 and the dielectric layer 128, a planarization process, such as a chemical mechanical polishing process, may be performed, which may appropriately selectively control a film, such as a material layer or a dielectric layer (not shown), stopping on the cap layer 114, or above the cap layer 114.
Referring to fig. 2A and 2B (wherein fig. 2B illustrates a top view of a portion of the semiconductor structure of fig. 2A), a mask layer 132 having an opening 130 is formed, according to an embodiment. In one embodiment, the opening 130 of the mask layer 132 is formed by patterning the mask layer 132 using a single photomask and using a photolithography and etching process. The mask layer 132 may comprise photoresist or other suitable material.
An etching process is performed to remove the dielectric layer 128 exposed by the opening 130 (fig. 1). In an embodiment, the etching process has a higher etching selectivity to the dielectric layer 128 than to the second dielectric spacer 126 (i.e., the etching rate of the etching process to the dielectric layer 128 is higher than that of the second dielectric spacer 126, or the second dielectric spacer 126 is not substantially etched, which is not repeated hereinafter), so that the second dielectric spacer 126 in the active region 122 can be retained while removing the dielectric layer 128. Portions covered by masking layer 132, such as dielectric layer 128 in outer region 124, are not removed. The etching process may be selected according to the materials of the dielectric layer 128 and the second dielectric spacers 126. The etching may be performed in any suitable manner, such as dry etching, wet etching, and the like, or a combination thereof.
Then, another etching process is performed to remove the second dielectric spacer 126 between the first gate structure 102 and the second gate structure 104 exposed by the opening 130 (fig. 1). The etching process has a higher etching rate for the second dielectric spacer 126 than for the first dielectric spacer 112 and the capping layer 114, thereby removing the second dielectric spacer 126 while retaining the first dielectric spacer 112 and the capping layer 114. Portions covered by the mask layer 132, such as the second dielectric spacers 126 on the sidewalls 134 and on the isolation structures 120 adjacent to the sidewalls 134 in the outer region 124, are not removed. The etching process may be selected according to the materials of the second dielectric spacer 126, the first dielectric spacer 112, and the cap layer 114. The etching may be performed in any suitable manner, such as dry etching, wet etching, and the like, or a combination thereof. In one embodiment, the etching process used to remove the second dielectric spacer 126 may use liquid ammonium hydroxide (NH), for example 4 OH) and hydrogen peroxide (hydrogen peroxide; h 2 O 2 ) The SC1 cleaning process of (1). The etch chemistry or etch solution used to remove the dielectric layer 128 may be different from the etch process used to remove the second dielectric spacers 126.
In one embodiment, after removing the dielectric layer 128 and the second dielectric spacer 126 (fig. 1) in the active region 122, the second dielectric spacer 126 and the dielectric layer 128 are only located on the sidewall 134 of the outer region 124 of the opposing sidewalls 134, 136 of the first gate structure 102, but not on the first dielectric spacer 112 of the second gate structure 104, nor on the sidewall 136 of the first gate structure 102 facing the second gate structure 104.
By removing the dielectric layer 128 and the second dielectric spacers 126 in the active region 122 (fig. 1), the first dielectric spacers 112 of the first and second gate structures 102 and 104 and the upper surfaces of the source/ drain regions 116 and 118 define a gap 138. Since the voids 138 are formed directly using the first gate structure 102 and the second gate structure 104 in a self-aligned manner, the single opening 130 of the mask layer 132 may be designed to have a large size, exposing the area where the plurality of voids 138 are located at a time. The large size of the opening 130 means that a single photomask used to define the opening 130 may also have large feature sizes, which is cheaper than a photomask with small feature sizes, thereby reducing manufacturing costs. The gap 138 is defined by the first gate structure 102 and the second gate structure 104, and therefore can be designed to have a small dimension (e.g., width). Without affecting the formation of the voids 138, the alignment of the openings 130 (or the photo mask) can be subject to large drift, which can avoid the yield reduction problem caused by the drift of the fabrication process, and in some embodiments, the voids 138 with desired features can be obtained without using multiple photolithography processes such as double photolithography and triple photolithography, which are generally used for patterning fine patterns, and the fabrication process is simple and fast.
Referring to fig. 3, the conductive material fills the gap 138 to form a conductive contact 140. The conductive material may be subjected to a planarization step, such as a chemical mechanical polishing process, which may be appropriately selectively controlled in the stop cap layer 114. As described above, the voids 138 for forming the conductive contacts 140 are formed on the source/drains 116, 118 between the first gate structure 102 and the second gate structure 104 by using a self-aligned process, so that the conductive contacts 140 can be electrically contacted with the source/drains 116, 118 as expected, and will not miss (mis-plating) on the gate electrodes 110 to cause unexpected circuits or short circuits, thereby avoiding the problem of reduced yield. The conductive material is not limited to metal such as gold, tungsten, and the like, and other materials having excellent conductivity can be suitably used. In some embodiments, a metal silicide 142 may optionally be formed on the source/drains 116, 118 using a metal silicide fabrication process.
Please refer toReferring to fig. 4, a dielectric layer 144 (e.g., ILD 1) may be formed, and conductive elements, such as conductive plugs 146, may be formed in the dielectric layer 144 to electrically contact the conductive contacts 140. Dielectric layer 144 may include an oxide, such as silicon dioxide (SiO) 2 ) Carbon-doped oxides (carbon-doped oxides; CDO), silicon nitride, organic polymers such as perfluorocyclobutane (perfluorobutane) or polytetrafluoroethylene (polytetrafluoroethylene), fluorosilicate glass (fluorosilicate glass; FSG), or organosilicates such as silsesquioxane (silsequioxane), siloxane (siloxane), or organosilicate glasses. The conductive plug 146 is not limited to metal such as gold, tungsten, etc., and other materials with good conductivity may be used appropriately. In one embodiment, the semiconductor structure is a fin-field-effect transistor (finfet).
The various materials described in the embodiments may be formed in any suitable manner, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and the like.
The concepts of the fabrication methods of the embodiments can be applied to various semiconductor structures, such as metal oxide semiconductors, DRAMs, SRAMs, logic, PRMs, etc., and also to products of 14nm or smaller generations.
In summary, although the present invention has been disclosed by the embodiments, the invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.
Claims (10)
1. A semiconductor structure, comprising:
the adjacent first gate structure and the second gate structure respectively comprise a first dielectric spacer, a gate dielectric and a gate electrode which are positioned on the gate dielectric;
a source/drain on opposite sides of the second gate structure, wherein an upper surface of the source/drain is above an upper surface of the gate dielectric of the second gate structure;
a metal silicide on the upper surface of the source/drain; and
a second dielectric spacer on the first dielectric spacer on one of the opposing sidewalls of the first gate structure and not disposed on the first dielectric spacer of the second gate structure.
2. The semiconductor structure of claim 1, wherein said first dielectric spacer is thicker than said second dielectric spacer.
3. The semiconductor structure of claim 1, being a fin-field-effect transistor (fin-field-effect transistor).
4. The semiconductor structure of claim 1, further comprising an isolation structure below said second dielectric spacer.
5. The semiconductor structure of claim 1, further comprising an isolation structure adjacent said one of said opposing sidewalls of said first gate structure having said second dielectric spacer thereon.
6. A method of manufacture, comprising:
forming a first gate structure and a second gate structure adjacent to each other, each of which comprises a first dielectric spacer, a gate dielectric and a gate electrode on the gate dielectric;
forming source/drain electrodes on opposite sides of the second gate structure, wherein an upper surface of the source/drain electrodes is above an upper surface of the gate dielectric of the second gate structure;
forming a metal silicide on the upper surface of the source/drain; and
a second dielectric spacer is formed on the first dielectric spacer on one of the opposing sidewalls of the first gate structure, the second dielectric spacer not being disposed on the first dielectric spacer of the second gate structure.
7. The method of claim 6, wherein the first dielectric spacer is thicker than the second dielectric spacer.
8. The method of claim 6, wherein the first gate structure and the second gate structure each further comprise a cap layer formed on an upper surface of the gate electrode.
9. The method of claim 6, further comprising forming an isolation structure below said second dielectric spacer.
10. The method of manufacturing of claim 6, further comprising forming an isolation structure adjacent to the one side of the opposing sidewalls of the first gate structure having the second dielectric spacer thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211062256.6A CN115332355A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211062256.6A CN115332355A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
| CN201410126012.9A CN104952915A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410126012.9A Division CN104952915A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115332355A true CN115332355A (en) | 2022-11-11 |
Family
ID=54167452
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410126012.9A Pending CN104952915A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
| CN202211062256.6A Pending CN115332355A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410126012.9A Pending CN104952915A (en) | 2014-03-31 | 2014-03-31 | Semiconductor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN104952915A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100307287B1 (en) * | 1998-11-20 | 2001-12-05 | 윤종용 | Manufacturing method of pad of semiconductor device |
| KR100441998B1 (en) * | 2002-07-06 | 2004-07-30 | 삼성전자주식회사 | Method for forming self-aligned contact hole in semiconductor device |
-
2014
- 2014-03-31 CN CN201410126012.9A patent/CN104952915A/en active Pending
- 2014-03-31 CN CN202211062256.6A patent/CN115332355A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN104952915A (en) | 2015-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102301251B1 (en) | A gate all around semiconductor device and a mehtod for fabricating the same | |
| TWI662627B (en) | Semiconductor device and fabrication method thereof | |
| KR102100790B1 (en) | Structure and method for metal gates with roughened barrier layer | |
| US10068770B2 (en) | Method and structure for semiconductor device having gate spacer protection layer | |
| US10515945B2 (en) | Method and structure for semiconductor mid-end-of-year (MEOL) process | |
| US9876116B2 (en) | Semiconductor structure and manufacturing method for the same | |
| CN107170825B (en) | Semiconductor device, fin field effect transistor device and forming method thereof | |
| US8357603B2 (en) | Metal gate fill and method of making | |
| US12021132B2 (en) | Gate patterning process for multi-gate devices | |
| KR102030241B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN106601814B (en) | Fin field effect transistor isolation structure and manufacturing method thereof | |
| CN107808849B (en) | Semiconductor element and manufacturing method thereof | |
| KR20160063210A (en) | Fin field effect transistor (finfet) device with controlled end-to-end critical dimension and method for forming the same | |
| US8802521B1 (en) | Semiconductor fin-shaped structure and manufacturing process thereof | |
| CN103633029B (en) | Semiconductor structure and manufacturing method thereof | |
| US11437286B2 (en) | Middle of line structures | |
| TWI762458B (en) | Contact structures of finfet devices, finfet devices and methods of forming the same | |
| CN118098979A (en) | Semiconductor element and manufacturing method thereof | |
| US11302534B2 (en) | Semiconductor structure with gate dielectric layer and fabrication method thereof | |
| TWI695477B (en) | Semiconductor structure and manufacturing method thereof | |
| CN110828377B (en) | Semiconductor element with asymmetric work function metal layer | |
| CN109755132B (en) | Semiconductor device and method for manufacturing the same | |
| US20210020635A1 (en) | Semiconductor structure and method of formation | |
| US10770360B2 (en) | Semiconductor structures and fabrication methods thereof | |
| CN115332355A (en) | Semiconductor structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |