KR20100071185A - Display panel and display device with the same - Google Patents

Abstract

PURPOSE: A display panel and a display device with the same are provided to improve response speed of a liquid crystal. CONSTITUTION: A display substrate(100) includes the first base substrate(101),the first common electrode(140), and a pixel electrode(160). The first common electrode is arranged on the first base substrate. The pixel electrode includes a plurality of slit patterns(161). An opposite substrate(200) includes the second base substrate(201) and the second common electrode(240). The second common electrode is arranged on the second base substrate. A liquid crystal layer(300) is interposed between the display substrate and the opposite substrate.

Description

DISPLAY PANEL AND DISPLAY DEVICE WITH THE SAME}

The present invention relates to a display panel and a display device having the same, and more particularly, to a display panel used for a liquid crystal display and a display device having the same.

In general, a liquid crystal display (LCD) displays grayscales by arranging liquid crystals by a voltage difference applied to a common electrode and a pixel electrode formed on two upper and lower substrates.

Since the liquid crystal display device implements an image by transmitting light only in a direction that is not shielded by the liquid crystal molecules of the liquid crystal layer, the viewing angle is relatively narrower than that of other display devices.

Accordingly, a patterned vertically alignment (PVA) mode in-plane switching (IPS) mode and a fringe field switching (FFS) mode have been developed to realize a wide viewing angle.

In the IPS mode, the pixel electrode and the common electrode are formed on the same plane so that the direction of the electric field is formed to have a horizontal electric field parallel to the substrate. The IPS mode rotates the liquid crystal molecules in a plane parallel to the substrate, so that the difference in the refractive anisotropy of the liquid crystal viewed by the observer is small and there are two liquid crystal layers having opposite directions of rotation of the liquid crystal molecules in the vertical cross section. The phase difference is compensated for to realize a wide viewing angle.

The FFS mode is the same as the IPS mode in terms of arranging liquid crystals using the horizontal electric field. However, in the FFS mode, the pixel electrode and the common electrode are formed in different layers to arrange liquid crystal molecules using two electric fields, a horizontal electric field and a vertical electric field. The FFS mode has a more advantageous structure than the IPS mode in terms of transmittance as liquid crystal molecules are arranged by the vertical electric field. In addition, in terms of the viewing angle, almost all liquid crystal molecules have the same characteristics as the IPS mode as they move in the horizontal direction in the same manner as the IPS mode.

Accordingly, the technical problem of the present invention has been made in view of the above, an object of the present invention is to provide a display panel for improving the response speed of the liquid crystal.

Another object of the present invention is to provide a display device having the display panel.

In order to achieve the above object of the present invention, a display panel according to an embodiment includes a display substrate, an opposing substrate, and a liquid crystal layer. The display substrate includes a first base substrate, a first common electrode disposed on the first base substrate, and a pixel electrode disposed on the first common electrode and including a plurality of slit patterns. The opposing substrate includes a second base substrate facing the first base substrate and a second common electrode disposed on the second base substrate. The liquid crystal layer is interposed between the display substrate and the counter substrate.

In an embodiment of the present invention, the second common electrode extends in a first direction parallel to the gate line formed on the first base substrate, and is spaced apart at regular intervals in a second direction perpendicular to the first direction.

In an exemplary embodiment of the present invention, the display panel is disposed between the pixel electrode and the liquid crystal layer and is disposed between the first alignment layer and the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. And a second alignment layer for horizontally aligning the liquid crystal in the layer.

In an exemplary embodiment of the present invention, the display panel is disposed between the pixel electrode and the liquid crystal layer and disposed between the first common alignment layer for vertically aligning the liquid crystal of the liquid crystal layer and between the second common electrode and the liquid crystal layer. And a second alignment layer for horizontally aligning the liquid crystal in the layer.

In an exemplary embodiment of the present invention, the display panel is disposed between the pixel electrode and the liquid crystal layer and is disposed between the first alignment layer and the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. A second alignment film for vertically aligning the liquid crystal of the layer is further included.

In an embodiment of the present invention, the opposing substrate further includes a metal part receiving a common voltage pulse, and the second common electrode is disposed on the metal part.

In accordance with another aspect of the present invention, a display device includes a display panel, a common electrode driver, a data driver, and a gate driver. The display panel includes a first common electrode disposed on a first base substrate on which a plurality of gate lines and data lines cross each other, and a pixel electrode disposed on the first common electrode and including a plurality of slit patterns. And an opposing substrate including a second common electrode disposed on a second base substrate facing the first base substrate, and a liquid crystal layer interposed between the display substrate and the opposing substrate. The common electrode driver applies a common voltage pulse having a second voltage level higher than that of the first voltage applied to the first common electrode to the second common electrode every time the frame starts. The data driver applies a data voltage to the pixel electrode after the first period. The gate driver sequentially applies gate signals to the gate lines after the first period.

In an embodiment of the present invention, the common electrode driver applies a common voltage pulse having the first voltage level to the second common electrode during the remaining sections except for the first section in one frame.

 In an exemplary embodiment of the present invention, the common electrode driver blocks and electrically floats the voltage applied to the second common electrode during the remaining sections except for the first section in one frame.

In an embodiment of the present invention, the second common electrode extends in a first direction parallel to the gate lines and is spaced apart at regular intervals in a second direction perpendicular to the first direction.

According to such a display panel and a display device having the same, a first common state is applied in a state in which the liquid crystals of the liquid crystal layer are instantaneously vertically applied by applying vertical electric fields to the first and second common electrodes during a set first period each time a frame is started. The arrangement speed of the liquid crystal can be controlled by applying a horizontal electric field to the electrode and the pixel electrode. Therefore, the response speed of the display device can be improved.

Hereinafter, exemplary embodiments of the display device of the present invention will be described in detail with reference to the drawings.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structure is shown in an enlarged scale than actual for clarity of the present invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof. In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment may include a display panel 400, a timing controller 500, a voltage generator 600, a data driver 700, a gate driver 800, and a common electrode. The driving unit 900 may be included.

The display panel 400 may include a display substrate 100, an opposing substrate 200 facing the display substrate 100, and a liquid crystal layer interposed between the display substrate 100 and the opposing substrate 200. ) May be included.

A plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersecting the gate lines GL1 to GLn are formed on the display substrate 100. A plurality of pixel parts is defined by the gate lines GL1 to GLn and the data lines DL1 to DLm. Each pixel unit may include a switching element TFT in which a gate electrode and a source electrode are respectively connected to a gate line and a data line, and a liquid crystal capacitor CLC and a storage capacitor CST electrically connected to the switching element. One end of the liquid crystal capacitor CLC is connected to the pixel electrode connected to the drain electrode of the switching element TFT, and the other end thereof is connected to the first common electrode to which the first common voltage Vcom1 is applied.

The timing controller 500 receives a control signal CONT and image data DATA provided from an external device such as a graphic controller (not shown). The control signal CONT may include a main clock signal MCLK, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a data enable signal DE, and the like. The timing controller 500 controls the driving timing of the first control signal 512 and the common electrode driver 900 for controlling the driving timing of the data driver 700 using the control signal CONT. A second control signal 514 for generating a third control signal 516 for controlling the driving timing of the gate driver 800 is generated. The first control signal 512 may include a horizontal start signal STH, a load signal TP, and a data clock signal DCLK. The second control signal 514 may include a first vertical start signal STV1. The third control signal 516 may include a second vertical start signal STV2, a gate clock signal GCLK, an output enable signal OE, and the like. The second vertical start signal STV2 is a signal delayed by a predetermined time with respect to the first vertical start signal STV1.

The voltage generator 600 generates driving voltages for driving the display panel 400. For example, the voltage generator 600 generates a reference gray voltage Vref for generating a pixel voltage and provides the reference gray voltage Vref to the data driver 700, and provides a gate on voltage Von and a gate off voltage Voff. It generates and provides it to the gate driver 800. In addition, the voltage generator 600 is applied to the first common voltage Vcom1 applied to the first common electrode formed on the display substrate 100 and the second common electrode applied to the second common electrode formed on the counter substrate 200. The common voltage Vcom2 is generated. The first common voltage Vcom1 is provided to the first common electrode of the display substrate 100. The voltage generator 600 provides the first and second common voltages Vcom1 and Vcom2 to the second common electrode driver 900.

The data driver 700 receives the first control signal 512 and the image data DATA from the timing controller 500, and receives the reference gray voltage Vref from the voltage generator 600. do. The data driver 700 converts the image data DATA into an analog data voltage using the reference gray voltage Vref and outputs the data voltages to the data lines DL1 to DLm.

The gate driver 800 uses the third control signal 516 provided from the timing controller 500 and the gate on and off voltages Von and Voff provided from the voltage generator 600. Gate signals for sequentially activating the gate lines GL1 to GLn are generated. The gate signals are output to the gate lines GL1 to GLn.

The common electrode driver 900 is electrically connected to a plurality of second common electrodes formed on the opposing substrate 200. The second common electrode driver 900 may receive the first or second common voltage Vcom1, which is provided from the voltage generator 600, in response to the second control signal 514 provided from the timing controller 500. A common voltage pulse having a Vcom2) level is generated and provided to the second common electrode.

For example, the common electrode driver 900 applies a common voltage pulse having the second common voltage Vcom2 level to the second common electrode during a preset first period every time the frame starts, and the first The common voltage pulse having the first common voltage Vcom1 level is applied to the second common electrode during the remaining sections except for the section.

The common electrode driver 900 may block the common voltage pulse applied to the second common electrode such that the second common electrode is electrically floated during the remaining period.

2 is a plan view illustrating a structure of a second common electrode according to an exemplary embodiment of the present invention.

1 and 2, the second common electrodes 240 according to the exemplary embodiment of the present invention are formed on the counter substrate 200 corresponding to each gate line. The second common electrodes 240 extend in a first direction D1 parallel to the gate line, and are spaced apart at regular intervals along a second direction D2 perpendicular to the first direction D1. do. For example, the second common electrodes 240 may be formed in a stripe type.

The common electrode driver 900 generates the common voltage pulse having the first and second common voltages Vcom1 and Vcom2 in response to the second control signal 514 to generate the second common electrode 240. Are output sequentially.

3 is a plan view illustrating a structure of a second common electrode according to another exemplary embodiment of the present invention.

1 and 3, the second common electrode 240 according to another embodiment of the present invention is formed on the counter substrate 200 corresponding to each gate line. The second common electrodes 240 extend in a first direction D1 parallel to the gate line and are spaced apart at regular intervals along a second direction D2 perpendicular to the first direction D1. Can be. For example, the second common electrodes 240 may be formed in a stripe type.

Each of the second common electrodes 240 may include a metal part 245 electrically connected to the common electrode driver 900 through the common electrode line CL. The metal part 245 may be formed of a metal material having a low electric resistance value such as aluminum (Al) and molybdenum (Mo). The metal part 245 receives the common voltage pulse provided from the common electrode driver 900 through the common electrode line CL.

As such, since the second common electrodes 240 are applied through the metal part 245 instead of directly applying the common voltage pulse, signal resistance due to an RC delay may be reduced. Can be reduced.

4 is an input / output waveform diagram of the gate driver and the common electrode driver illustrated in FIG. 1.

1 to 4, the common electrode driver 900 may receive a second common voltage during the first period T1 preset in response to the first vertical start signal STV1 provided from the timing controller 500. The common voltage pulse Vcp having the (Vcom2) level is sequentially applied to the second common electrodes 240. The common electrode driver 900 applies a first common voltage Vom1 level lower than the second common voltage Vcom2 level during the remaining period T2 except for the first period T1 in one frame. The common voltage pulse Vcp is sequentially applied to the second common electrodes 240. Here, when the level of the second common voltage Vcom2 is about 10V, the first period T1 to which the common voltage pulse having the second common voltage Vcom2 level is applied may be set to about 1 ms. When the level of the second common voltage Vcom2 is set to be greater than the 10V, the first section T1 is decreased, and when the level of the second common voltage Vcom2 is set to be less than the 10V, the first portion is reduced. The period T1 may be increased.

The gate driver 800 sequentially outputs a gate signal G to the gate lines GL1 to GLn in response to the second vertical start signal STV2 provided from the timing controller 500. The second vertical start signal STV2 is a signal delayed for a predetermined time from the first vertical start signal STV1.

FIG. 5 is a plan view according to an exemplary embodiment of the display panel illustrated in FIG. 1. FIG. 6 is a cross-sectional view taken along the line II ′ of FIG. 5.

5 and 6, the display panel 400 includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 interposed between the display substrate 100 and the opposing substrate 200. It may include.

The display substrate 100 includes a first base substrate 101, a gate line GL, a gate insulating layer 120, a data line DL, a switching element TFT, a first common electrode 140, and protective insulation. The layer 150, the pixel electrode 160, the first alignment layer 170, and the first polarizer 180 may be included.

The first base substrate 101 may be made of a transparent insulating material. For example, the first base substrate 101 may be a glass substrate, a soda lime substrate, a plastic substrate, or the like.

The gate line GL is formed on the first base substrate 101. The gate lines GL may extend in a first direction D1, and a plurality of gate lines GL may be arranged in parallel in a second direction D2 perpendicular to the first direction D1.

The gate insulating layer 120 is disposed on the gate electrode GE of the switching element TFT. The gate insulating layer 120 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

The data lines DL may extend in the second direction D2, and a plurality of data lines DL may be arranged in parallel in the first direction D1.

The switching element TFT includes the gate electrode GE, the source electrode SE, the semiconductor pattern 130, and the drain electrode DE. The gate electrode GE is electrically connected to the gate line GL, and the source electrode SE is electrically connected to the data line DL. The semiconductor pattern 130 is formed on the gate insulating layer 120 to correspond to the gate electrode GE. The semiconductor pattern 130 includes a semiconductor layer 130a and an ohmic contact layer 130b. The drain electrode DE is disposed spaced apart from the source electrode SE by a predetermined interval.

The first common electrode 140 is formed in the pixel area PA defined by the gate line GL and the data line DL. The first common electrode 140 is formed on the gate insulating layer 120. It may be made of the transparent conductive material. For example, the first common electrode 140 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

The protective insulating layer 150 is disposed on the first base substrate 101 on which the switching element TFT and the first common electrode 140 are formed. The protective insulating layer 150 may be formed of an inorganic material such as silicon nitride (SiNx) and silicon oxide (SiOx) in the same manner as the gate insulating layer 120. In addition, the protective insulating layer 150 may be formed of an organic material. A contact hole CNT exposing a part of the drain electrode DE is formed in the protective insulating layer 150.

The pixel electrode 160 may be disposed on the first base substrate 101 on which the protective insulating layer 150 is formed, and may be made of a transparent conductive material. For example, the pixel electrode 160 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or the like. The pixel electrode 160 may be electrically connected to the switching element TFT by contacting the drain electrode DE exposed through the contact hole CNT. The pixel electrode 160 includes a plurality of slit patterns 161. The slit patterns 161 extend in a direction substantially parallel to an extension direction of the data line DL.

The first alignment layer 170 is formed on the first base substrate 101 on which the pixel electrode 160 is formed. The first alignment layer 170 is a horizontal alignment layer that substantially aligns the optical axis of the liquid crystal included in the liquid crystal layer 300 with respect to the surface of the first base substrate 101. The first alignment layer 170 arranges the liquid crystal horizontally in an electroless state.

The first polarizer 180 is formed on an opposite surface of one surface of the first base substrate 101 on which the gate electrode GE is formed.

The opposing substrate 200 includes a second base substrate 201, a light shielding pattern 210, a color filter 220, an overcoating layer 230, a second common electrode 240, a second alignment layer 250, and a second The polarizer 260 may be included.

The second base substrate 201 may be made of a transparent insulating material in the same manner as the first base substrate 101.

The light blocking pattern 210 is disposed on the second base substrate 201 to block light. For example, the light blocking pattern 210 may be disposed to correspond to a region where the gate line GL, the data line DL, and the switching element TFT are formed.

The color filter 220 is disposed on the second base substrate 201 corresponding to the pixel area PA. The color filter 210 may include color filters of red, green, and blue.

The overcoat layer 230 is disposed on the second base substrate 201 on which the light blocking pattern 9 and the color filter 220 are formed. The overcoat layer 230 serves to planarize the opposing substrate 200. An example of the material for forming the overcoat layer 230 may be an acrylic resin.

The second common electrode 240 is formed on the second base substrate 201 on which the overcoat layer 230 is formed.

The second alignment layer 250 is formed on the second base substrate 201 on which the second common electrode 240 is formed. The second alignment layer 250 is a horizontal alignment layer that substantially aligns the optical axis of the liquid crystal included in the liquid crystal layer 300 with respect to the surface of the second base substrate 201. The first alignment layer 170 arranges the liquid crystal horizontally in an electroless state.

The second polarizing plate 260 is formed on an opposite surface of one surface of the second base substrate 201 on which the light blocking pattern 210 is formed. The polarization axis of the second polarizing plate 260 may be disposed to be substantially orthogonal to the polarization axis of the first polarizing plate 180. One of the first and second polarizers 260 may have a polarization axis parallel to the initial alignment direction of the liquid crystal.

The liquid crystal layer 300 includes a liquid crystal interposed between the display substrate 100 and the opposing substrate 200. The liquid crystals included in the liquid crystal layer 300 are horizontally arranged by the first and second alignment layers 250 in the electroless state. The liquid crystals included in the liquid crystal layer 300 are vertically arranged by voltages applied to the first and second common electrodes 140 and 240. That is, a vertical electric field is formed by voltages applied to the first and second common electrodes 140 and 240, and the liquid crystals are vertically arranged by the vertical electric field. A first common voltage is applied to the first common electrode 140, and a second common voltage greater than a level of the first common voltage is applied to the second common electrode 240. For example, a voltage of 0V may be applied to the first common electrode 14, and a voltage of 10V or more may be applied to the second common electrode 240. In the state in which the liquid crystals are arranged horizontally or vertically, light incident from the outside does not pass through the liquid crystal layer 300. Therefore, the display state of the display panel 400 is dark.

Meanwhile, a horizontal electric field is formed by the voltages applied to the first common electrode 140 and the pixel electrode 160, and the liquid crystal is formed on the polarization axis of the first or second polarizing plate 260 by the horizontal electric field. Inclined at a predetermined angle (eg, about 45 °). The first common voltage is applied to the first common electrode 140, and a data voltage is applied to the pixel electrode 160. The level of the data voltage may be about 4-5V. As such, when the liquid crystal is inclined at a predetermined angle with respect to the polarization axis of the first or second polarizing plate 260, light incident from the outside is transmitted through the liquid crystal layer 300. Therefore, the display state of the display panel 400 is in a bright state. In this case, a voltage substantially equal to or greater than the first common voltage Vocm1 applied to the first common electrode 140 may be applied to the second common electrode 240. In contrast, the second common electrode 240 may be electrically floating.

According to the present invention, after each frame starts, the liquid crystal included in the liquid crystal layer 300 is temporarily vertically applied by applying a voltage to the first and second common electrodes 140 and 240 during the set first period. The gray level is implemented by applying a voltage to the first common electrode 140 and the pixel electrode 160. As such, when a vertical electric field is applied to the first and second common electrodes 140 and 240, a horizontal electric field is applied to the first common electrode 140 and the pixel electrode 160. By applying a horizontal electric field to the 300, the liquid crystals may be arranged at a speed faster than the speed of arranging the liquid crystals in the same arrangement as the liquid crystal array direction of the bright state. This is because the instantaneous vertically aligned liquid crystals are relatively less affected by surface orientation energy when deformed into a twisted state.

In addition, when the gray to be displayed is changed from a light gray to a dark gray in a state where the liquid crystal is vertically arranged by applying a vertical electric field to the first and second common electrodes 140 and 240, the first common electrode 140. ) And no voltage is applied to the pixel electrode 160. In this case, the liquid crystals are rearranged in a horizontal arrangement again.

Although not shown in the drawing, when the light source is turned off while applying a vertical electric field to the first and second common electrodes 140 and 240, quasi-impulse driving is possible. Therefore, blurring of the screen can be improved, so that the display quality of the video can be improved.

7 is a cross-sectional view of another exemplary embodiment of the display panel illustrated in FIG. 1.

The display panel 400a illustrated in FIG. 7 is substantially the same as the display panel 400 described with reference to FIGS. 5 and 6 except for an initial arrangement direction of the liquid crystal included in the liquid crystal layer 300. Since the same members are denoted by the same reference numerals, overlapping detailed descriptions will be omitted.

Referring to FIG. 7, the display panel 400a may include a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 interposed between the display substrate 100 and the opposing substrate 200. Can be.

The display substrate 100 includes a first base substrate 101, a gate line GL, a gate insulating layer 120, a data line DL, a switching element TFT, a first common electrode 140, and protective insulation. The layer 150, the pixel electrode 160, the first alignment layer 170, and the first polarizer 180 may be included.

The opposing substrate 200 includes a second base substrate 201, a light shielding pattern 210, a color filter 220, an overcoating layer 230, a second common electrode 240, a second alignment layer 250a, and a second The polarizer 260 may be included.

The first alignment layer 170 may be a horizontal alignment layer that substantially aligns the optical axis of the liquid crystal included in the liquid crystal layer 300 with respect to the surface of the first base substrate 101.

The second alignment layer 250a may be a vertical alignment layer in which the optical axis of the liquid crystal included in the liquid crystal layer 30 is substantially perpendicular to the surface of the first base substrate 101.

Liquid crystals disposed adjacent to the first alignment layer 170 in the electroless state by the first and second alignment layers 170 and 250a are horizontally arranged with respect to the first base substrate 101, and the second liquid crystals are arranged horizontally. Liquid crystals disposed adjacent to the alignment layer 250a are vertically arranged with respect to the second base substrate 201.

Although not illustrated, the first alignment layer 170 may be a vertical alignment layer, and the second alignment layer 250a may be a horizontal alignment layer. In this case, the liquid crystals disposed adjacent to the first alignment layer 170 are vertically arranged, and the liquid crystals disposed adjacent to the second alignment layer 250a are horizontally arranged.

Even when the liquid crystal included in the liquid crystal layer 300 adopts a vertically and horizontally oriented structure as described above, the first and second common electrodes 140 and 240 for the first period set every frame start. The liquid crystal is vertically aligned by applying a vertical electric field to the first common electrode 140 and the pixel electrode 160 according to the gray level. Therefore, when the display state of the display panel 400a is changed from the bright state to the dark state or vice versa, the response speed of the liquid crystal may be improved. In addition, the switching speed between the gray levels can also be improved.

Although not shown in the drawings, the display panel 400a according to the present exemplary embodiment may include a first optical compensation film and / or the liquid crystal layer 300 disposed between the liquid crystal layer 300 and the first polarizing plate 180. ) And a second optical compensation film disposed between the second polarizing plate 260.

Table 1 below shows response characteristics of the display device according to the comparative example, and Table 2 illustrates response characteristics of the display device according to the present invention.

Referring to Table 1 and Table 2, the display device according to the comparative example is configured to form a common electrode and a pixel electrode on the display substrate, so that the liquid crystal contained in the liquid crystal layer is horizontally arranged in an electroless state. That is, no electrode was formed on the counter substrate.

Meanwhile, in the display device according to the present invention, the first common electrode and the pixel electrode are formed on the display substrate and the second common electrode is formed on the opposing substrate facing the display substrate as described with reference to FIGS. 5 to 7. The liquid crystal contained in the liquid crystal layer was configured to be horizontally arranged in an electroless state. In the display device according to the present invention, a vertical electric field is applied to the first and second common electrodes during a first period set every time a frame starts, and the first liquid crystals are vertically aligned in the first period. The electric field was driven by applying a horizontal electric field to the common electrode and the pixel electrode.

As shown in Table 1 and Table 2, when the response characteristics between grayscales were measured, the response time between grayscales was about 20ms to 30ms in the display device according to the comparison, whereas the display apparatus according to the present invention was used. It can be seen that less than 10ms. In addition, the slowest response time is 38.7 ms in the case of the display device according to the comparative example, whereas the slowest response time is 9.6 ms in the display device according to the present invention. It was confirmed that the improvement of about%.

When the vertical alignment of the liquid crystals by applying a vertical electric field to the horizontally aligned liquid crystal as in the present invention, the elastic energy is charged in the liquid crystal and the influence of the orientation energy is small. Therefore, when the gray level is expressed by applying a horizontal electric field in the state in which the liquid crystals are arranged vertically, it was confirmed that the rise time is faster. In addition, it was confirmed that the fall time for switching from a bright state to a dark state was also accelerated by applying a vertical electric field at the beginning of every frame.

Although described above with reference to preferred embodiments of the present invention, those skilled in the art or those skilled in the art without departing from the spirit and scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made within the scope of the invention.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is a plan view illustrating a structure of a second common electrode according to an exemplary embodiment of the present invention.

3 is a plan view illustrating a structure of a second common electrode according to another exemplary embodiment of the present invention.

4 is an input / output waveform diagram of the gate driver and the common electrode driver illustrated in FIG. 1.

FIG. 5 is a plan view according to an exemplary embodiment of the display panel illustrated in FIG. 1.

FIG. 6 is a cross-sectional view taken along the line II ′ of FIG. 4.

7 is a cross-sectional view of another exemplary embodiment of the display panel illustrated in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100 display substrate 101 first base substrate

140: first common electrode 160: pixel electrode

170: first alignment layer 200: opposing substrate

201: second base substrate 240: second common electrode

300: liquid crystal layer 500: timing control unit

600: voltage generator 700: data driver

800: gate driver 900: common electrode driver

Claims (14)

A display substrate including a first base substrate, a first common electrode disposed on the first base substrate, and a pixel electrode disposed on the first common electrode and including a plurality of slit patterns; An opposing substrate including a second base substrate facing the first base substrate and a second common electrode disposed on the second base substrate; And And a liquid crystal layer interposed between the display substrate and the opposing substrate. The method of claim 1, wherein the second common electrode extends in a first direction parallel to the gate line formed on the first base substrate, and is spaced apart at regular intervals in a second direction perpendicular to the first direction. Display panel. The liquid crystal display of claim 2, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. The liquid crystal display of claim 2, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to vertically align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. The liquid crystal display of claim 2, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to vertically align the liquid crystal of the liquid crystal layer. The method of claim 1, wherein the opposing substrate further comprises a metal portion receiving a common voltage pulse, The second common electrode is disposed on the metal part. A display substrate including a first common electrode disposed on a first base substrate on which a plurality of gate lines and data lines cross each other, a pixel electrode disposed on the first common electrode, and including a plurality of slit patterns; A display panel including an opposing substrate including a second common electrode disposed on a second base substrate facing the first base substrate, and a liquid crystal layer interposed between the display substrate and the opposing substrate; And A common electrode driver configured to apply a common voltage pulse having a second voltage level higher than a first voltage applied to the first common electrode to the second common electrode each time the frame starts; A data driver applying a data voltage to the pixel electrode after the first period; And And a gate driver configured to sequentially apply gate signals to the gate lines after the first period. The display device of claim 7, wherein the common electrode driver applies a common voltage pulse having the first voltage level to the second common electrode during the remaining sections except for the first section in one frame. 8. The display device of claim 7, wherein the common electrode driver blocks and electrically floats a voltage applied to the second common electrode during a period other than the first period in one frame. The display device of claim 7, wherein the second common electrode extends in a first direction parallel to the gate lines and is spaced at a predetermined interval in a second direction perpendicular to the first direction. The liquid crystal display device of claim 8, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. The liquid crystal display of claim 8, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to vertically align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer. The liquid crystal display device of claim 8, further comprising: a first alignment layer disposed between the pixel electrode and the liquid crystal layer to horizontally align the liquid crystal of the liquid crystal layer; And And a second alignment layer disposed between the second common electrode and the liquid crystal layer to vertically align the liquid crystal of the liquid crystal layer. The display apparatus of claim 7, wherein the counter substrate further includes a metal part electrically connected to the common electrode driver through a common electrode line to receive the common voltage pulse. The second common electrode is disposed on the metal part.

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