KR20100070586A - Manufacturing method of junction for nonvolatile memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing the junction region of a nonvolatile memory device is provided to prevent the cycling property of the nonvolatile memory device from deteriorating by reinforcing dopants which are contained in the junction overlap of word-lines adjacent to select-lines. CONSTITUTION: An element isolation region(A) and an active region(B) are defined in a semiconductor substrate. An element isolation structure(107) is formed in the element isolation region. Select-lines and word-lines(WL) are formed on the semiconductor substrate. Dopants are implanted into the active region in order to form a junction region(101a). Dopants are injected into the edge part of word-lines which is adjacent to the select-lines.

Description

Manufacturing method of junction for nonvolatile memory device

The present invention relates to a method for forming a junction region of a nonvolatile memory device, and in particular, to improve the amount of dopants included in the junction overlap of a word line adjacent to a select line, thereby improving deterioration of cycling characteristics of the nonvolatile memory device. The present invention relates to a method for forming a junction region of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

1 is a diagram for describing a conventional nonvolatile memory device. Referring to FIG. 1, a conventional nonvolatile memory device is formed on an upper portion of a semiconductor substrate in which device isolation regions A and active regions B are alternately defined.

A plurality of string structures are formed on the semiconductor substrate including the device isolation region A and the active region B. FIG. Each string structure includes a drain select transistor having a drain connected to a bit line, a source select transistor having a source connected to a common source line, a plurality of memory cells connected in series between a drain select transistor, and a source select transistor. This string structure is electrically isolated in parallel with the device isolation structure 17 formed in the device isolation region A therebetween. In string structures formed in parallel, the gates of the drain select transistors or the gates of the source select transistors are connected to become a select line, and the gates of the memory cells are connected in parallel to be word lines WL, respectively. The select line includes a drain select line DSL to which gates of the drain select transistors are connected and a source select line SSL to which gates of the source select transistors are connected. Hereinafter, the word line WL adjacent to the drain select line DSL and the source select line SSL is defined as an edge word line.

The drain select line DSL, the source select line SSL, and the word line WL form the device isolation structure 17 in the device isolation region A of the semiconductor substrate, and then include the device isolation structure 17. It is formed by depositing a conductive film on top of a semiconductor substrate and etching the conductive film. In this case, the drain select line DSL, the source select line SSL, and the word line WL are formed to cross the device isolation structures 17. The first interval l1 defined between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL is adjacent to each other. Wider than the second interval l2 defined between them. Therefore, since the wide part is etched at a higher speed during the etching process, the drain select line DSL and the edge word during the etching process to form the drain select line DSL, the source select line SSL, and the word line WL. The conductive isolation layer 17 may be quickly etched between the line WL and between the source select line SSL and the edge word line WL to expose the device isolation structure 17. The insulation of the device isolation structure 17 exposed between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL is adjacent to each other. (WL) are lost during the further etching process to ensure complete separation. As a result, the height of the isolation structure 17 is between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL than between the word lines WL. Lower in

Meanwhile, the source select transistor, the drain select transistor, and the memory cells are connected in series through the junction region 11a. The junction region 11a is formed by injecting dopants in a direction perpendicular to the semiconductor substrate using the select line SL and the word line WL as masks. At this time, the dopant implanted into the device isolation structure 17 and the active region B is diffused into the active region B below both sides of the select line and the word line WL through a subsequent thermal process. Due to diffusion of the dopant, a junction overlap is formed in which the gate and the junction region 11a overlap.

The dopant implanted into the device isolation structure 17 formed between the drain select line DSL and the word line WL and between the source select line SSL and the word line WL is relatively low. Due to the diffusion does not form a junction overlap, but spreads below the junction overlap. Therefore, the amount of dopant included in the junction overlap is insufficient among the junction regions 11a on one side of the word line WL adjacent to the drain select line DSL and the source select line SSL. In addition, the amount of dopants included in the junction overlap decreases as cycling, which is an erase and write operation of the nonvolatile memory device, is repeated, so that the junction overlap of the word line WL adjacent to the drain select line DSL and the source select line SSL is reduced. The amount of dopant contained in the layer is further insufficient. When the amount of dopant included in the junction overlap is insufficient, the threshold voltage shift is increased, which causes a malfunction of the nonvolatile memory device.

The present invention provides a method of forming a junction region of a nonvolatile memory device capable of improving the deterioration of cycling characteristics of the nonvolatile memory device by improving the amount of dopant included in the junction overlap of the word line adjacent to the select line.

According to an embodiment of the present disclosure, a method of forming a junction region of a nonvolatile memory device includes forming a device isolation structure in a device isolation region of a semiconductor substrate in which device isolation regions and active regions are alternately defined, and including a device isolation structure. Forming select lines and word lines that cross the device isolation structure and the active region on the substrate, and forming a junction region by implanting a dopant into the active region using the select lines and the word lines as a mask; A second implantation step of injecting a dopant into a junction region below one side of an edge word line adjacent to a select line among the lines, and a channel region defined in an active region below the word line and facing each other Diffusing the dopant into the junction region superimposed on both sides.

In the first implantation step, the dopant is implanted perpendicularly to the semiconductor substrate.

In the second implantation step, the dopant is implanted at an inclined angle with respect to the semiconductor substrate.

The inclined angle is preferably set so that the junction region under the other side of the edge word line and the junction region under the word lines other than the edge word line can be blocked by the word lines.

The dopant amount injected in the second injection step is preferably 1/10 to 1/2 of the amount of dopant injected in the first injection step.

The dopant includes at least one of phosphorus (P) or arsenic (As).

The select line includes a drain select line and a source select line facing each other with a plurality of word lines interposed therebetween.

The spacing between the select line and the word lines adjacent to the select line is preferably wider than the spacing between neighboring word lines.

In the forming of the select lines and the word lines, the height of the device isolation structure between the select line and the word line adjacent to the select line is lower than the height of the device isolation structure between the adjacent word lines.

The forming of the device isolation structure may include forming a tunnel insulating film and a first conductive film on an upper portion of the semiconductor substrate, a tunnel insulating film and a first conductive film on an upper portion of the active region, and forming a trench in the device isolation region. Etching the first conductive film and the semiconductor substrate, and filling the inside of the trench with an insulator.

The present invention can reduce the amount of threshold voltage shift after cycling by reinforcing the dopant of the cell junction region adjacent to the select line by adjusting the angle without using a separate ion implantation mask. It can be improved.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

2 is a layout diagram illustrating a method of forming a junction region in a nonvolatile memory device according to the present invention. 3A to 3D are cross-sectional views taken along the line I-I 'of FIG. 2 to illustrate a method of forming a junction region of a nonvolatile memory device according to the present invention.

2 and 3A, select lines and word lines WL are formed on the semiconductor substrate 101 on which the device isolation structure 107 is formed to cross the device isolation structure 107. The select line includes a drain select line DSL and a source select line SSL, and a plurality of word lines WL are formed between the drain select line DSL and the source select line SSL. Hereinafter, a method of forming the device isolation structure 107 and a method of forming the select line and the word line WL will be described in more detail. Hereinafter, the word line WL adjacent to the drain select line DSL and the source select line SSL is defined as an edge word line.

In the semiconductor substrate 101, the device isolation region A and the active region B are alternately defined. The tunnel insulating film 103 and the floating conductive first conductive film 105 are stacked on the semiconductor substrate 101. Thereafter, the tunnel insulating film 103 and the first conductive film are formed so that the tunnel insulating film 103 and the first conductive film 105 remain on the active region B, and trenches are formed in the device isolation region A. 105 and the semiconductor substrate 101 are etched. In this case, an element isolation mask (not shown) formed on the floating gate layer 105 may be used as an etching barrier. After the trench is formed in the device isolation region A of the semiconductor substrate 101 by the above-described etching process, an insulating material is formed on the semiconductor substrate 101 including the trench to have a sufficient thickness so that the inside of the trench is filled with the insulating material. Planarize the surface of the insulation. Through such a series of processes, the device isolation structure 107 may be formed in the device isolation region A. FIG. The device isolation mask may be removed after the device isolation structure 107 is formed.

The tunnel insulating layer 103 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by a wet oxidation or dry oxidation process. The first conductive layer 105 is used as a floating gate of the nonvolatile memory device and may be formed using a polysilicon layer. Insulators used in the device isolation structure 107 include oxide-based materials, for example High Temperature Oxide (HTO), High Density Plasma (HDP) oxide, TEOS (Tetra Ethyl Ortho Silicate), BPSG (Boron-Phosphorus Silicate Glass) or USG (Undoped Silicate Galss) have.

After the device isolation structure 107 is formed, the dielectric film 109, the second conductive films 111 and 113, and the gate hard mask pattern 115 are stacked on the semiconductor substrate including the device isolation structure 107. . Thereafter, the second conductive layers 111 and 113, the dielectric layer 109, and the first conductive layer 105 are etched by an etching process using the gate hard mask pattern 115 as an etching barrier. Accordingly, the gate pattern 117 having the first conductive film 105, the dielectric film 109, and the second conductive films 111 and 113 stacked on the tunnel insulating film 103 formed on the semiconductor substrate 101. Is formed. The gate hard mask pattern 115 may remain in the gate pattern 117 without being removed after the gate pattern 117 is formed. In addition, the second conductive layers 111 and 113 of the string structure arranged side by side are connected to each other and intersect the word isolation structure 107 and the word line WL or the drain select line DSL or the source select line SSL. Becomes

The dielectric film 109 may be formed by stacking an oxide film / nitride film / oxide film by using a low pressure chemical vapor deposition (LPCVD) method or an atomic layer deposition (ALD) method. More specifically, the oxide film may be a hot temperature oxide (HTO) film formed by mixing N ₂ O gas with DCS (SiH ₂ Cl ₂ ). The nitride film may be formed by mixing NH ₃ gas with DCS (SiH ₂ Cl ₂ ). In addition, the dielectric layer 109 may be formed using either Hf or Al ₂ O ₃ having a high dielectric constant while the nonvolatile memory device is highly integrated. In addition, contact holes are formed in the dielectric layer 109 in the region where the drain select line DSL and the source select line SSL are to be formed to electrically connect the first conductive layer 103 and the second conductive layers 113 and 115. Connect

The second conductive films 111 and 113 are conductive films for control gates. The second conductive layer may be formed in a stacked structure of the upper layer 113 to improve the resistance of the lower layer 111 and the lower layer 111. The lower layer 111 may be formed using polysilicon or amorphous silicon, and the upper layer 113 may be formed of tungsten silicide layer WSix, tungsten W, or cobalt silicide layer CoSix. It can be formed using a film containing a metal.

The gate hard mask pattern 115 is a pattern defining a region in which the word line WL, the drain select line DSL, and the source select line SSL are to be formed. The gate hard mask pattern 115 is formed by using SiON or TEOS (Tetra Ethyl Ortho Silicate). can do.

The first interval l1 defined between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL is a word line WL in order to minimize interference. It is set to be wider than the second interval l2 defined between them. For example, the first interval l1 is set to be two or more times the second interval l2. Since the first interval l1 is wider than the second interval l2, the etching rate is different in the etching process for forming the drain select line DSL, the source select line SSL, and the word lines WL. . Due to this difference in etching speed, the insulating film of the device isolation structure 107 formed between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL is lost. As a result, between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL than the height of the device isolation structure 107 formed between the word lines WL. The height of the formed device isolation structure 107 is lowered.

After the above-described gate pattern 117 is formed, defects generated on both sides of the gate pattern 117 may be removed during the etching process for forming the gate pattern 117 by performing a reoxidation process.

Thereafter, a first implantation step of implanting dopants in a direction perpendicular to the semiconductor substrate 101 is performed to form the junction region 101a. In the first implantation step, the dopant is implanted perpendicularly to the semiconductor substrate 101. Therefore, the drain select line DSL, the source select line SSL, and the word line WL serve as masks in the first injection step. As a result, in the first implantation step, the dopant is not blocked by the drain select line DSL, the source select line SSL, and the word line WL serving as a mask, and the device isolation structure 107. Is injected into. Here, the dopant includes phosphorus (P) or arsenic (As).

The dopant implanted in the first implantation step is diffused through heat generated in a subsequent process or through a separate annealing process. The diffusion of the dopant causes the junction region 101a to overlap both sides of the word line WL, resulting in a cell junction overlap. At this time, it is preferable to control the ion implantation depth Rp (Projected Range) in the first implantation step so that the dopant is not diffused in the entire channel region under the gate pattern 117. For example, in the first implantation step, the ion implantation depth may be controlled to 150 kPa or less. At the same time the ion implantation energy can be controlled to 15KeV. As such, the dopant implanted by controlling the ion implantation depth may be diffused only in the lower portions of both sides of the word line WL without being diffused in the entire lower portion of the word line WL even when diffused in a subsequent process. Therefore, the junction region 101a including the cell junction overlap region is separated from each other with the channel region defined in the active region overlapping the lower portion of the word line WL interposed therebetween.

On the other hand, the device isolation structure 107 between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL has device isolation between the word lines WL. Lower than structure 107. Therefore, the dopant implanted into the device isolation structure 107 between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL should form a cell junction overlap. It does not spread to the part, but to spread below it. Accordingly, the dopant amount of the cell junction overlap region X on one side of the edge word line WL adjacent to the source select line SSL or the drain select line DSL is the cell junction overlap region Y on the other side of the edge word line WL. It is less than dopant amount of). The present invention reinforces the dopant in the cell junction overlap region X on one side of the edge word line WL. Detailed description thereof will be described later with reference to FIG. 3B.

Referring to FIGS. 2, 3B, and 3C, a dopant is formed in an active region B below one side of the edge word line WL to reinforce the dopant of the cell junction overlap region X on one side of the edge word line WL. A second injection step is performed. At this time, the dopant is preferably injected in a dose amount in the range of 1/10 to 1/2 as compared with the first injection step.

In the second implantation step, the dopant may be implanted at a first angle θ1 that is inclined with respect to the semiconductor substrate 101. In this case, the first angle θ1 should be set such that the dopant is injected only into the active region B below one side of the edge word line WL. That is, the first angle θ1 should be set such that the dopant is injected only into the cell junction overlap region X below one side of the edge word line WL. On the other hand, the first angle θ1 should be set so as not to be injected into the cell junction overlap region Y under the other side of the edge word line WL and the cell junction overlap region under the other word lines WL other than the edge word line. do. To this end, the first angle θ1 should be set smaller than the second angle θ2 defined by the second interval l2 between the word lines WL and the height H of the gate pattern 117. When the dopant is implanted at the first angle θ1, the cell junction overlap region Y and the remaining word lines WL other than the edge word line are formed in the active region B under the other side of the edge word line WL. The lower active region B is blocked by the word line WL so that no additional dopant is injected.

According to the present invention, since the word lines WL act as a mask even if a separate ion implantation mask pattern (for example, a photoresist pattern) is not formed by implanting the dopant at the first angle θ1, the edge word line WL The dopant may be additionally injected only into the cell junction overlap region X formed at one side of the substrate. Accordingly, the present invention can uniformize the dopant amount of the cell junction overlap region X formed on one side of the edge word line WL and the cell junction overlap region Y formed on the other side of the edge word line WL in a simplified manner. .

In addition, it is preferable to control the ion implantation depth in the second implantation step so that the dopant is not diffused through the channel region under the gate pattern 117 through the subsequent thermal process. For example, in the second implantation step, the ion implantation depth may be controlled to 150 μm or less.

The second implantation step may be performed in a symmetrical direction with respect to the drain select line DSL and the source select line SSL.

2 and 3D, spacers 119 are formed on sidewalls of the gate pattern 117. The spacers 119 adjacent between the word lines WL may be connected to each other to fill the gaps between the word lines WL since the spacers 119 adjacent to each other are narrow. The spacer 119 is a subsequent contact hole forming process for exposing the junction region 101a between the drain select line DSL and the edge word line WL and between the source select line SSL and the edge word line WL. Serves to prevent the gate pattern 117 from being exposed. Although not illustrated, the spacer 119 is formed on sidewalls of the gate pattern formed in the peripheral circuit region outside the memory cell region.

After the spacer 119 is formed, a dopant may be further injected into the junction region of the peripheral region using the spacer 119 and the gate pattern as a mask to form the junction region of the peripheral region in a double structure. That is, the junction region of the peripheral region is a double region including a lightly doped drain (LDD) region having a first concentration and a second junction region having a second concentration higher than the first concentration by a dopant which is additionally injected after formation of the spacer 119. It is formed into a structure.

After implanting the dopants for forming the junction region 101a of the memory cell region and the junction region of the peripheral region, an annealing process for adjusting the depth of the junction region 101a or activating the dopant is performed. When the annealing process is performed, dopants of the junction region 101a are diffused to overlap the junction regions 101a on both sides of the word line WL to form cell junction overlaps. In this case, the cell junction overlaps overlapped on both sides of the word line WL are not formed in the entire channel region through the ion implantation depth adjusted during dopant implantation, but are spaced apart from each other with the channel region interposed therebetween.

As described above, the present invention provides a threshold voltage shift after cycling by additionally injecting a dopant into an active region below one side of an edge word line adjacent to the drain select line and the source select line by adjusting the angle without using a separate ion implantation mask. The amount can be reduced, and the erase speed and the read operation failure can be improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a view for explaining a conventional nonvolatile memory device.

2 is a layout for explaining a method for forming a junction region of a nonvolatile memory device according to the present invention;

3A to 3D are cross-sectional views taken along the line “I-I '” of FIG. 2 to illustrate a method of forming a junction region of a nonvolatile memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 103 tunnel insulating film

105: dielectric film 107: device isolation structure

109 and 111: second conductive film 113: gate hard mask pattern

115: gate pattern 117: spacer

101a: junction area X, Y: cell capturing overlap area

A: device isolation region B: active region

SL: Select Line WL: Word Line

Claims (10)

Forming a device isolation structure in the device isolation region of the semiconductor substrate in which device isolation regions and active regions are alternately defined; Forming select lines and word lines intersecting the device isolation structure and the active region on the semiconductor substrate including the device isolation structure; A first implantation step of forming a junction region by implanting a dopant into the active region using the select lines and the word lines as a mask; A second implantation step of implanting a dopant into the junction region below one side of an edge word line adjacent to the select line among the word lines; And And diffusing the dopant into the junction regions facing each other with a channel region defined in the active region below the word line and overlapping both sides of the word line. The method of claim 1, And the dopant is implanted perpendicularly to the semiconductor substrate in the first implantation step. The method of claim 1, And the dopant is implanted at an inclined angle with respect to the semiconductor substrate in the second implantation step. The method of claim 3, wherein The inclined angle is a junction region of a nonvolatile memory device configured to allow the junction region under the other side of the edge word line and the junction region under the word lines other than the edge word line to be blocked by the word lines. Formation method. The method of claim 1 And the dopant amount implanted in the second implantation step is 1/10 to 1/2 of the amount of dopant implanted in the first implantation step. The method of claim 1, The dopant includes at least one of phosphorus (P) and arsenic (As). The method of claim 1, The select line may include a drain select line and a source select line facing each other with the plurality of word lines interposed therebetween. The method of claim 1, And a spacing between the select line and the word lines adjacent to the select line is wider than a spacing between adjacent word lines. The method of claim 1, In the forming of the select lines and the word lines And a height of the device isolation structure between the select line and the word line adjacent to the select line is lower than a height of the device isolation structure between the adjacent word lines. The method of claim 1, Forming the device isolation structure is Forming a tunnel insulating film and a first conductive film on the semiconductor substrate; Etching the tunnel insulating film, the first conductive film and the semiconductor substrate so that the tunnel insulating film and the first conductive film remain on the active region, and a trench is formed in the device isolation region; And And filling the inside of the trench with an insulator.

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