KR20100068663A - Method manufacturing semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to improve electrical connection reliability between the semiconductor package and an external device by controlling the thickness of the external device based on the thickness of a conductive layer. CONSTITUTION: A semiconductor chip is flip-chip bonded to a rearranged wiring layer(120). A sealing material(150) hermetically seals the semiconductor chip. A connection unit(161) is arranged on the rearranged wiring layer. A solder ball(162) is arranged on the connection unit. The connection unit is a metal post with a thickness range of 100 to 500um.

Description

Semiconductor package and method for manufacturing same

The present invention relates to a method for manufacturing a semiconductor package, comprising: forming a rearrangement wiring layer on a conductive layer, mounting a semiconductor chip on the rearrangement wiring layer, and etching the conductive layer to electrically connect the external device to an external device. A semiconductor package to be formed and a manufacturing method thereof.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables this product design goal is the semiconductor package.

The semiconductor package is a technology for efficiently packaging devices used in electronic products, and is being developed in various forms as it is a technology that will determine the performance of semiconductor devices and the price, performance, and reliability of the final product.

Semiconductor packages have been manufactured by flip chip processes using bump ball technology for the electrical connection between semiconductor chips or between semiconductor chips and substrates. In this bump ball technology, there is a problem that the number of input / output pads and chip size of the package is limited due to the limitation of the miniaturization of the bump ball. That is, when the package is miniaturized or the number of input / output pads increases, the package has a limit in accommodating the number of solder balls, the final input / output terminals, in the upper surface of the semiconductor chip.

In order to improve this, a package has been developed such as an embedded structure in which a semiconductor chip is mounted inside a circuit board or a fan-out structure in which solder balls, which are final input / output terminals of the semiconductor chip, are disposed on an outer circumferential surface of the semiconductor chip.

Here, the package of the embedded structure or the fan-out structure is manufactured by a build-up method in which a metal layer is built up from an electrical contact pattern of the semiconductor chip after mounting the semiconductor chip. In this case, thermal expansion coefficient difference (CTE) and warpage between the substrate and the semiconductor chip may occur in the build-up process, in particular, a cure process and a lamination process. As a result, when a fine pitch semiconductor chip is mounted, the position of the semiconductor chip may be misaligned, and thus a misalignment problem between the mounted semiconductor chip and a circuit layer formed in a build-up process, in particular, a solder ball as a final external connection means May occur. Accordingly, there was a problem that the reliability of the finished product is lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a connection means for forming a rearranged wiring layer on a conductive layer, mounting a semiconductor chip on the rearranged wiring layer, and then forming connection means for etching the conductive layer to be electrically connected to an external device. It relates to a manufacturing method.

In order to achieve the above technical problem, an aspect of the present invention provides a method of manufacturing a semiconductor package. The manufacturing method includes a rearranged wiring layer; A semiconductor chip flip-chip bonded to the rearrangement wiring layer; A sealing member for sealing the semiconductor chip; Connecting means disposed on the rearrangement wiring layer; And a solder ball disposed on the connecting means.

Here, the connecting means may include a metal post having a thickness range of 100 to 500㎛.

In addition, the connecting means may include a bump pad and an additional solder ball disposed on the bump pad.

The semiconductor device may further include an underfill interposed between the rearranged wiring layer and the semiconductor chip.

The semiconductor device may further include a non-conductive paste (NCP) and an anisotropic conductive film (ACF) interposed between the rearranged wiring layer and the semiconductor chip.

The display device may further include an insulation pattern exposing the connection means and covering the rearrangement wiring layer.

In order to achieve the above technical problem there is provided a method of manufacturing a semiconductor package of another aspect of the present invention. The manufacturing method includes preparing a substrate; Forming a conductive layer on the substrate; Forming a rearranged wiring layer on the conductive layer; Flip chip bonding a semiconductor chip on the rearranged wiring layer; Sealing the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form connection means; Forming a solder ball on the connection means; may include.

In addition, flip chip bonding of the semiconductor chip may use any one of soldering, non-conductive paste (NCP), and anisotropic conductive film (ACF).

The method may further include forming an underfill between at least the semiconductor chip and the rearranged wiring layer.

In addition, the conductive layer may have a thickness range of 100 to 500㎛.

The forming of the connecting means may include forming a bump pad by etching the conductive layer; And forming an additional solder ball on the bump pad.

According to the method of manufacturing a semiconductor package of the present invention, after forming a rearranged wiring layer on a conductive layer, mounting a semiconductor chip on the rearranged wiring layer, and etching the conductive layer to form a connection means, the connection means and the semiconductor Misalignment between chips can be prevented, thus ensuring the reliability of the product.

In addition, since the thickness of the external connection means can be easily controlled according to the thickness of the conductive layer, and the stand-off height of the semiconductor package and the external device can be sufficiently obtained, electrical connection between the semiconductor package and the external device can be achieved. Reliability can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings of a semiconductor package. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor package according to an exemplary embodiment of the present invention may include a rearrangement wiring layer 120, a semiconductor chip 130 mounted on the rearrangement wiring layer 120, and a sealing member for sealing the semiconductor chip 130. 150, an external connection means 160 disposed on the rearranged wiring layer 120.

Here, the external connection means 160 serves to electrically connect the semiconductor package and the external device to each other. For example, the external device may be a package substrate, another semiconductor package, a semiconductor chip, a main board substrate, or the like.

The external connection means 160 may include a connection means 161 and a solder ball 162. Here, the connecting means 161 is directly connected to the rearranged wiring layer 120. The connection means 161 may be a metal post electrically connected to the rearrangement wiring layer 120. The metal post may have a thickness range of 100 to 500㎛. Accordingly, the height of the stand-off with the external device on which the semiconductor package is mounted by the metal post can be satisfied, thereby ensuring contact reliability by soldering.

The semiconductor chip 130 may be mounted on the rearranged wiring layer 120 by flip chip bonding. That is, the semiconductor chip 130 and the rearranged wiring layer 120 may be electrically connected to each other by bonding and soldering the bump balls, which are the connection terminals 131 of the semiconductor chip 130, to the rearranged wiring layer 120. Can be.

In addition, the semiconductor device 130 may further include an underfill 140 covering the connection portion between the semiconductor chip 130 and the rearranged wiring layer 120. Here, the underfill 140 may improve the fatigue life of the bump ball by providing an effect of alleviating thermal stress applied to the bump ball in the soldering process. Accordingly, electrical connection reliability between the semiconductor chip 130 and the rearrangement wiring layer 120 may be improved. Here, examples of the material for forming the underfill 140 may include resins such as epoxy resins, polyimide resins, polar arctic resins, polyester resins, and polybenzoxazoles.

In the embodiment of the present invention, the semiconductor chip 130 is described as being mounted by flip chip bonding by soldering, but is not limited thereto. For example, the semiconductor chip 130 may be mounted on the rearranged wiring layer 120 using a non-conductive paste (NCP) and an anisotropic conductive film (ACF).

The sealing member 150 seals the semiconductor chip 130, thereby protecting the semiconductor chip 130 from an external environment. Examples of the material for forming the sealing member 150 may be an epoxy resin, a silicone resin, a fluorine resin, an acrylic resin, or the like.

In addition, the semiconductor package may further include an insulation pattern 170 that exposes the connection means 160 and covers the rearrangement wiring layer 120. The insulating pattern 170 serves to prevent unwanted connection by soldering when the external device is mounted. That is, the insulating pattern 170 may serve to provide insulation between a protective material and a circuit protecting the rearranged wiring layer 120 of the semiconductor package.

Therefore, in the embodiment of the present invention, through the thickness control of the connection means, it is possible to ensure the standoff height between the semiconductor package and the external device for contact reliability, it is possible to improve the reliability of the finished product.

Hereinafter, a semiconductor package according to a second exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Here, the second embodiment may have the same configuration as the semiconductor package described above except for the external connection means. Accordingly, in the second embodiment, repeated description of the first embodiment will be omitted, and the same reference numerals will be used for the same configuration.

2 is a cross-sectional view of a semiconductor package according to a second exemplary embodiment of the present invention.

2, a semiconductor package according to an exemplary embodiment of the present invention may include a rearrangement wiring layer 120, a semiconductor chip 130 mounted on the rearrangement wiring layer 120, and a sealing member for sealing the semiconductor chip 130. The external connection means 260 may be disposed on the rearrangement wiring layer 120.

Here, the semiconductor package and the external device may be electrically connected to each other by the external connection means 260.

The external connection means 260 includes connection means 261 and 262 and solder balls 263. The connection means 261 and 263 may include a bump pad 261 electrically connected to the rearranged wiring layer 120 and an additional solder ball 262 disposed on the bump pad 261. In this case, the bump pad 261 may be directly connected to the rearrangement wiring layer 120.

Accordingly, since the external connection means 260 includes a double solder ball, it is possible to secure a standoff height between the semiconductor package and the external device, thereby improving contact reliability between the semiconductor package and the external device.

Therefore, in the embodiment of the present invention, by forming a double solder ball as the external connection means, it is possible to ensure the stand-off height between the semiconductor package and the external device for contact reliability, thereby improving the reliability of the finished product.

Hereinafter, a method of manufacturing a semiconductor package according to a third embodiment of the present invention will be described with reference to the drawings.

3 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a third embodiment of the present invention.

Referring to FIG. 3, in order to manufacture a semiconductor package, a substrate 100 is first provided.

Here, the substrate 100 may be a wafer substrate used in a semiconductor process. Examples of the material of the substrate 100 may be silicon, ceramic, glass, and polymer.

The conductive layer 110 is formed on the substrate 100. In this case, the conductive layer 110 may be formed by laminating a metal foil. The embodiment of the present invention is not limited to the method of forming the conductive layer 110. Alternatively, the conductive layer 110 may be formed by depositing a metal. In addition, examples of the metal may be Cu, Au, W, Ni, Pb, Ti, and the like.

In a subsequent process, the metal post formed by the conductive layer 110 serves to secure a standoff height between the semiconductor package and the external device. Accordingly. In order to ensure electrical contact reliability between the semiconductor package and the external device, the thickness of the conductive layer 110 may have a thickness range of 100 to 500 μm.

Referring to FIG. 4, after the conductive layer 110 is formed, a first resist pattern 121 is formed on the conductive layer 110. In order to form the first resist pattern 121, a resist layer is first formed by coating a photosensitive resin on the conductive layer 110 or laminating a dry film resist (DFR). Thereafter, the first resist pattern 121 may be formed by performing an exposure and development process on the resist layer.

Subsequently, the rearranged wiring layer 120 is formed on the conductive layer 110 exposed by the first resist pattern 121 using the first resist pattern 121 as a mask.

The rearranged wiring layer 120 may be formed through a deposition process using a shadow mask. Alternatively, the rearranged wiring layer 120 may be formed by electroplating using the conductive layer 110 as a seed layer.

The rearranged wiring layer 120 may be made of metal, such as Al, W, Pb, Sb, Cr, Ni, Ag, Au, Cu, and the like. Here, the rearranged wiring layer 120 may include a pad connected to the semiconductor chip 130 in a subsequent process.

Referring to FIG. 6, the semiconductor chip 130 is mounted on the rearranged wiring layer 120. Here, the semiconductor chip 130 may be electrically connected to the pad of the rearrangement wiring layer 120 through flip chip bonding. That is, the semiconductor chip 130 and the rearranged wiring layer 120 are bonded to each other by bonding and soldering the connection terminal 131 of the semiconductor chip 130 to the pad of the rearranged wiring layer 120. Can be electrically connected.

Thereafter, an underfill 140 may be further formed to cover at least the connection portion between the semiconductor chip 130 and the pad. The underfill 140 may be formed by filling an underfill resin between the semiconductor chip 130 and the rearranged wiring layer 120. Here, the underfill 140 may improve the fatigue life of the bump ball by providing an effect of alleviating thermal stress applied to the bump ball in the soldering process. Accordingly, the electrical connection reliability between the semiconductor chip 130 and the rearranged wiring layer 120 may be improved. Here, examples of the material used as the underfill resin may include resins such as epoxy resins, polyimide resins, polyacrylate resins, polyester resins, and polybenzoxazoles.

In the exemplary embodiment of the present invention, an underfill is formed to improve electrical contact reliability between the semiconductor chip and the rearranged wiring layer, but is not limited thereto. For example, the role of the underfill may be replaced by a sealing member formed in a subsequent process. That is, since the sealing member is formed to cover the connection portion between the semiconductor chip and the rearranged wiring layer, the sealing member may serve as the underfill.

In addition, the method of mounting the semiconductor chip 130 is described as limited by flip chip bonding using soldering, but is not limited thereto. For example, another method of mounting the semiconductor chip 130 may use a conductive paste, an anisotropic conductive film (ACF), and a liquid non-conductive paste (NCP).

Referring to FIG. 7, a sealing member 150 for sealing the semiconductor chip 130 is formed. In this case, the sealing member 150 may be formed to cover the underfill 140. Here, the sealing member 150 serves to seal the semiconductor chip 130 to protect the semiconductor chip 130 from the external environment. Here, examples of the method of forming the sealing member 150 may be a transfer molding method, an injection molding method, a sprin printing method and a dispensing method. In addition, the sealing member 150 is formed of a resin, and for example, may be an epoxy resin, a silicone resin, a fluororesin, an acrylic resin, or the like.

Referring to FIG. 8, after forming the sealing member 150, the substrate 100 is removed from the conductive layer 110. By removing the substrate 100, the substrate 100 may be polished or decomposed by a wet process.

As another method of removing the substrate 100, although not shown in the drawing, after the sacrificial layer is formed between the substrate 100 and the conductive layer 110, the sacrificial layer is subjected to a wet process or UV irradiation. By removing it, the substrate 100 may be separated from the conductive layer 110. In this case, the sacrificial layer is formed on the substrate 100 before the conductive layer 110 is formed. Here, the sacrificial layer may be formed of any one of metal, silicon oxide, silicon nitride, and UV light decomposable resin.

Referring to FIG. 9, a second resist pattern 122 is first formed on the exposed conductive layer 110 by removing the substrate 100. Thereafter, as the etching process of the conductive layer 110 using the second resist pattern 122 as an etching mask, as shown in FIG. 10, a metal post serving as the connecting means 161 may be formed. In this case, the connection means 161 may have a thickness of the conductive layer 110 itself, that is, 100 to 500㎛.

Referring to FIG. 11, after forming the connection means, the second resist pattern 122 is removed.

Referring to FIG. 12, an insulating pattern 170 is formed to expose the connection means 161 and cover the rearrangement wiring layer 120. The insulating pattern 170 serves to prevent a short defect of the rearranged wiring layer 120 from the solder ball 162 formed by a subsequent process.

Thereafter, as the solder ball 162 is formed on the rearranged wiring layer 120 exposed by the insulating pattern 170, the external connection means 160 including the connection means 161 and the solder ball 162 is formed. Can be formed.

Therefore, in the method of manufacturing a semiconductor package according to an embodiment of the present invention, after forming a rearranged wiring layer on the conductive layer, mounting the semiconductor chip on the rearranged wiring layer, the conductive layer is etched to etch the connecting means. By forming, the misalignment between the solder ball and the semiconductor chip in contact with the external device can be significantly reduced, resulting in a poor contact between the semiconductor package and the external device.

In addition, the connecting means for electrically connecting the semiconductor chip and the external device to each other is formed from a conductive layer having a predetermined thickness, thereby ensuring a standoff height between the semiconductor chip and the external device, thereby providing a semiconductor chip and an external device. The contact reliability of the liver can be secured.

Hereinafter, a method of manufacturing a semiconductor package described in the fourth embodiment of the present invention will be described with reference to the drawings. Here, the fourth embodiment may have the same manufacturing method as the semiconductor package according to the third embodiment described above except for the connecting means. Accordingly, in the fourth embodiment, repeated description of the third embodiment will be omitted, and the same reference numerals will be used for the same configuration.

13 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a fourth embodiment of the present invention.

Referring to FIG. 13, to manufacture a semiconductor package, first, a substrate 100 is prepared. Thereafter, a conductive layer 210 is formed on the substrate 100.

Referring to FIG. 14, a rearrangement wiring layer 120 is formed on the conductive layer 210. The rearranged wiring layer 120 may be formed by a deposition process or a plating method using a mask. Here, the rearranged wiring layer 120 may include a pad for electrically connecting with the semiconductor chip 130 to be described later.

Referring to FIG. 13, the semiconductor chip 130 is mounted to be electrically connected to the rearrangement wiring layer 120. The semiconductor chip 130 may be mounted using a flip chip bonding method using soldering of bump balls. However, embodiments of the present invention are not limited thereto, and the semiconductor chip 130 may be mounted using any one of a non-conductive paste (NCP) and an anisotropic conductive film (ACF). It may be.

In addition, in order to improve the contact reliability of the semiconductor chip 130, the semiconductor chip 130 and the rearranged wiring layer to cover at least a connection portion between the semiconductor chip 130 and the rearranged wiring layer 120. An underfill 140 may be further formed between the layers 120.

Thereafter, after the sealing member 150 is formed to seal the semiconductor chip 130, the substrate 100 is removed from the conductive layer 210.

Referring to FIG. 14, a resist pattern 221 is formed on the conductive layer 210 exposed by removing the substrate 100. In order to form the resist pattern 221, first, a photosensitive resin is coated on the conductive layer 210 or a dry film resist (DFR) is formed to form a resist layer. Thereafter, the resist layer 221 may be formed by performing exposure and development processes on the resist layer.

The conductive layer 210 is etched using the resist pattern 221 as an etch mask to form a bump pad 261 as shown in FIG. 15.

After the bump pad 261 is formed, the resist pattern 221 is removed as shown in FIG. 18.

Referring to FIG. 19, by forming the additional solder balls 262 on the bump pads 261, the connection means 261 and 262 formed of the bump pads 261 and the additional solder balls 262 may be formed.

Referring to FIG. 20, an insulating pattern 170 is formed on the rearranged wiring layer 120 to expose the connection means 261 and 262, that is, the additional solder ball 262. Thereafter, solder balls 263 are formed on the connection means 261 and 262 exposed by the insulating pattern 170. Accordingly, the semiconductor package may form the external connection means 260, that is, the connection means 261 and 262 and the solder ball 263 to be connected to the external device.

Therefore, in the method of manufacturing a semiconductor package according to the embodiment of the present invention, a rearrangement wiring layer is formed on a conductive layer for forming bumping pads, that is, connecting means for electrically connecting the external device and the semiconductor chip to each other, By mounting the semiconductor chip on the rearranged wiring layer and etching the conductive layer to form bump pads, it is possible to prevent the alignment miss problem between the semiconductor chip and the connecting means, thereby ensuring the reliability of the final product. .

In addition, since the double solder ball is provided as the external connection means, the standoff height between the semiconductor package and the external device can be sufficiently secured, thereby ensuring contact reliability between the semiconductor package and the external device.

1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

2 is a cross-sectional view of a semiconductor package according to a second exemplary embodiment of the present invention.

3 to 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a third embodiment of the present invention.

13 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with a fourth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 substrate 110 conductive layer

120: rearranged wiring layer 130: semiconductor chip

140: underfill 150: sealing member

160, 260: external connection means 161: connection means

162, 263: solder ball 170: insulation pattern

261: bump pad 262: additional solder ball

Claims (11)

Rearranged wiring layer; A semiconductor chip flip-chip bonded to the rearrangement wiring layer; A sealing member for sealing the semiconductor chip; Connecting means disposed on the rearrangement wiring layer; And A semiconductor package comprising a solder ball disposed on the connecting means. The method of claim 1, The connecting means is a semiconductor package having a metal post having a thickness range of 100 to 500㎛. The method of claim 1, The connecting means is a bump pad and an additional solder ball disposed on the bump pad. The method of claim 1, The semiconductor package further comprises an underfill interposed between the rearranged wiring layer and the semiconductor chip. The method of claim 1, The semiconductor package further comprises a non-conductive paste (NCP) and an anisotropic conductive film (ACF) interposed between the rearranged wiring layer and the semiconductor chip. The method of claim 1, And an insulating pattern exposing the connection means and covering the rearrangement wiring layer. Preparing a substrate; Forming a conductive layer on the substrate; Forming a rearranged wiring layer on the conductive layer; Flip chip bonding a semiconductor chip on the rearranged wiring layer; Sealing the semiconductor chip; Separating the substrate from the conductive layer; Etching the conductive layer to form connection means; Forming a solder ball on the connection means; Method of manufacturing a semiconductor package comprising a. The method of claim 7, wherein Flip chip bonding of the semiconductor chip is a method of manufacturing a semiconductor package using any one of soldering, non-conductive paste (NCP) and anisotropic conductive film (ACF). The method of claim 7, wherein And forming an underfill between at least the semiconductor chip and the rearranged wiring layer. The method of claim 7, wherein The conductive layer is a method of manufacturing a semiconductor package having a thickness range of 100 to 500㎛. The method of claim 6, Forming the connection means Etching the conductive layer to form a bump pad; And Forming an additional solder ball on the bump pad.

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