KR20100068051A - Display substrate, method of manufacturing the same and liquid crystal display device having the same - Google Patents

Abstract

PURPOSE: A display substrate, a method for manufacturing the same, and a liquid crystal display device with the same are provided to improve light transmittance using a circular polarizing light plate. CONSTITUTION: A data line crosses a gate line. A transistor is connected to the gate line and the data line. The first pixel electrode(145) is connected to the first output electrode of the transistor. The first pixel electrode includes the first cut grooves to define the first domain. The second pixel electrode(147) is connected to the second output electrode of the transistor. The gate line is arranged between the first pixel electrode and the second pixel electrode.

Description

DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a display substrate, a manufacturing method thereof and a liquid crystal display device having the same. More particularly, the present invention relates to a display substrate having an improved display quality, a manufacturing method thereof, and a liquid crystal display apparatus having the same.

In general, a patterned vertical alignment (PVA) mode (hereinafter, mPVA mode) liquid crystal display for small and medium-sized mobiles adopts a circularly polarized optical mode superior to other modes in terms of transmittance, or a linearly polarized optical mode with excellent visibility and contrast ratio. Apply.

In the liquid crystal display of the mPVA mode, the slit portions are formed on the common electrode of the color filter substrate and the pixel electrode of the array substrate to form a multi-domain that improves the viewing angle.

In the case of the liquid crystal display of the mPVA mode, the pixel size is small, and it is preferable that not only the aperture ratio of the pixel itself be large, but also the alignment of the directors of the liquid crystal is 45 degrees to the polarization axis of the polarizing plate. Due to this, the light leakage from the side cannot be removed with the existing compensation film. Therefore, the side visibility improvement is calculated | required.

In addition, the polymer stabilized vertical alignment (SVA) mode is a technique for controlling the liquid crystal by introducing a micro slit pixel structure without patterning the upper common electrode. Since the upper common electrode is not patterned, the safety of the domain is lowered. Thus, a panel is manufactured by adding a small amount of reactive mesogen to the liquid crystal to move along the liquid crystal in the same direction as the liquid crystal. After the panel is manufactured, the liquid crystal is oriented by polymerizing the added reactive mesogen by exposing ultraviolet rays while the panel is driven.

However, there is a problem of low transmittance due to the use of the micro slit pixel structure and the linear polarizing plate.

Accordingly, the technical problem of the present invention has been conceived in this respect, and an object of the present invention is to provide a display substrate having improved side visibility and improved transmittance.

Another object of the present invention is to provide a method of manufacturing the display substrate.

Still another object of the present invention is to provide a liquid crystal display device including the display substrate.

In order to achieve the above object of the present invention, a display substrate according to an embodiment includes a gate line, a data line crossing the gate line, a transistor connected to the gate line and the data line, the first output electrode of the transistor And a first pixel electrode having a plurality of first cutouts formed to define a first domain, and a second pixel electrode connected to a second output electrode of the transistor.

In an embodiment of the present invention, the gate line may be disposed between the first pixel electrode and the second pixel electrode, and a voltage may be applied to the first pixel electrode and the second pixel electrode simultaneously by the transistor.

In an embodiment of the present invention, the outer region of the first pixel electrode may define an open loop shape, and the outer region of the second pixel electrode may define a closed loop shape. The first cutouts may be formed while defining four groups in the first domain, and the first cutouts may be parallel to each other in the same group.

In an embodiment of the present invention, a first boosting electrode overlapping a first output electrode of the transistor to define a first storage capacitor, and a second boosting overlapping a second output electrode of the transistor to define a second storage capacitor. It may further include an electrode.

In an embodiment of the present disclosure, the first boosting electrode and the second boosting electrode may include a transparent material, and the size of the first boosting electrode may be smaller than that of the second boosting electrode. The display device may further include a first boosting line formed in parallel with the gate line and electrically connected to the first boosting electrode, and a second boosting line formed in parallel with the gate line and electrically connected to the second boosting electrode. .

In an embodiment of the present invention, an outer size of the first pixel electrode may be larger than an outer size of the second pixel electrode.

In order to achieve the above object of the present invention, according to the manufacturing method of the display substrate according to an embodiment, a transistor electrically connected to the gate line and the data line to cross each other is formed. Subsequently, a first pixel electrode connected to the first output electrode of the transistor and having a plurality of first cutout grooves defined to define a first domain, and a second pixel electrode connected to the second output electrode of the transistor are formed. do.

In an embodiment, a first boosting line and a second boosting line boosting the first pixel electrode and the second pixel electrode by patterning a first metal layer deposited on a base substrate, and a gate electrode of the transistor. And forming a gate line, depositing and patterning a transparent metal layer on the base substrate having the first boosting line, the second boosting line, the gate electrode, and the gate line, and patterning the first boosting line; The method may further include forming a first boosting electrode and a second boosting electrode electrically connected to the second boosting line, respectively. The size of the first boosting electrode may be smaller than the size of the second boosting electrode.

In order to achieve the above object of the present invention, the liquid crystal display device according to the embodiments includes a display substrate, an opposing substrate and a liquid crystal layer. The display substrate includes a gate line, a data line crossing the gate line, a transistor connected to the gate line and the data line, a plurality of transistors connected to a first output electrode of the transistor and defined to define a first domain. A first pixel electrode having first cutouts and a second pixel electrode connected to a second output electrode of the transistor. The counter substrate opposes the display substrate and includes a common electrode. The liquid crystal layer is interposed between the display substrate and the counter substrate.

In an embodiment of the present invention, the semiconductor device may further include a first boosting electrode forming a first output electrode and a first storage capacitor of the transistor, and a second boosting electrode forming a second output electrode and a second storage capacitor of the transistor. can do.

In example embodiments, the first pixel electrode and the second pixel electrode may include a first contact hole and a second contact hole electrically connected to the first and second output electrodes, respectively. The opposing substrate may include a common electrode in which a first common electrode hole and a second common electrode hole are formed corresponding to a central portion of each of the first and second pixel electrodes. The first contact hole and the second contact hole may be disposed to overlap the first common electrode hole and the second common electrode hole, respectively.

In an exemplary embodiment of the present invention, the opposing substrate may include a common electrode having a common electrode hole corresponding to a central portion of the second pixel electrode. The second contact hole may be disposed to overlap the common electrode hole. The liquid crystal layer may include a reactive mesogen.

In order to achieve the above object of the present invention, the liquid crystal display device according to the embodiments includes a display substrate, an opposing substrate and a liquid crystal layer. The display substrate includes a pixel electrode having a gate line, a data line crossing the gate line, a transistor connected to the gate line and the data line, and a plurality of cutout grooves connected to the transistor to define a pixel region. It includes. The opposite substrate includes a common electrode facing the display substrate and having a common electrode hole. The liquid crystal layer includes a liquid crystal layer interposed between the display substrate and the counter substrate.

According to such a display substrate, a manufacturing method thereof, and a liquid crystal display device having the same, transmittance may be improved due to the use of a circular polarizing plate while improving side visibility compared to the existing circular polarization mPVA. In addition, since the first pixel electrode and the second pixel electrode may implement dual gamma through the first boosting signal and the second boosting signal, side visibility may be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are shown in an enlarged scale than actual for clarity of the invention. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part of a layer, a film, an area, a plate, etc. is said to be above another part, this includes not only the case where it is directly over another part but also another part in the middle. Conversely, if a part of a layer, film, region, plate, etc. is under another part, this includes not only the part directly under another part but also another part in the middle.

Example 1

1 is a plan view of a liquid crystal display according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1. 3 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 to 3, the liquid crystal display according to the first exemplary embodiment of the present invention includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300.

The display substrate 100 includes a base substrate 110 in which a pixel region is defined. The gate line GL, the first boosting line BL1, the second boosting line BL2, the first boosting electrode 10, the second boosting electrode 30, and the gate insulating layer may be disposed on the first base substrate 110. 120, the first data wire DL1, the second data wire DL2, the data insulating layer 130, the first contact electrode 50, the second contact electrode 70, the first pixel electrode 145, and the first The two pixel electrode 147, the transistor TFT, and the lower alignment layer 150 are formed.

The first base substrate 110 has a plate shape and is made of a transparent material, for example, glass, quartz, and synthetic resin.

The gate line GL is formed on the base substrate 110 and extends along the first direction DI1. The gate line GL may be disposed between the first pixel electrode 145 and the second pixel electrode 147.

The first boosting line BL1 and the second boosting line BL2 extend along the first direction DI1 to cross the centers of the first pixel electrode 145 and the second pixel electrode 147. It is formed by screaming.

The first boosting electrode 10 and the second boosting electrode 30 overlap with portions of the first boosting line BL1 and the second boosting line BL2, respectively, and are formed on the base substrate 110. do. Since the first boosting electrode 10 and the second boosting electrode 30 are transparent metal patterns, transmittance may be improved.

The first gate insulating layer 120 covers the gate line GL, the first and second boosting lines BL1 and BL2, and the first and second boosting electrodes 10 and 30. It is formed on the base substrate 110.

The first and second data lines DL1 and DL2 are formed on the gate insulating layer 120 and extend along a second direction DI2 crossing the first direction DI1. In this case, the first and second directions DI1 and DI2 may be perpendicular to each other.

The transistor TFT includes a gate electrode GE, an active electrode AE, a source electrode SE, a first drain electrode DE1, and a second drain electrode DE2. The transistor TFT may simultaneously apply a voltage to the first pixel electrode 145 and the second pixel electrode 147.

The gate electrode GE may be part of the gate line GL. The active electrode AE is formed on the gate insulating layer 120 to overlap the gate electrode GE.

The source electrode SE is branched from the data line DL.

The first drain electrode DE1 and the second drain electrode DE2 are formed to be spaced apart from each other, and are formed to be spaced apart from the source electrode SE.

The first drain electrode DE1 is extended to be electrically connected to the first contact electrode 50 and overlapped with the first boosting electrode 10 to improve transmittance.

The second drain electrode DE2 is extended to be electrically connected to the second contact electrode 70 and overlapped with the second boosting electrode 30 to improve transmittance.

The first and second contact electrodes 50 and 70 are formed on the gate insulating layer 120 and are formed in unit pixels, respectively. The first and second contact electrodes 50 and 70 may have, for example, a rectangular shape when viewed from a plane.

The data insulating layer 130 may include the data lines DL1 and DL2, the source electrode SE and the first and second drain electrodes DE1 and DE2, the first contact electrode 50, and the second. The gate insulating layer 120 is formed to cover the contact electrode 70. The data insulating layer 130 may include an inorganic insulating layer 131 and an organic insulating layer 132. The inorganic insulating layer 131 is formed to cover the organic insulating layer 132.

A first contact hole 133 is formed on the first contact electrode 50 in the data insulating layer 130, and a second contact hole 135 is formed on the second contact electrode 70.

The first and second pixel electrodes 145 and 147 are formed on the data insulating layer 130. The first and second pixel electrodes 145 and 147 may be metal patterns formed by patterning the transparent metal layer.

The first pixel electrode 145 contacts the first contact electrode 50 from which the first drain electrode DE1 of the transistor TFT extends, and is formed to define a first domain D1. Has first incision grooves 160.

The second pixel electrode 147 contacts the second contact electrode 70 from which the second drain electrode DE2 of the transistor TFT extends. The second domain D2 is defined corresponding to the second pixel electrode 147. In addition, since the outer region of the first pixel electrode 145 has an open loop shape, the first cutouts 160 have a shape formed through the inside of the first pixel electrode 145 to the outside.

The first cutouts 160 of the first pixel electrode 145 are formed by defining four first subdomains in the first domain D1. The first cutouts 160 are formed parallel to each other in one first subdomain region. Accordingly, the remaining area of the first pixel electrode 145 except for the first cutouts 160 has a shape in which a plurality of slits are arranged.

The outer size of the first pixel electrode 145 is larger than the outer size of the second pixel electrode 147, and the area of the first pixel electrode 145 is smaller than the area of the second pixel electrode 147. do.

Therefore, since the pattern shapes of the first pixel electrode 145 and the second pixel electrode 147 are different from each other, the transmittance may be increased and the side visibility may be improved.

The lower alignment layer 150 is formed on the first base substrate 110 on which the first and second pixel electrodes 145 and 147 are formed to display the liquid crystal molecules of the liquid crystal layer 300 in a vertical direction. Orientation is directed from the substrate 100 toward the counter substrate 200.

The opposing substrate 200 is disposed to face the display substrate 100.

The opposing substrate 200 may include an upper substrate 210, a light blocking pattern BM, a color filter pattern 220, an overcoating layer 230, a common electrode 240, and an upper alignment layer 250.

The light blocking pattern BM is formed on the upper substrate 201 to correspond to the data lines DL1 and DL2 and the transistor TFT. Therefore, the color filter pattern 220 is formed in the pixel area that is not shielded.

The color filter pattern 220 may include, for example, a red filter, a green filter, and a blue filter. The overcoat layer 230 covers the color filter pattern 220 and the light blocking pattern BM.

The common electrode 240 is formed on the overcoat layer 230. The common electrode 240 has common electrode holes 243 and 245 corresponding to the first and second contact holes 133 and 135. The common electrode holes 243 and 245 serve to arrange the liquid crystals of the liquid crystal layer 300 toward the common electrode holes 243 and 245 when an electric field is applied.

Here, although the common electrode holes 243 and 245 are arranged in the center and have a quadrangular shape, the common electrode holes 243 and 245 may be cross-shaped, circular, and cross-shaped inclined at 45 degrees. .

The upper alignment layer 250 is formed on the common electrode 240 to vertically align the liquid crystal layer 300.

The liquid crystal layer 300 is interposed between the display substrate 100 and the opposing substrate 200. The arrangement of liquid crystals in the liquid crystal layer 300 is changed by an electric field formed between the first and second pixel electrodes 145 and 147 and the common electrode 240, and as a result, the liquid crystal layer 300 The light transmittance may be changed according to the intensity of the electric field.

4 is a circuit diagram illustrating an electrical connection relationship in FIG. 1. 5A is a waveform diagram illustrating a first pixel voltage corresponding to the first pixel electrode of FIG. 4. 5B is a waveform diagram illustrating a second pixel voltage corresponding to the second pixel electrode of FIG. 4.

1 through 5B, the data signal DS may receive the input electrodes of the first and second switching elements T1 and T2 included in the transistor TFT through the data line DL. The gate signal GS is applied to the control electrode CE of the first and second switching elements T1 and T2 through the gate line GL.

The data signal DS applied to the input electrode IE is output to the first output electrode VP1 and the second output electrode VP2.

The first boosting electrode 10, the gate insulating layer 120, the active pattern AP, and the first contact electrode 50, which are in contact with the first boosting line BL1, have a first storage capacitor CST. Form _A ). The first contact electrode 50 is connected to the first drain electrode DE1 to represent the first output electrode VP1.

Since the capacitance of the first storage capacitor CST _A is increased by the first boosting electrode 10, the gate insulating layer 120, the active pattern AP, and the first pixel electrode 145, it is opaque. Since the size of the first contact electrode 50 made of metal can be reduced, the transmittance is improved.

The second boosting electrode 30, the gate insulating layer 120, the active pattern AP, and the second contact electrode 70 which are in contact with the second boosting line BL2 may have a second storage capacitor CST. Form _B ). The second contact electrode 70 is connected to the second drain electrode DE2 to represent the second output electrode VP2.

Since the capacitance of the second storage capacitor CST _B is increased by the second boosting electrode 30, the gate insulating layer 120, the active pattern AP, and the second pixel electrode 147, it is opaque. Since the size of the second contact electrode 70 made of metal can be reduced, the transmittance is improved.

When the first boosting signal VCST1 is applied to the first boosting line BL1, the voltage of the data signal DS applied to the first output electrode VP1 due to the first storage capacitor CST _A is controlled. The level may be boosted to the first pixel voltage VP, which is the voltage of the first pixel electrode 145.

When controlling the second boosting signal VCST2 applied to the second boosting line BL2, the voltage of the data signal DS applied to the second output electrode VP2 due to the second storage capacitor CST _B. The level may be boosted to the second pixel voltage VP, which is the voltage of the second pixel electrode 147.

The first and second boosting lines BL1 and BL2 may be the same boosting line ALS LINE.

The first pixel voltage VP and the second pixel voltage VP applied by the first and second boosting lines BL1 and BL2 may be determined from Equations 1 and 2 below.

Here, Vd is the data voltage applied by the data line DL, and ΔV1 and ΔV2 are respectively the first pixel voltages changed by the coupling when the levels of the first and second boosting lines BL1 and BL2 are changed. The first difference voltage CST _A of the first difference voltage and the second pixel voltage, CST _A, is formed by overlapping the gate insulating layer 120 formed between the first boosting electrode 10 and the first contact electrode 50. The capacitor CST _B is a second storage capacitor formed by overlapping the gate insulating layer 120 formed between the second boosting electrode 30 and the second contact electrode 70, and CLC _A is formed on the first pixel electrode 145. The liquid crystal capacitors CLC _B formed correspondingly correspond to the liquid crystal capacitors Vh and Vh ′ formed corresponding to the second pixel electrode 147, respectively, and the high voltage levels V1 and Vl of the first and second boosting signals VCST1 and VCST2. And V1 'respectively represent low voltage levels of the first and second boosting signals VCST1 and VCST2.

As can be seen in Equations 1 and 2, according to the embodiment of the present invention, the first storage capacitor and the second storage capacitor are different from each other. Therefore, the first kickback voltage corresponding to the first pixel electrode and the second kickback voltage corresponding to the second pixel electrode are also different from each other. The first and second kickback voltages may be represented by Equations 3 and 4, respectively.

Here, ΔVk1 denotes a first kickback voltage in a region corresponding to the first pixel electrode 145, and ΔVk2 denotes a second kickback voltage in a region corresponding to the second pixel electrode 147. Each of CGS _A and CGS _B refers to a capacitor formed by overlapping a gate insulating layer 120 formed between a gate electrode and a source electrode corresponding to the first pixel electrode 145 and the second pixel electrode 147.

As shown in Equation 1 to Equation 4, the first storage capacitor CST _A is formed to correspond to the first pixel electrode 145 and the second pixel electrode 147. The size of the second differential voltage ΔV2 may be smaller than that of the first differential voltage ΔV1 by being smaller than the capacitor CST _B. Accordingly, the size of the second pixel voltage VP is larger than the size of the first pixel voltage VP by forming the size of the first boosting electrode 10 smaller than the size of the second boosting electrode 30. can do.

However, since the first storage capacitor CST _A is relatively smaller than the second storage capacitor CST _B , the first kickback voltage ΔVk1 in the region corresponding to the first pixel electrode 145 is equal to the first storage capacitor CST _A. It is greater than the second kickback voltage ΔVk2 in the region corresponding to the two pixel electrodes 147. The first gate-source parasitics of the region corresponding to the first pixel electrode 145 to improve flicker by having the same magnitude of the first kickback voltage ΔVk1 and the same magnitude of the second kickback voltage ΔVk2. The capacitor CGS _A may be designed to be smaller than the second gate-source parasitic capacitor CGS _{B in} the region corresponding to the second pixel electrode 147.

Further, the first liquid crystal capacitor CLC _A formed corresponding to the first pixel electrode 145 and the second pixel electrode 147 is larger than the second liquid crystal capacitor CLC _B so that the first difference voltage ( The magnitude of the second difference voltage ΔV2 may be smaller than that of ΔV1. Accordingly, the size of the second pixel voltage VP may be larger than the size of the first pixel voltage VP by reducing the circumference of the first pixel electrode 145 and making it smaller than the second pixel electrode 147. Can be. In this embodiment, since the area of the second pixel electrode 147 is reduced in the area covered by the light blocking pattern BM, there is no loss of transmittance.

1 to 4 and 5A, the data signal DS is boosted to the first pixel voltage VP by the first boosting signal VCST1.

As described above, when the gate signal GS is applied to the control electrode C of the first switching element T1, the data applied to the input electrode IE of the first switching element T1. The signal DS is applied to the first output electrode VP1.

The first boosting signal VCST1 is applied to the first boosting line BL1 in association with the data signal DS. The first boosting signal VCST1 has a voltage level much higher than that of the common voltage applied to the common electrode VCOM. Accordingly, the data signal DS is boosted to the first pixel voltage VP by the first storage capacitor CST _A formed by the first output electrode VP1 and the boosting line BL. It may be applied to the first pixel electrode 145.

As the first pixel voltage V1 is applied, the arrangement of the liquid crystal layer 300 on the first pixel electrode 145 is changed.

1 to 4 and 5B, the data signal DS is boosted to the second pixel voltage VP by the second boosting signal VCST2.

Substantially at the same time as the data signal DS is boosted to the first pixel voltage VP, the data signal DS is boosted to the second pixel voltage VP by the second boosting line BL2. .

When the control signal GS is applied to the control electrode C of the second switching element T2, the data signal DS applied to the input electrode IE of the second switching element T2 is The second output electrode VP2 is applied to the second output electrode VP2.

The second boosting signal VCST2 is applied to the second boosting line BL2. The second boosting signal VCST2 has a higher voltage level than the common voltage applied to the common electrode VCOM. Therefore, the data signal DS is boosted to the second pixel voltage VP by the second storage capacitor CST _B formed by the second output electrode VP2 and the second boosting line BL2. It may be applied to the second pixel electrode 147.

FIG. 6 is a cross-sectional view taken along line III-III ′ of FIG. 1. FIG. 7 is a cross-sectional view taken along the line VI-VI 'of FIG. 1.

6 and 7 are substantially the same as the liquid crystal display described with reference to FIG. 3. Therefore, corresponding reference numerals are used for corresponding elements, and duplicate descriptions are omitted.

3, 6, and 7, the first boosting electrode 10, the gate insulating layer 120, the active pattern AP, the first contact electrode 50, and the first pixel electrode ( The first storage capacitor CLC _A is formed by 145. The second storage capacitor CLC _B is formed by the second boosting electrode 30, the gate insulating layer 120, the active pattern AP, the second contact electrode 70, and the second pixel electrode 147. ) Is formed.

Here, the width A of the first contact electrode 50 may be 18 μm. In addition, the width A ′ of the second contact electrode 70 may be 18 μm.

However, the width B of the first boosting electrode 10 and the width B ′ of the second boosting electrode 30 can be adjusted. Therefore, the width B of the first boosting electrode 10 is adjusted to adjust the capacitance of the first storage capacitor CST _A , and the width B ′ of the second boosting electrode 30 is adjusted. The capacity of the second storage capacitor CST _B may be adjusted.

Referring to FIGS. 4, 6, and 7 again, the first storage capacitor CLC _A is made smaller than the second storage capacitor CST _B so that the second differential voltage ΔV2 is smaller than the first differential voltage ΔV1. As a result, the magnitude of the second pixel voltage VP may be larger than that of the first pixel voltage VP. That is, the width B of the first boosting electrode 10 is smaller than the width B ′ of the second boosting electrode 30, so that the second pixel voltage is larger than the size of the first pixel voltage VP. The size of the (VP) can be increased. As a result, since the magnitude of the second pixel voltage VP is greater than the magnitude of the first pixel voltage VP, the liquid crystal of the first domain D1 is greater than that of the second domain D2. You can see that it is much tilted.

In addition, the size of the first contact electrode 50 and the second contact electrode 70 made of an opaque metal is fixed, and the first boosting electrode 10 and the second boosting electrode 30 are made of a transparent metal. The capacitance of the first storage capacitor CST _A and the second storage capacitor CST _B can be increased by changing the size of the second capacitor, thereby improving the aperture ratio.

8A through 8C are cross-sectional views illustrating a method of manufacturing a display substrate included in the liquid crystal display shown in FIG. 3. 8A to 8C are substantially the same as the cross-sectional view of the liquid crystal display described with reference to FIG. 3. Therefore, corresponding reference numerals are used for corresponding elements, and duplicate descriptions are omitted.

1 to 3 and 8A, a gate metal layer is formed on the base substrate 110. The gate metal layer is patterned to form the first boosting line BL1 and the second boosting line BL2 corresponding to the first domain D1 and the second domain D2, respectively, as shown in FIG. 2. A gate metal pattern including the gate electrode GE of the transistor TFT is formed.

A transparent metal layer is formed on the gate metal pattern. The first boosting electrode 10 and the second boosting electrode 30 are formed by patterning the transparent metal layer. A portion of the first boosting electrode 10 and the second boosting electrode 30 is formed to overlap the first boosting line BL1 and the second boosting line BL2, respectively.

The gate insulating layer 120 is formed on the first base substrate 110 on which the gate metal pattern and the transparent metal pattern are formed.

1 to 3 and 8B, the active pattern AP is formed on the base substrate 110 on which the gate insulating layer 120 is formed. A source metal layer is formed on the first base substrate 110 on which the active pattern AP is formed. The source metal layer is patterned to form a source metal pattern including the first and second data lines DL1 and DL2, the source electrode SE, and the drain electrodes DE1 and DE2 illustrated in FIG. 1. . Herein, the active pattern AP and the source metal patterns are formed using different masks, but the channel pattern and the source metal pattern may be formed using one mask. Subsequently, the inorganic insulating layer 131 is formed on the base substrate 110 on which the source metal pattern is formed.

1 to 3 and 8C, the organic insulating layer 132 is formed on the base substrate 110 on which the inorganic insulating layer 131 is formed. The first and second contact holes 133 and 135 are formed to etch the inorganic insulating layer 131 and the organic insulating layer 132 to expose the first and second contact electrodes 50 and 70. .

A transparent metal layer is formed on the base substrate 110 on which the first and second contact holes 133 and 135 are formed. The first and second pixel electrodes 145 and 147 are formed by patterning the transparent metal layer.

Here, the first cutouts 160 of the first pixel electrode 145 are formed while defining four first subdomains in the first domain D1, and within the same group, the first cutouts 160 are formed. The grooves are formed parallel to each other. Accordingly, the remaining area of the first pixel electrode 145 except for the first cutouts 160 has a shape in which a plurality of slits are formed.

Therefore, the outer size of the first pixel electrode 145 is larger than the outer size of the second pixel electrode 147, and the area of the first pixel electrode 145 is larger than the area of the second pixel electrode 147. It is formed small.

The first and second pixel electrodes 145 and 147 are in contact with the first and second contact electrodes 50 and 70 through the first and second contact holes 133 and 135. The first and second drain electrodes DE1 and DE2 which are first and second output electrodes of the transistor TFT are electrically connected to each other.

That is, the data signal DS is applied to the first pixel electrode 145 and the second pixel electrode 147 by the first boosting signal VCST1 and the second boosting signal VCST2. Boosted and applied to the second and second pixel voltages VP. Therefore, since the dual gamma of the first pixel electrode 145 and the second pixel electrode 147 can be implemented, the side visibility is improved.

In addition, the counter substrate 200 disposed on the first and second pixel electrodes 145 and 147 having slits has the first and second common electrode holes 243 and 245, thereby providing Since the liquid crystal layer 300 does not need to include a reactive mesogen and the UV irradiation process may be omitted, the manufacturing process may be simplified.

Example 2

9 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 10 is a cross-sectional view taken along the line VV ′ of FIG. 9. FIG. 11 is a cross-sectional view taken along the line VI-VI 'of FIG. 9.

In Example 2 of the present invention, the common electrode hole is not formed corresponding to the first domain D1 region of the common electrode 240 of the counter substrate 200, and the liquid crystal layer 300 includes the reactive mesogen. Except for the liquid crystal display described with reference to FIGS. 1 to 4 are substantially the same. Therefore, corresponding reference numerals are used for corresponding elements, and duplicate descriptions are omitted.

9 to 11, the common electrode 240 is formed on the overcoat layer 230. The common electrode 240 has a common electrode hole 245 corresponding to the second contact hole 135. The common electrode hole 245 serves to allow the liquid crystals of the liquid crystal layer 300 to be arranged toward the common electrode hole 245 when an electric field is applied.

Instead of the common electrode hole 243 corresponding to the first contact hole 133 of the liquid crystal display according to the first embodiment, the liquid crystal layer 300 of the liquid crystal display according to the second embodiment may be reactive mesogen. RM) below. When light is irradiated onto the liquid crystal layer 300, the first RM cured layer 151 and the second RM cured layer 251 for fixing the liquid crystal molecules adjacent to the lower alignment layer 150 and the upper alignment layer 250 in a horizontal direction. ) Is formed. In addition, when moved to the center of the liquid crystal layer 300, the liquid crystal molecules are arranged vertically.

Due to the arrangement of the liquid crystal molecules, the response speed at which the liquid crystal array is aligned with respect to the driving signal may be very fast, and the viewing angle may be improved by varying the direction of the liquid crystal array.

In Embodiment 2 of the present invention, the electrical connection relationship of the liquid crystal display device shown in FIG. 9 is substantially the same as the electrical connection relationship of the liquid crystal display device in Embodiment 1 described by FIG. Detailed description of the electrical connection relationship between the illustrated liquid crystal display will be omitted.

In Embodiment 2 of the present invention, the relationship between the signals and voltages applied to the liquid crystal display device shown in FIG. 9 is the relationship between the signals and voltages applied to the liquid crystal display device in Embodiment 1 described in FIGS. Since it is substantially the same as the electrical connection relationship, a detailed description of the relationship between the signals and voltages applied to the liquid crystal display shown in FIG. 9 will be omitted.

12 is a cross-sectional view taken along the line VII-VII ′ of FIG. 9. FIG. 13 is a cross-sectional view taken along the line VIII-VIII ′ of FIG. 9.

In Example 2 of the present invention, the common electrode hole is not formed corresponding to the first domain D1 region of the common electrode 240 of the counter substrate 200, and the liquid crystal layer 300 includes the reactive mesogen. Except for the liquid crystal display device described with reference to FIGS. 6 and 7. Therefore, corresponding reference numerals are used for corresponding elements, and duplicate descriptions are omitted.

12 and 13, the common electrode 240 is formed on the overcoat layer 230. The common electrode 240 has a common electrode hole 245 corresponding to the second contact hole 135. The common electrode hole 245 serves to allow the liquid crystals of the liquid crystal layer 300 to be arranged toward the common electrode hole 245 when an electric field is applied.

Instead of the common electrode hole 243 corresponding to the first contact hole 133 of the liquid crystal display according to the first embodiment, the liquid crystal layer 300 of the liquid crystal display according to the second embodiment may be reactive mesogen. RM) below. When light is irradiated onto the liquid crystal layer 300, the first RM cured layer 151 and the second RM cured layer 251 for fixing the liquid crystal molecules adjacent to the lower alignment layer 150 and the upper alignment layer 250 in a horizontal direction. ) Is formed. In addition, when moved to the center of the liquid crystal layer 300, the liquid crystal molecules are arranged vertically.

Due to the arrangement of the liquid crystal molecules, there is an advantage that the response speed at which the liquid crystal array is aligned with respect to the driving signal may be very fast, and the viewing angle may be improved by varying the direction of the liquid crystal array.

In Embodiment 2 of the present invention, the manufacturing method of the display substrate included in the liquid crystal display is substantially the same as the manufacturing method of the display substrate included in the liquid crystal display described with reference to FIGS. 8A to 8C. Therefore, duplicate descriptions are omitted.

According to the second exemplary embodiment of the present invention, since the counter substrate 200 disposed on the second pixel electrode 147 having slits has the common electrode hole 245, the direction of liquid crystal array is varied so that the viewing angle is varied. This may be improved, and since the liquid crystal layer 300 includes a reactive mesogen, the viewing angle may be further improved.

Example 3

14 is a plan view of a liquid crystal display according to a third embodiment of the present invention. FIG. 15 is a cross-sectional view taken along the line IX-IX 'of FIG. 14.

In Embodiment 3 of the present invention, the display substrate 100 is not divided into two domains, the first domain D1 and the second domain D2, so that the first domain D1 of Embodiment 1 is one pixel region. A liquid crystal display described with reference to FIGS. 1 to 3 except that boosting lines and boosting electrodes are not required to configure PA and separately drive the first and second domains D1 and D2. It is substantially the same as the device. Therefore, corresponding reference numerals are used for corresponding elements, and duplicate descriptions are omitted.

14 and 15, the liquid crystal display according to Embodiment 3 of the present invention includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300.

The display substrate 100 includes a base substrate 110 in which a pixel region is defined. The gate wiring GL, the gate insulating film 120, the first data wiring DL1, the second data wiring DL2, the data insulating film 130, the contact electrode 90, and the pixel are disposed on the first base substrate 110. The electrode 345, the transistor TFT, and the lower alignment layer 150 are formed.

The gate line GL is formed on the base substrate 110 and extends along the first direction DI1.

The gate insulating layer 120 is formed on the first base substrate 110 to cover the gate line GL and the gate electrode GE extending from the gate line GL.

The first and second data lines DL1 and DL2 are formed on the gate insulating layer 120 and extend along a second direction DI2 crossing the first direction DI1. In this case, the first and second directions DI1 and DI2 may be perpendicular to each other.

The transistor TFT includes a gate electrode GE, an active electrode AE, a source electrode SE, and a drain electrode DE.

The gate electrode GE may be part of the gate line GL. The active electrode AE is formed on the gate insulating layer 120 to overlap the gate electrode GE.

The source electrode SE is branched from the data line DL.

The drain electrode DE is formed spaced apart from the source electrode SE.

The drain electrode DE extends to be electrically connected to the contact electrode 90.

The contact electrode 90 is formed on the gate insulating layer 120 and formed in unit pixels, respectively. The contact electrode 90 may have, for example, a rectangular shape when viewed from a plane.

The data insulating layer 130 is formed on the gate insulating layer 120 to cover the data lines DL1 and DL2, the source electrode SE, the drain electrode DE, and the contact electrode 90. . The data insulating layer 130 may include an inorganic insulating layer 131 and an organic insulating layer 132. The inorganic insulating layer 131 is formed to cover the organic insulating layer 132.

A contact hole 333 is formed in the data insulating layer 130 on the contact electrode 90.

The pixel electrode 345 is formed on the data insulating layer 130. The pixel electrode 345 may be a metal pattern formed by patterning from a transparent metal layer.

The pixel electrode 345 contacts the contact electrode 90 from which the drain electrode DE of the transistor TFT extends, and defines a plurality of cutouts 360 formed to define the pixel area PA. Has

In addition, since the outer region of the pixel electrode 345 has an open loop shape, the cutouts 360 have a shape formed through the inside of the pixel electrode 345 to the outside.

The cutting grooves 360 of the pixel electrode 345 are formed by defining four subdomains in the pixel area PA. The cutouts 360 are formed parallel to each other in one subdomain area. Accordingly, the remaining area of the pixel electrode 345 except for the cutouts 360 has a shape in which a plurality of slits are arranged.

In addition, the slits may be formed radially toward the center of the pixel electrode 345. The slits may be arranged side by side in the first direction DI1 and may be arranged side by side in the second direction DI2.

The lower alignment layer 150 is formed on the first base substrate 110 on which the pixel electrode 345 is formed, so that the liquid crystal molecules of the liquid crystal layer 300 are opposed to each other in a vertical direction, that is, from the display substrate 100. In the direction facing 200).

The opposing substrate 200 is disposed to face the display substrate 100.

The opposing substrate 200 may include an upper substrate 210, a light blocking pattern BM, a color filter pattern 220, an overcoating layer 230, a common electrode 240, and an upper alignment layer 250.

The light blocking pattern BM is formed on the upper substrate 201 to correspond to the data lines DL1 and DL2 and the transistor TFT. Therefore, the color filter pattern 220 is formed in the pixel area PA that is not shielded.

The common electrode 240 is formed on the overcoat layer 230. The common electrode 240 has a common electrode hole 443 at the center thereof. The common electrode hole 443 serves to arrange liquid crystals of the liquid crystal layer 300 toward the common electrode hole 443 when an electric field is applied.

Here, in the third exemplary embodiment of the present invention, the common electrode hole 443 is arranged at the center and has a quadrangular shape. May be

The upper alignment layer 250 is formed on the common electrode 240 to vertically align the liquid crystal layer 300.

The liquid crystal layer 300 is interposed between the display substrate 100 and the opposing substrate 200. The arrangement of liquid crystals in the liquid crystal layer 300 is changed by an electric field formed between the pixel electrode 345 and the common electrode 240, and as a result, the light transmittance of the liquid crystal layer 300 depends on the intensity of the electric field. Subject to change.

In Embodiment 3 of the present invention, the manufacturing method of the display substrate included in the liquid crystal display device is not divided into two domains, the first domain D1 and the second domain D2. The first domain D1 of the pixel region PA constitutes one pixel area PA, and boosting lines and boosting electrodes are not required to separately drive the first domain D1 and the second domain D2. Except for the same, the manufacturing method of the display substrate included in the liquid crystal display device illustrated in FIGS. 8A to 8C is substantially the same. Therefore, duplicate descriptions are omitted.

According to the third exemplary embodiment of the present invention, since the opposing substrate 200 disposed on the pixel electrode 345 having slits has the common electrode hole 443, a sufficient viewing angle is ensured so that the liquid crystal layer ( Since the 300) does not need to contain a reactive mesogen and the UV irradiation process can be omitted, the manufacturing process can be simplified.

According to embodiments of the present invention, by having a hybrid structure using both the circularly polarized light mPVA mode and the SVA mode at the same time, the side visibility is improved compared to the existing circularly polarized light mPVA, and the transmittance may be improved due to the use of the circularly polarized polarizing plate. In addition, since the first pixel electrode and the second pixel electrode can implement dual gamma through the first boosting signal and the second boosting signal, side visibility is improved.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

1 is a plan view of a liquid crystal display according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is a cross-sectional view taken along the line II-II 'of FIG. 1.

4 is a circuit diagram illustrating an electrical connection relationship in FIG. 1.

5A is a waveform diagram illustrating a first pixel voltage corresponding to the first pixel electrode of FIG. 4.

5B is a waveform diagram illustrating a second pixel voltage corresponding to the second pixel electrode of FIG. 4.

FIG. 6 is a cross-sectional view taken along line III-III ′ of FIG. 1.

FIG. 7 is a cross-sectional view taken along the line IV-IV ′ of FIG. 1.

FIG. 1 is a cross-sectional view illustrating a comparison between a first storage capacitor and a second storage capacitor of the liquid crystal display shown in FIG. 1.

8A through 8C are cross-sectional views illustrating a method of manufacturing a display substrate included in the liquid crystal display shown in FIG. 3.

9 is a plan view of a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along the line VV ′ of FIG. 9.

FIG. 11 is a cross-sectional view taken along the line VI-VI 'of FIG. 9.

12 is a cross-sectional view taken along the line VII-VII ′ of FIG. 9.

FIG. 13 is a cross-sectional view taken along the line VIII-VIII ′ of FIG. 9.

14 is a plan view of a liquid crystal display according to a third embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line IX-IX 'of FIG. 14.

<Description of the symbols for the main parts of the drawings>

100: display substrate 110: base substrate

120 gate insulating film 130 data insulating film

131: inorganic insulating film 132: organic insulating film

133: first contact hole 135: second contact hole

145: first pixel electrode 147: second pixel electrode

150: lower alignment layer 200: counter substrate

210: upper substrate 220: color filter pattern

230: overcoating layer 240: common electrode

243: first common electrode hole 245: second common electrode hole

250: upper alignment layer 300: liquid crystal layer

10: first boosting electrode 30: second boosting electrode

50: first contact electrode 70: second contact electrode

BL1: first boosting line BL2: second boosting line

Claims (21)

Gate lines; A data line crossing the gate line; A transistor connected to the gate line and the data line; A first pixel electrode connected to a first output electrode of the transistor and having a plurality of first cutouts formed to define a first domain; And And a second pixel electrode connected to the second output electrode of the transistor. The method of claim 1, wherein the gate line is disposed between the first pixel electrode and the second pixel electrode, and a voltage is simultaneously applied to the first pixel electrode and the second pixel electrode by the transistor. Indicator board. The display substrate of claim 1, wherein an outer region of the first pixel electrode defines an open loop shape, and an outer region of the second pixel electrode defines a closed loop shape. The display substrate of claim 1, wherein the first incision grooves are formed by defining four groups in the first domain, and the first incision grooves are parallel to each other in the same group. The semiconductor device of claim 1, further comprising: a first boosting electrode overlapping the first output electrode of the transistor to define a first storage capacitor; And And a second boosting electrode overlapping the second output electrode of the transistor to define a second storage capacitor. The display substrate of claim 5, wherein the first boosting electrode and the second boosting electrode include a transparent material. The display substrate of claim 5, wherein a size of the first boosting electrode is smaller than a size of the second boosting electrode. The semiconductor device of claim 5, further comprising: a first boosting line formed in parallel with the gate line and electrically connected to the first boosting electrode; And And a second boosting line formed in parallel with the gate line and electrically connected to the second boosting electrode. The display substrate of claim 1, wherein an outer size of the first pixel electrode is larger than an outer size of the second pixel electrode. Forming a transistor electrically connected to the gate line and the data line crossing each other; And Forming a first pixel electrode connected to a first output electrode of the transistor and having a plurality of first cutout grooves defined to define a first domain, and a second pixel electrode connected to a second output electrode of the transistor; Method for producing a display substrate comprising. The semiconductor device of claim 10, further comprising: a first boosting line and a second boosting line for boosting the first pixel electrode and the second pixel electrode by patterning a first metal layer deposited on a base substrate; Forming the gate line; And Depositing and patterning a transparent metal layer on the base substrate having the first boosting line, the second boosting line, the gate electrode, and the gate line to electrically connect the first boosting line and the second boosting line, respectively. The method of claim 1, further comprising forming a first boosting electrode and a second boosting electrode. The method of claim 11, wherein the size of the first boosting electrode is smaller than that of the second boosting electrode. A gate line, a data line crossing the gate line, a transistor connected to the gate line and the data line, and a plurality of first cutouts connected to the first output electrode of the transistor and formed to define a first domain A display substrate comprising a first pixel electrode having a second pixel electrode connected to a second output electrode of the transistor; An opposite substrate facing the display substrate and including a common electrode; And And a liquid crystal layer interposed between the display substrate and the counter substrate. The semiconductor device of claim 13, further comprising: a first boosting electrode forming a first output electrode and a first storage capacitor of the transistor; And And a second boosting electrode forming a second output electrode and a second storage capacitor of the transistor. 15. The liquid crystal display of claim 14, wherein the first pixel electrode and the second pixel electrode include first and second contact holes electrically connected to the first and second output electrodes, respectively. Device. The liquid crystal display of claim 15, wherein the counter substrate comprises a common electrode having a first common electrode hole and a second common electrode hole corresponding to a central portion of each of the first and second pixel electrodes. . The liquid crystal display of claim 16, wherein the first contact hole and the second contact hole are disposed to overlap the first common electrode hole and the second common electrode hole, respectively. The liquid crystal display of claim 15, wherein the counter substrate comprises a common electrode having a common electrode hole corresponding to a center portion of the second pixel electrode. 19. The liquid crystal display of claim 18, wherein the second contact hole is disposed to overlap the common electrode hole. 20. The liquid crystal display device according to claim 19, wherein the liquid crystal layer comprises a reactive mesogen. A display substrate including a gate line, a data line crossing the gate line, a transistor connected to the gate line and the data line, and a pixel electrode having a plurality of cutout grooves connected to the transistor and defined to define a pixel region. ; A counter substrate opposing the display substrate and including a common electrode having a common electrode hole; And And a liquid crystal layer interposed between the display substrate and the counter substrate.

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