KR20100066318A - Display device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A display device and a manufacturing method thereof are provided to prevent block dim or noise, thereby improving picture quality. CONSTITUTION: A plurality of pattern lines(147a,147b) and a plurality of contact electrodes(141,143) are formed on a substrate(131). An anisotropic conductive film(150) including a plurality of conductive balls(152) is arranged on the substrate. A plurality of driving circuits is arranged on the substrate. The conductive balls are electrically connected to the contact electrodes by bumps(156) of the driving circuits. Contact layers(158) are formed by applying a laser beam to contact areas.

Description

Display device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device and a method of manufacturing the same that can prevent contact failure of a driver IC in a COG method.

Due to the development of the information society, display devices capable of displaying information have been actively developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Among these, the liquid crystal display device has advantages such as light weight, small size, low power consumption, and full color video, and is widely applied to mobile phones, navigation, monitors, and televisions.

The liquid crystal display device includes a liquid crystal panel including two substrates and a liquid crystal layer interposed between the substrates, and a driving integrated circuit is positioned in an outer region of the liquid crystal panel.

The driving integrated circuit is divided into a chip on glass (COG) method, a tape carrier package (TCP) method, and a chip on film (COF) method according to the method of mounting the liquid crystal panel. .

Among them, the COG method has a simple structure and easy mounting method compared to the TCP method, and thus is widely applied to small and medium panels.

1 is a plan view illustrating a liquid crystal display of a conventional COG method.

As shown in FIG. 1, a conventional COG type liquid crystal display device includes first and second substrates 11 and 13 and a liquid crystal layer (not shown) interposed between the substrates 11 and 13. do. An area in which the first and second substrates 11 and 13 overlap each other is defined as a display area 9 in which an image is displayed, and a first substrate in which the first and second substrates 11 and 13 do not overlap. The area of 11) is defined as the non-display area 10 in which no image is displayed.

A flexible printing circuit board (FPC) 3 is connected to the first substrate 11 in the non-display area 10 of the first substrate 11, and the gate driving integrated circuits 5 are connected to the non-display area 10. Data driving integrated circuits 25 to 27 are mounted. The gate driving integrated circuits 5 and the data driving integrated circuits 25 to 27 are mounted on a glass substrate, which is called a COG method.

A plurality of pattern lines 15a to 15d, 17a, and 17c are formed in the non-display area 10. That is, the gate pattern lines 17a and 17b for connecting the FPC 3 and the gate driver integrated circuits 5 and the data pattern for connecting the FPC 3 and the data driver integrated circuits 25 to 27. Lines 15a to 15d are provided. The data driving integrated circuits 25 to 27 are cascaded by data pattern lines 15a to 15d.

A gate line 21 is connected between the gate driving integrated circuits 5 and the display region 9, and data lines 23 are connected between the data driving integrated circuits 25 to 27 and the display region 9. Is connected by.

The power signals VDD, VDD_gnd, VCC, VCC_gnd, gamma voltage, data signal and control signal provided from the FPC 3 are supplied to the first data driving integrated circuit via the data pattern lines 15a to 15d. The data voltages generated by the power signal, the gamma voltage, the data signal and the control signal are supplied to the display area 9 via the data lines 23.

VDD and VDD_gnd are reference voltages of the gamma voltage, and VCC and VCC_gnd are voltages for driving the data driver integrated circuits 25 to 27. These power signals are values determined by the standard, and when fluctuating, they cause fluctuations in data voltages output from each of the data driving integrated circuits 25 to 27, resulting in noise or dim defects (Fig. 1). Block dim or block noise generation area).

These power signals VDD, VDD_gnd, VCC, and VCC_gnd are changed by contact failures between the data driving integrated circuits 25 to 27 and the data pattern lines 15a to 15d.

FIG. 2 is a plan view illustrating the data driving integrated circuit of FIG. 1.

As shown in FIG. 2, the data driver integrated circuits 25 to 27 have a plurality of bumps 31, 33, and 35. These bumps 31, 33, and 35 serve as bridges for connecting the data driving integrated circuits 25 to 27 and the data pattern lines 15a to 15d.

Input side bumps 31 and output side bumps 33 are provided at both ends of the data driving integrated circuits 25 to 27 in the longitudinal direction of the data driving integrated circuits 25 to 27, and bumps for outputting data signals are at other ends. Field 35 is provided.

Input side bumps 31 receive power signals VDD, VDD_gnd, VCC, and VCC_gnd, gamma voltages, data signals and control signals, and output side bumps 33 receive power signals, gamma voltages, data signals and control signals. Output Bumps 35 for data signal output output a data signal.

The gate driving integrated circuit 5 also includes bumps (not shown) for electrically connecting the gate pattern lines 17a and 17b and the gate lines 21.

3 is a cross-sectional view of the data driving integrated circuit and the first substrate when taken along the line II ′ in FIG. 2.

As illustrated in FIG. 3, the first substrate 11 includes a gate insulating layer 43, data pattern lines 45, a passivation layer 47, and contact electrodes 48. Reference numeral 41 is a substrate. The gate insulating film 43 is formed on the non-display area 1 of the substrate 11. The data pattern lines 45 are formed to be spaced apart from each other on the gate insulating layer 43. That is, the data pattern lines 45 are formed in the input terminal regions and the output terminal regions of the data driver integrated circuits 25 to 27. The passivation layer 47 is formed to expose the data pattern lines 45 on the gate insulating layer 43. Contact electrodes 48 are formed on the exposed data pattern lines 45. The contact electrodes 48 electrically connect the respective data driver integrated circuits 25 to 27 to the data pattern lines 45.

The first substrate 11 further includes an anisotropic conductive film (ACF) 49 disposed on the non-display area 10 and including the plurality of conductive balls 50. On the anisotropic conductive film 49 is placed a data drive integrated circuit 26 with bumps 31, 33.

The data driving integrated circuit 26 is pressurized by heat and pressure, which causes the bumps 31 and 33 of the data driving integrated circuit 26 to press the anisotropic conductive film 49 and the anisotropic conductive film 49. Will melt. Therefore, the conductive balls 50 included in the anisotropic conductive film 49 are electrically connected to the contact electrodes 48.

However, it is widely known that the adhesions between the anisotropic conductive film 49 and / or the conductive balls 50 and the contact electrodes 48 are very weak. In addition, as shown in FIG. 4, the anisotropic conductive film 49 is cured as time passes. Thus, the anisotropic conductive film 49 including the conductive balls 50 is detached from the contact electrodes 48 such that the conductive balls 50 are no longer connected to the contact electrodes 48. Therefore, contact defects occur in the contact terminal regions of the input terminal regions and / or output terminal regions of the data driver integrated circuits 25 to 27. The contact failure may be defined as a size in which bumps 31 and 33 overlap each contact electrode 48.

In addition, it is well known that the adhesion between the contact electrodes 48 and the data pattern lines 45 is also relatively weak. Thus, contact failure is further generated in the contact terminal regions of the input terminal regions and / or output terminal regions of the data driver integrated circuits 25 to 27.

Due to this contact failure, the contact resistance between the bumps 31 and 33 of the data driving integrated circuit 26 and the contact electrode 48 is increased. The increase in the contact resistance causes the power signals VDD, VDD_gnd, VCC, and VCC_gnd to vary, the gamma voltage, the data signal, and the control signal.

For example, while the voltage levels of the power signals VDD and VCC decrease, the voltage levels of the power signals VDD_gnd and VCC_gnd increase. The power signals VCC and VCC_gnd are used to drive the respective data driving integrated circuits 25 to 27, and the power signals VDD and VDD_gnd are used as reference voltages for generating gamma voltages.

As shown in FIG. 5, in a state where VCC is 2.7 V and VCC_gnd is 0 V, the contact resistance between the bumps 31 and 33 of the data driving integrated circuit 26 and the contact electrode 48 is reduced. Increasing, VCC is reduced to 2.6V, while VCC_gnd is increased to 0.4V, and the margin width of VCC is 2.2V. The reduced margin width prevents the data driver integrated circuit 26 from being driven.

In particular, when the data driving integrated circuits 26 are cascaded and contact failure occurs in the input terminal regions and the output terminal regions of each data driving integrated circuit 26, The margin between the power signal VCC and the power signal VCC_gnd is further reduced toward the last data driver IC 27. Accordingly, the other data driver integrated circuits 26 adjacent to the last data driver integrated circuit 27 are not driven. As such, the last data driver integrated circuit 27 and the other data driver integrated circuits 26 adjacent thereto are not driven so that no data voltage is supplied to the display area, so that block noise may be generated. A block is defined as an area including data lines of a display area connected to each data driving integrated circuit.

In addition, due to the increase in the contact resistance, the power signal VDD is decreased while the power signal VDD_gnd is increased, so that the gamma voltages are not generated as the set voltage but are generated as the variable voltage. Due to the variation of the gamma voltages, variations in the data voltages output from the data driving integrated circuits cause grayscale distortion. The gradation distortion becomes more severe toward the last data driving integrated circuit 27 than the first data driving integrated circuit 25. Therefore, due to the change of the power signals VDD and VDD_gnd due to the contact failure, gradation distortion occurs in the data lines of the display area respectively connected to the last data driver integrated circuit 27 and another data driver integrated circuit 26 adjacent thereto. This causes a block dim.

Contact failure is also generated between the bumps 31 and 33 of the data driving integrated circuit 26 and the data line 23, and the data supplied from the data driving integrated circuit 26 to the data line 23 is caused by the contact failure. Voltage distortion occurs.

Therefore, it is urgent to prevent contact defects at the source.

It is an object of the present invention to provide a display device and a method of manufacturing the same, in which all conductive balls in a contact region are electrically connected to a contact electrode, thereby preventing contact failure.

According to the present invention, a method of manufacturing a display device includes: forming a plurality of pattern lines and a plurality of contact electrodes connected thereto on a substrate; Disposing an anisotropic conductive film including a plurality of conductive balls on the substrate; Disposing a plurality of drive circuits on the substrate such that bumps correspond to the anisotropic conductive film; Applying heat and pressure to the drive circuits so that the conductive balls are electrically connected to the contact electrodes by bumps of the drive circuits; And irradiating laser light to contact regions to fuse the pattern lines and the contact electrodes to form a plurality of contact layers for connecting the conductive balls.

According to the present invention, a display device includes: a substrate formed of a pattern line and a contact electrode; A drive circuit having bumps; An anisotropic conductive film having a plurality of conductive balls; And a contact layer formed by melting the pattern line and the contact electrode, wherein the contact layer is connected to the conductive balls.

The present invention irradiates laser light to the contact regions to melt the data pattern lines and the data contact electrodes to form contact layers including the same, while forming a plurality of peaks on the contact layers, the peaks being conductive balls. While flowing down in contact with each other, they are bonded to each other, and the joined peaks and the contact layer are cured. Accordingly, since the conductive balls are strongly connected to the contact layers through the combined peaks, the image quality may be improved by preventing block dim or noise.

In addition, the present invention can solve the problem of adhesion weakness between the data line and the data contact electrodes by fusing the data pattern lines and the data contact electrodes with poor adhesion by the laser light irradiation to be mixed with each other.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

6 is a plan view showing a liquid crystal display of the COG method according to the present invention.

Referring to FIG. 6, the COG type liquid crystal display of the present invention includes first and second substrates 111 and 113 and a liquid crystal layer (not shown) interposed between the substrates 111 and 113. . The liquid crystal panel 101 is formed of the first and second substrates 111 and 113 and the liquid crystal layer. An area in which the first and second substrates 111 and 113 overlap each other is defined as a display area 125 in which an image is displayed, and a first substrate in which the first and second substrates 111 and 113 do not overlap. The region of 111 is defined as the non-display region 129 where no image is displayed. The display area 125 is defined as a plurality of sub display areas 126a, 126b, 127a, 127b, 128a, 128b, 129a, and 129b.

A flexible printing circuit board (FPC) 103 is connected to the first substrate 111 in the non-display area 129 of the first substrate 111, and the gate driving integrated circuits 105 are connected to the non-display area 129. The data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are mounted. The gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are mounted on the first substrate 111 made of glass, which is called a COG method. Name it.

In the present invention, an area in which the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are disposed is defined as a plurality of data driving regions 116 to 119.

Each data driving region 116-119 includes two plurality of data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, 119b. The data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b respectively correspond to the sub display areas 126a, 126b, 127a, 127b, 128a, 128b, 129a, and 129b. Data signals output from the respective data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are stored in the respective sub display areas 126a, 126b, 127a, 127b, 128a, 128b, 129a, and 129b. Is displayed.

In particular, data signals output from the data driver integrated circuit 116a of the first data driver region 116 are displayed in the sub display region 126a. Data signals output from the data driver integrated circuit 116b of the first data driver region 116 are displayed in the sub display region 126b. Data signals output from the data driver integrated circuit 117a of the second data driver region 117 are displayed in the sub display region 127a. Data signals output from the data driver integrated circuit 117b of the second data driver region 117 are displayed in the sub display region 127b.

The data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b disposed in the data driving regions 116 to 119 are connected to each other. For example, the data driving integrated circuits 116a and 116b disposed in the first data driving region 116 are cascaded to each other. The data driver integrated circuits 117a and 117b disposed in the second data driver region 117 are cascaded to each other. The data driving integrated circuits 118a and 118b disposed in the third data driving region 118 are cascaded to each other. The data driving integrated circuits 119a and 119b disposed in the fourth data driving region 119 are cascaded to each other.

The power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal provided from the FPC 103 are supplied to the first to fourth data driving regions 116 to 119, respectively. The power signals VDD and VDD_gnd are reference voltages of gamma voltages, and the power signals VCC and VCC_gnd are used to drive the data driver integrated circuits 116 to 119.

That is, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal provided from the FPC 103 are driven by the first data included in the first to fourth data driving regions 116 to 119, respectively. Applied to integrated circuits 116a, 117a, 118a, and 119a. The power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal applied to the first data driving integrated circuits 116a, 117a, 118a, and 119a may be used. And transfer to second data driver integrated circuits 116b, 117b, 118b, and 119b disposed adjacently adjacent to 118a and 119a. In this way, the power signals VDD, VDD_gnd, VCC, VCC_gnd, gamma voltage, data signal and control signal are transferred from the first data driver integrated circuits 116a, 117a, 118a and 119a to the last data driver integrated circuit 116b, 117b, 118b and 119b) sequentially.

In other words, in the first data driving region 116, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal applied to the first data driving integrated circuit 116a are adjacently cascaded. Applied to the second data driver integrated circuit 116b. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal are transmitted to the last data driver integrated circuit 116b.

In the second data driving region 117, the power signals VDD, VDD_gnd, VCC, and VCC_gnd applied to the first data driving integrated circuit 117a, the gamma voltage, the data signal, and the control signal are adjacently connected to the second data. Applied to the driver integrated circuit 117b. In this manner, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal and the control signal are transmitted to the last data driver integrated circuit 117b.

In the third data driving region 118, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal applied to the first data driving integrated circuit 118a are adjacently connected to the second data. Applied to the driver integrated circuit 118b. In this manner, power signals VDD, VDD_gnd, VCC, and VCC_gnd, gamma voltages, data signals, and control signals are transmitted to the last data driver integrated circuit 118b.

In the fourth data driving region 119, the power signals VDD, VDD_gnd, VCC, and VCC_gnd, the gamma voltage, the data signal, and the control signal applied to the first data driving integrated circuit 119a are adjacently connected to the second data. Applied to the driving integrated circuit 119b. In this manner, power signals VDD, VDD_gnd, VCC, and VCC_gnd, a gamma voltage, a data signal, and a control signal are transmitted to the last data driving integrated circuit.

The output signals provided by the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b included in the data driver regions 116 through 119 are respectively converted into the data driver integrated circuits 116a, 116b, The sub display areas 126a, 126b, 127a, 127b, 128a, 128b, 129a, and 129b corresponding to 117a, 117b, 118a, 118b, 119a, and 119b may be displayed as images.

A plurality of pattern lines 107, 147a, and 147b are formed in the non-display area 129. That is, the pattern lines may include the gate pattern lines 107, the FPC 103, and the data driver integrated circuits 116a, 117a, 118a for electrically connecting the FPC 103 and the gate driver integrated circuits 105. And data pattern lines 147a for electrically connecting between 119a and data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b for electrically connecting each other. Data pattern lines 147b are provided.

Each gate driving integrated circuit 105 and the display area 125 are connected by gate lines 121, and each data driving integrated circuit 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b is displayed. The regions 125 are connected by data lines 123.

Each data driving integrated circuit 116a, 116b, 117a, 117b, 118a, 118b, 119a, 119b includes a plurality of bumps (not shown). These bumps connect the gate driving integrated circuit 105 to the gate pattern lines 107 and each of the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, 119b to the data pattern lines 147a. , 147b) acts as a crosslinking agent.

The bumps electrically connect the gate driving integrated circuit 105 and the input pattern lines 147a on the input terminal regions on the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b. Input bumps and output pattern lines 147b on the output terminal regions on the gate driver integrated circuit 105 and the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b. Output side bumps for electrically connecting, gate line 121 and data lines (e.g., gate drive integrated circuit 105 and data drive integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b); Bumps for data signal output for electrically connecting 123.

The power signals VDD, VDD_gnd, VCC, VCC_gnd, gamma voltages, data signals and control signals input by the input bumps of the data driver integrated circuits 116a, 117a, 118a, and 119a are connected to other data adjacent through the output bumps. Input bumps of the driving integrated circuits 116b, 117b, 118b and 119b. The data signal output by the data signal output bumps is provided to the sub display areas 126a, 126b, 127a, 127b, 128a, 128b, 129a, and 129b through the data lines 123.

As described above, since the conductive balls included in the anisotropic conductive film are detached from the contact electrodes and the adhesion between the contact electrodes and the data pattern lines is weak, the contact is defined in the contact region defined between the bump and the data pattern line. Defects may occur.

The present invention divides two data driving integrated circuits 116a and 116b, 117a and 117b, 118a and 118b, 119a and 119b connected to each other into respective data driving regions 116 to 119. Accordingly, power signals VDD, VDD_gnd, VCC, and VCC_gnd, gamma voltages, data signals, and control signals are separately supplied to the data driving regions 116 to 119.

As a result, the number of data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b included in each data driving region 116 to 119 is significantly reduced. Power signals VDD, VDD_gnd, VCC, and VCC_gnd input to the last data driving integrated circuit of each data driving region 116 to 119, gamma voltage, data signal, and control signal input to the last data driving integrated circuit of FIGS. No fluctuation occurs in the block, and block dim or noise is not generated.

7A to 7F illustrate a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention. The data driving integrated circuits illustrated in FIGS. 7A to 7F may be applied to all of the data driving integrated circuits included in each data driving region described above. 7A to 7F limit the manufacturing process of the liquid crystal display device for eliminating contact defects between the bumps of the data driving integrated circuits and the data pattern lines, the present invention is not limited thereto. The same can be applied to the manufacturing process of the liquid crystal display device for eliminating contact defects between the and data lines.

6 and 7A to 7F, a manufacturing process of the following liquid crystal display device will be described.

As shown in FIG. 7A, the first substrate 111 may include a gate insulating layer 133, data pattern lines 147a and 147b, contact electrodes 141 and 143, and a protective layer 139 on the substrate 131. It is prepared by forming a.

In more detail, although not shown on the substrate 131, a gate metal film formed of a gate metal material is formed, and the gate metal film is patterned to form a gate line 121, a gate electrode, and a gate pattern electrode. The gate line is formed in the display area 125. In the display area 125, a plurality of pixels is defined as a matrix. One end of the gate line may extend to not only the display area 125 but also the non-display area 129. A gate electrode is formed in each pixel, and gate pattern lines 107 are formed between the gate driver integrated circuits 105 and between the FPC 103 and the gate driver integrated circuit 105. The gate insulating layer 133 is formed on the entire region of the substrate 131 including the gate line 121 using a gate insulating material.

A semiconductor material is formed on the gate insulating layer 133 and patterned to form a semiconductor layer.

A data metal film made of a data metal material is formed on the substrate 131 including the semiconductor layer, and the data metal film is patterned to form data lines 123, source / drain electrodes, and data pattern lines 147a and 147b. do. The data line 123 crosses the gate line 121. The pixel may be defined in the display area 125 by the intersection of the gate line 121 and the data line 123. The data line 123 may extend to the non-display area 129 as well as the display area 125. The source / drain electrodes are spaced apart from each other on the gate insulating layer 133 corresponding to the gate electrode. The data pattern lines 147a and 147b are interposed between the data driver integrated circuits 116a and 116b and 117a and 117b and 118a and 118b and 119a and 119b and the FPC 103 and the data driver integrated circuits 116a and 116b and 117a. , 117b, 118a, 118b, 119a, and 119b. The data metal material may be the same or different than the gate metal material.

The thin film transistor is composed of a gate electrode, a gate insulating film, a semiconductor layer, and a source / drain electrode. The thin film transistor is connected to a gate line and a data line defining each pixel.

The passivation layer 139 is formed on the substrate 131 including the data pattern lines 147a and 147b using an organic material or an inorganic material. Subsequently, the passivation layer 139 is patterned to expose a drain contact hole (not shown) where a portion of the drain electrode is exposed, and a data contact hole (not shown) that exposes an end region of the data line 123 extending to the non-display area 129. And a portion of the data pattern lines 147a and 147b form an exposed data pattern line contact hole 149. In addition, a gate contact hole (not shown) and gate pattern lines 107 exposing end regions of the gate line 121 extending to the non-display area 129 by patterning the passivation layer 139 and the gate insulating layer 133. A portion of the gate pattern contact hole (not shown) is formed.

A transparent conductive material such as ITO or IZO is formed and patterned on the passivation layer 139 to form a pixel electrode (not shown), a gate contact electrode (not shown), and a data contact electrode 141, 143. The pixel electrode is formed in each pixel and is electrically connected to the drain electrode through the drain contact hole. The gate contact electrode is formed to be electrically connected to the gate line 121 through the gate contact hole. In addition, the gate contact electrode is formed to be electrically connected to the gate pattern lines 107 through the gate pattern line contact hole. The data contact electrodes 141 and 143 are formed to be electrically connected to the data line 123 through the data contact holes. The data contact electrodes 141 and 143 are formed to be electrically connected to the data pattern lines 147a and 147b through the data pattern line contact holes.

As shown in FIG. 7B, the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, and 119a in the non-display area 129 of the first substrate 111. , Anisotropic conductive films 150 including conductive balls 152 randomly distributed in regions where 119b is to be positioned are positioned. That is, the anisotropic conductive films 150 may be located under the gate and data driving integrated circuits 105, 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b. In other words, the anisotropy is applied to the end region of the gate line 121, the end region of the data line 123, the end regions of the gate pattern line 107, and the end regions of the data pattern lines 147a and 147b, respectively. The conductive film 150 may be disposed.

As shown in FIG. 7C, heat is applied and pressure is applied to the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b to drive the gate. The bumps 156 of the integrated circuits 105 or the bumps 156 of the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b respectively form the conductive lines 152 by the gate lines (gates). 121, the gate pattern lines 107, the data lines 123, and the data pattern lines 147a and 147b.

That is, the gate driving integrated circuits 105 or the data driving integrated circuits are pressed by pressing the gate driving integrated circuits 105 or the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b. The bumps 156 provided in the fields 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b are pressed. Accordingly, the anisotropic conductive film 150 is pressed while the anisotropic conductive film 150 is melted. Thus, the anisotropic conductive film 150 is electrically connected to the gate contact electrodes and the data contact electrodes 141 and 143. In particular, the conductive balls 152 included in the anisotropic conductive film 150 are electrically connected to the gate contact electrodes and the data contact electrodes 141 and 143.

In the present invention, the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are described as being simultaneously mounted on the first substrate 111. The present invention is not limited thereto, and the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b may be sequentially mounted on the first substrate 111. It may be.

However, as shown in FIG. 7D, the anisotropic conductive film 150 is cured as time passes, and the conductive balls 152 and the anisotropic conductive film 150, the gate contact electrodes, and the data contact electrodes 141 are formed. 143 between the gate contact electrodes and the data contact electrodes 141 and 143 and the gate lines 121, the gate pattern lines 107, the data lines 123 and the data pattern lines 147a and 147b. The adhesion between) is very weak. Accordingly, the conductive balls 152 and the anisotropic conductive film 150 are detached from the gate contact electrodes and the data contact electrodes 141 and 143, and the gate contact electrodes and the data contact electrodes 141 and 143 are removed. The gate lines 121, the gate pattern lines 107, the data lines 123, and the data pattern lines 147a and 147b are detached from the gate lines 121. The contact failure is caused by the input terminal regions, output terminal regions, and signal output terminal regions of the gate driver integrated circuits 105 and the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b. In contact areas. Due to this contact failure, the contact resistance in the contact region increases, and ultimately, a defect such as block dim or block noise occurs.

In order to solve this problem, as shown in FIG. 7E, a laser beam (or a laser beam) is irradiated to a contact region inside the substrate 131 in a lower direction of the substrate 131 to form a double layer, that is, a gate line, in the contact region. Gates 121 and gate contact electrodes, gate pattern lines 107 and gate contact electrodes, data lines 123 and data contact electrodes 141 and 143 and data pattern lines 147a and 147b and The data contact electrodes 141 and 143 are melted. Accordingly, contact layers 158 are formed in each contact region. At the same time, a number of peaks 158a are formed on the top surface of each contact layer 158 by laser light. Peaks 158a are in contact with the respective conductive balls 152. The contact layer 158 is a double layer in the contact region, that is, gate lines 121 and gate contact electrodes, gate pattern lines 107 and gate contact electrodes, data lines 123 and data contact electrodes 141. And 143 and the data pattern lines 147a and 147b and the data contact electrodes 141 and 143 are fused.

As shown in FIG. 7F, after the irradiation of the laser light is completed, as time passes, the peaks 158a contacting the conductive balls 152 flow along the surface of each conductive ball 152 to be coupled to each other. Get off. In addition, the combined peaks 158b and the contact layer 158 are cured. Thus, the conductive balls 152 are strongly attached and connected to the contact layer 158, specifically the combined peaks 158, in the contact region.

As the laser source for emitting the laser light, a solid laser can be used. Solid state lasers may be Nd: YAG, ruby, KCl or RbCl. Among them, preferably, a solid laser made of Nd: YAG can be used as the laser source of the present invention. As the laser light of the present invention, pulsed laser light having a power in the range of 60 mJ to 120 mJ may be used.

Accordingly, as all conductive balls 152 included in the contact region are in contact with the contact layers 158, the contact resistance is significantly reduced. Thus, between the gate driving integrated circuits 105 and the gate lines 121 or the gate pattern lines, and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, 119b and data lines The desired power signal can be accurately transmitted without changing the signal between the 123 or the data pattern lines 147a and 147b.

In particular, a power signal VDD, VDD_gnd, VCC, VCC_gnd that is sensitive to contact propagation between the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b and the data pattern lines 147a and 147b. ), The gamma voltage, the data signal and the control signal are not changed, so that block dim or noise is not generated.

8A to 8E illustrate a method of manufacturing a liquid crystal display according to a second exemplary embodiment of the present invention.

As illustrated in FIG. 8A, the data pattern lines 147a and 147b, the gate insulating layer 133, the passivation layer 139, and the contact electrodes 141 and 143 may include the substrate (111 in FIG. 6). 131).

In detail, the gate lines 121, the gate electrodes (not shown), the gate pattern lines 107, and the data pattern lines 147a and 147b are formed of a gate metal film on the substrate 131. It is provided by forming (not shown) and patterning the gate metal film. The gate lines 121 are formed on the display area 125. A plurality of pixels is defined on the display area 125. The gate lines 121 extend to the non-display area 129 as well as the display area 125. Gate electrodes are formed on each pixel, and gate pattern lines 107 are formed between the gate driver integrated circuits 105 and between the gate driver integrated circuits 105 and the FPC 103. The data pattern lines 147a and 147b are interposed between the data driver integrated circuits 116a and 116b, 117a and 117b, 118a and 118b, 119a and 119b and the data driver integrated circuits 116a and 116b, 117a and 117b, 118a and 118b, 119a, and 119b and the FPC 103.

The gate insulating layer 133 is formed of a gay insulating material on the entire surface of the substrate 131 including the data pattern lines 147a and 147b.

The semiconductor layer (not shown) is provided by forming and patterning a semiconductor material on the gate insulating layer 133. In addition, the data lines 123 and the source / drain electrodes (not shown) are provided by forming and patterning a data metal film (not shown) made of a data metal material on the substrate 131 including the semiconductor layer. The source / drain electrodes are spaced apart from each other at predetermined intervals on the gate insulating layer 133 corresponding to the gate electrode. The data metal material may be the same or different than the gate metal material. The data lines 123 are formed to cross the gate lines 121. The pixels are defined by the gate lines 121 and the data lines 123 that cross each other on the display area 125. The data lines 123 extend to the non-display area 129 as well as the display area 125.

The gate electrode, the gate insulating layer 133, the semiconductor layer, and the source / drain electrodes constitute a thin film transistor TFT. The thin film transistor TFT is connected to the gate line 121 and the data line 123 that define the pixel.

The passivation layer 139 is formed of an organic or inorganic material on the substrate 131 including the data lines 123. Subsequently, the passivation layer 139 is patterned so that the drain contact hole (not shown) where the drain electrode is partially exposed and the data contact where the end regions of the data lines 123 extending to the non-display area 129 are partially exposed. Holes (not shown) are formed. In addition, the passivation layer 139 and the gate insulating layer 133 are patterned to expose the gate contact holes (not shown) and gate pattern lines (ie, end regions of the gate lines 121 extending to the non-display area 129). A gate pattern line contact hole (not shown) in which the 105 is partially exposed and a data pattern line contact hole 161 in which the data pattern lines 147a and 147b are partially exposed are formed.

A transparent conductive material such as ITO or IZO is formed and patterned on the passivation layer 139 to form a pixel electrode (not shown), a gate contact electrode (not shown), and a data contact electrode 141, 143. The pixel electrode is formed in each pixel and is electrically connected to the drain electrode through the drain contact hole. The gate contact electrode is formed to be electrically connected to the gate line 121 through the gate contact hole. In addition, the gate contact electrode is formed to be electrically connected to the gate pattern lines 107 through the gate pattern line contact hole. The data contact electrodes 141 and 143 are formed to be electrically connected to the data line 123 through the data contact holes. The data contact electrodes 141 and 143 are formed to be electrically connected to the data pattern lines 147a and 147b through the data pattern line contact hole 161.

8B-8E are similar to FIGS. 7B-7F except data pattern lines 147a, 147b.

As shown in FIG. 8B, anisotropic conductive films 150 are disposed on the non-display area 129 of the first substrate 111. Each of the anisotropic conductive films 150 may include a randomly distributed conductive material in regions where the gate driver integrated circuits 105 and the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b will be located. Balls 152. That is, the anisotropic conductive films 150 may be located under the gate and data driving integrated circuits 105, 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b. In other words, the end region of the gate line 121, the end region of the data line 123, the end regions of the gate pattern line 107, and the end regions of the data pattern lines 147a and 147b, respectively. Anisotropic conductive film 150 may be disposed. The gate drive integrated circuits 105 and the data drive integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b are arranged such that their bumps correspond to the respective anisotropic conductive film 15.

Subsequently, heat is applied and pressure is applied to the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b, thereby driving the gate driving integrated circuits 105. The bumps 156 of the bumps or the bumps 156 of the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b respectively form the gate lines 121 and the gate pattern. It is connected to the lines 107, the data lines 123 and the data pattern lines 147a and 147b.

That is, the gate driving integrated circuits 105 or the data driving integrated circuits are pressed by pressing the gate driving integrated circuits 105 or the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b. The bumps 156 provided in the fields 116a, 116b, 117a, 117b, 118a, 118b, 119a and 119b are pressed. Accordingly, the anisotropic conductive film 150 is pressed while the anisotropic conductive film 150 is melted. Thus, the anisotropic conductive film 150 is electrically connected to the gate contact electrodes and the data contact electrodes 141 and 143. In particular, the conductive balls 152 included in the anisotropic conductive film 150 are electrically connected to the gate contact electrodes and the data contact electrodes 141 and 143.

In the present invention, the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b are described as being simultaneously mounted on the first substrate 111. The present invention is not limited thereto, and the gate driving integrated circuits 105 and the data driving integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b may be sequentially mounted on the first substrate 111. It may be.

However, as shown in FIG. 8C, the anisotropic conductive film 150 is cured as time passes, and the conductive balls 152 and the anisotropic conductive film 150, the gate contact electrodes, and the data contact electrodes 141 are formed. 143 between the gate contact electrodes and the data contact electrodes 141 and 143 and the gate lines 121, the gate pattern lines 107, the data lines 123 and the data pattern lines 147a and 147b. The adhesion between) is very weak. Accordingly, the conductive balls 152 and the anisotropic conductive film 150 are detached from the gate contact electrodes and the data contact electrodes 141 and 143, and the gate contact electrodes and the data contact electrodes 141 and 143 are gated. Detachment is performed from the lines 121, the gate pattern lines 107, the data lines 123, and the data pattern lines 147a and 147b. The contact failure is caused by the input terminal regions, output terminal regions, and signal output terminal regions of the gate driver integrated circuits 105 and the data driver integrated circuits 116a, 116b, 117a, 117b, 118a, 118b, 119a, and 119b. In contact areas. Due to this contact failure, the contact resistance in the contact region increases, and ultimately, a defect such as block dim or block noise occurs.

In order to solve this problem, as shown in FIG. 8D, a laser beam (or a laser beam) is irradiated to a contact region inside the substrate 131 in a lower direction of the substrate 131 to form a double layer, that is, a gate line, in the contact region. Gates 121 and gate contact electrodes, gate pattern lines 107 and gate contact electrodes, data lines 123 and data contact electrodes 141 and 143 and data pattern lines 147a and 147b And melt the data contact electrodes 141, 143. Accordingly, contact layers 158 are formed in each contact region. At the same time, a number of peaks 158a are formed on the top surface of each contact layer 158 by laser light. Peaks 158a are in contact with the respective conductive balls 152. The contact layer 158 is a double layer in the contact region, that is, gate lines 121 and gate contact electrodes, gate pattern lines 107 and gate contact electrodes, data lines 123 and data contact electrodes 141. And 143 and the data pattern lines 147a and 147b and the data contact electrodes 141 and 143 are fused.

As shown in FIG. 8E, after the irradiation of the laser light is completed, as time passes, peaks 158a contacting the conductive balls 152 flow along the surface of each conductive ball 152 to be coupled to each other. Get off. In addition, the combined peaks 158b and the contact layer 158 are cured. Thus, the conductive balls 152 are strongly attached and connected to the contact layer 158, specifically the combined peaks 158, in the contact region.

Although the present invention has been described with reference to a liquid crystal display device, the present invention is not limited thereto and may be applied to an organic light emitting display device.

1 is a plan view illustrating a liquid crystal display of a conventional COG method.

FIG. 2 is a plan view illustrating the data driving integrated circuit of FIG. 1.

3 is a cross-sectional view of the data driving integrated circuit and the first substrate when taken along the line II ′ in FIG. 2.

4 is a view showing a contact failure in FIG.

5 is a diagram illustrating a change in voltage margin of a power signal due to a poor contact.

6 is a plan view showing a liquid crystal display of the COG method according to the present invention.

7A to 7F illustrate a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention.

8A to 8E illustrate a method of manufacturing a liquid crystal display according to a second exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: liquid crystal panel 103: FPC

105: gate driving integrated circuit 111: first substrate

113: second substrates 116 to 119: data driving region

116a, 116b, 117a, 117b, 118a, 118b, 119a, 119b: data driving integrated circuit

121: gate line 123: data line

125: display area

126a, 126b, 127a, 127b, 128a, 128b, 129a, 129b: sub display area

129: non-display area 131: substrate

133: gate insulating film 139: protective film

141 and 143: data contact electrodes 147a and 147b: data pattern line

150: anisotropic conductive film 152: conductive ball

156: bump

Claims (17)

Forming a plurality of pattern lines and a plurality of contact electrodes connected thereto on the substrate; Disposing an anisotropic conductive film including a plurality of conductive balls on the substrate; Disposing a plurality of drive circuits on the substrate such that bumps correspond to the anisotropic conductive film; Applying heat and pressure to the drive circuits so that the conductive balls are electrically connected to the contact electrodes by bumps of the drive circuits; And And irradiating laser light to contact regions to fuse the pattern lines and the contact electrodes to form a plurality of contact layers for connecting the conductive balls. The method of claim 1, wherein a plurality of peaks are formed on an upper surface of each contact layer by the laser light. The method of claim 2, wherein the peaks are in contact with the conductive balls. The method of claim 3, wherein the peaks flow along a surface of the conductive ball to be coupled to each other. The method of claim 4, wherein the combined peaks and the contact layers are cured as time passes. The method of claim 1, wherein the laser light is emitted from a solid state laser. The method of claim 6, wherein the solid state laser comprises any one of an Nd: YAG laser, a ruby laser, a KCl laser, and an RbCl laser. The method of claim 1, wherein the laser light is emitted from a pulse laser having a power in a range of 60 mJ to 120 mJ. The method of claim 1, wherein the pattern lines include gate pattern lines and data pattern lines. A substrate formed of a pattern line and a contact electrode; A drive circuit having bumps; An anisotropic conductive film having a plurality of conductive balls; And A contact layer formed by melting the pattern line and the contact electrode, And the contact layer is connected to the conductive balls. The method of claim 10, A gate line formed on the substrate; An insulating film formed on the substrate including the gate line; A data line formed on the insulating layer to intersect the gate line; A protective film formed on the substrate including the data line; And a pixel electrode formed on the passivation layer. The display device of claim 11, wherein the pattern line is formed together with the gate line. The display device of claim 12, wherein the contact electrode is in contact with the pattern line through the insulating layer and the passivation layer. The display device of claim 11, wherein the pattern line is formed together with the data line. The display device of claim 14, wherein the contact electrode is in contact with the pattern line through the passivation layer. The display device of claim 11, wherein the contact electrode is formed together with the pixel electrode. The display device of claim 11, further comprising a plurality of peaks formed on an upper surface of the contact layer to contact the conductive balls.

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