KR20100065537A - Plasma display apparatus - Google Patents

Abstract

PURPOSE: A plasma display apparatus is provided to prevent a damage of switching elements with stabling a driving by secluding a supply of a waveform and preventing a wrong operation of the switching elements. CONSTITUTION: A plasma display panel(100) includes an electrode. A driver secludes a supply of a drive waveform and maintains a voltage of the electrode in a minimum voltage maintaining period of a vertical synchronizing signal in case of exceeding the drive waveform provided to the electrode to one cycle period of the vertical synchronization signal.

Description

Plasma Display Apparatus {Plasma Display Apparatus}

The present invention relates to a plasma display device.

The plasma display apparatus includes a plasma display panel.

The plasma display panel includes a phosphor layer formed in a discharge cell divided by a partition wall, and also includes a plurality of electrodes.

When the drive signal is supplied to the electrode of the plasma display panel, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generate. The visible light displays an image on the screen of the plasma display panel.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display apparatus which cuts off the supply of waveforms when the waveform overflows so that waveforms of two adjacent frames do not overlap.

In the plasma display device according to the present invention, when the driving waveform supplied to the plasma display panel including the electrode and the electrode exceeds one cycle period of the vertical synchronization signal Vsync, the supply of the driving waveform in the minimum voltage holding period of the vertical synchronization signal is performed. It may include a driving unit to block the and maintain the voltage of the electrode.

In addition, in the lowest voltage sustain period of the vertical synchronization signal, the electrode may maintain the voltage of the ground level GND.

Another plasma display apparatus according to the present invention includes a plasma display panel that implements an image as a frame including a plurality of sub-fields, and a subfield including any two frames for the same image data. It may include a drive unit for varying the number.

In addition, any two frames for the same image data include a first frame and a second frame, and the number of subfields included in the second frame is less than the number of subfields included in the first frame, and the second frame includes the second frame. In the frame, the driving waveform supplied to the electrode of the plasma display panel exceeds one period of the vertical synchronization signal Vsync, and in the first frame, the driving waveform supplied to the electrode of the plasma display panel is one of the vertical synchronization signal Vsync. It may not exceed the cycle period.

In addition, the supply time of the first frame may be earlier than the supply time of the second frame, or the supply time of the second frame may be earlier than the supply time of the first frame.

Another plasma display apparatus according to the present invention includes a plasma display panel for implementing an image in a frame including a plurality of sub-fields and a subfield including any two frames for the same image data. It may include a driving unit for varying the length of any one of the subfields.

In addition, any two frames for the same image data may include a first frame and a second frame, and the length of the first subfield among the subfields included in the second frame may be the first among the subfields included in the first frame. Shorter than the length of the tenth subfield corresponding to the first subfield of the two frames, and in the second frame, the driving waveform supplied to the electrode of the plasma display panel exceeds one cycle period of the vertical synchronization signal Vsync, and the first In the frame, the driving waveform supplied to the electrode of the plasma display panel may not exceed one cycle period of the vertical synchronization signal Vsync.

In addition, the first subfield and the tenth subfield may have the same weight and the arrangement order.

The first subfield may be the last subfield among the plurality of subfields of the second frame, and the tenth subfield may be the last subfield of the plurality of subfields of the first frame.

Plasma display device according to the present invention by preventing the supply of the waveform when the waveform overflows to prevent the malfunction of the switching (Switching) element to stabilize the drive, and also has the effect of preventing the damage of the switching elements.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining the configuration of a plasma display device according to an embodiment of the present invention.

Referring to FIG. 1, a plasma display apparatus according to an exemplary embodiment may include a plasma display panel 100 and a driver 110.

The plasma display panel 100 may include scan electrodes Y1 to Yn and sustain electrodes Z1 to Zn that are parallel to each other, and may include address electrodes X1 to Xm that cross the scan electrode and the sustain electrode. In addition, the plasma display panel 100 may implement an image in a frame including a plurality of subfields.

The driver 110 may supply a driving signal to at least one of a scan electrode, a sustain electrode, and an address electrode of the plasma display panel 100 to implement an image on the screen of the plasma display panel 100. Preferably, the driving unit 110 supplies the driving waveform in the minimum voltage holding period of the vertical synchronization signal when the driving waveform supplied to the electrode of the plasma display panel 100 exceeds one cycle period of the vertical synchronization signal Vsync. Can cut off and maintain the voltage of the electrode.

Here, in FIG. 1, only the case in which the driving unit 110 is formed in one board form is illustrated, but in the present invention, the driving unit 110 is divided into a plurality of board forms according to electrodes formed on the plasma display panel 100. It is also possible to lose. For example, the driver 110 may include a first driver (not shown) for driving the scan electrode of the plasma display panel 100, a second driver for driving the sustain electrode, and a third driver (not shown) for driving the address electrode. Can be divided into

2 is a diagram for explaining the structure of a plasma display panel.

Referring to FIG. 2, the plasma display panel 100 includes a front substrate 201 in which scan electrodes 202 and Y and sustain electrodes 203 and Z are parallel to each other, and scan electrodes 202 and Y and a sustain electrode ( The back substrate 211 on which the address electrodes 213 and X intersect with 203 and Z may be formed.

On the front substrate 201 where the scan electrodes 202 and Y and the sustain electrodes 203 and Z are formed, the discharge currents of the scan electrodes 202 and Y and the sustain electrodes 203 and Z are limited and the scan electrodes 202 and Y are restricted. ) And an upper dielectric layer 204 may be arranged to insulate between the sustain electrodes 203 and Z.

A protective layer 205 may be formed on the front substrate 201 where the upper dielectric layer 204 is formed to facilitate discharge conditions. The protective layer 205 may include a material having a high secondary electron emission coefficient, such as magnesium oxide (MgO) material.

The address electrodes 213 and X are formed on the rear substrate 211, and the address electrodes 213 and X are covered on the upper side of the rear substrate 211 on which the address electrodes 213 and X are formed. A lower dielectric layer 215 may be formed that insulates X).

On top of the lower dielectric layer 215, a partition space 212, such as a stripe type, a well type, a delta type, a honeycomb type, etc., is formed on the discharge space, that is, to partition the discharge cells. Can be. Accordingly, the first discharge cell emitting red (R) light, the second discharge cell emitting blue (B) light, and the green (Green) light between the front substrate 201 and the rear substrate 211. : G) A third discharge cell or the like that emits light can be formed.

The partition 212 may include a first partition 212b and a second partition 212a, and a height of the first partition 212b and a height of the second partition 212a may be different from each other.

In the discharge cell, the address electrode 213 may cross the scan electrode 202 and the sustain electrode 203. That is, the discharge cell is formed at the point where the address electrode 213 crosses the scan electrode 202 and the sustain electrode 203.

A predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, a first phosphor layer that generates red light, a second phosphor layer that generates blue light, and a third phosphor layer that generates green light may be formed.

In addition, the address electrode 213 formed on the rear substrate 211 may have substantially the same width or thickness, but the width or thickness inside the discharge cell may be different from the width or thickness outside the discharge cell. . For example, the width or thickness inside the discharge cell may be wider or thicker than that outside the discharge cell.

When a predetermined signal is supplied to at least one of the scan electrode 202, the sustain electrode 203, and the address electrode 213, discharge may occur in the discharge cell. As such, when discharge is generated in the discharge cell, ultraviolet rays may be generated by the discharge gas filled in the discharge cell, and the ultraviolet rays may be irradiated onto the phosphor particles of the phosphor layer 214. Then, a predetermined image may be displayed on the screen of the plasma display panel 100 by the phosphor particles irradiated with ultraviolet rays to emit visible light.

FIG. 3 is a diagram for describing an image frame for implementing gradation of an image.

Referring to FIG. 3, a frame for implementing gray levels of an image may include a plurality of subfields SF1 to SF8.

In addition, the plurality of subfields may include a sustain period for implementing gradation according to an address period and a number of discharges for selecting discharge cells in which discharge cells will not occur or discharge cells in which discharge occurs. Period) may be included.

For example, in case of displaying an image with 256 gray levels, for example, one frame is divided into eight subfields SF1 to SF8 as shown in FIG. 3, and each of the eight subfields SF1 to SF8 is an address. It can include a period and a sustain period.

Alternatively, at least one subfield of the plurality of subfields of the frame may further include a reset period for initialization.

In addition, at least one subfield of the plurality of subfields of the frame may not include a sustain period.

Meanwhile, the weight of the corresponding subfield may be set by adjusting the number of sustain signals supplied in the sustain period. That is, a predetermined weight can be given to each subfield using the sustain period. For example, the weight of each subfield is 2 ⁿ by setting the weight of the first subfield to 2 ⁰ and the weight of the second subfield to 2 ¹ (where n = 0, 1, 2, 3, 4, 5, 6, 7) can be set to increase the ratio. As described above, gray levels of various images may be realized by adjusting the number of sustain signals supplied in the sustain period of each subfield according to the weight in each subfield.

In FIG. 3, only one image frame is composed of eight subfields. However, the number of subfields constituting one image frame may be variously changed. For example, one video frame may be configured with 12 subfields from the first subfield to the twelfth subfield, or one video frame may be configured with 10 subfields.

In addition, in FIG. 3, subfields are arranged in an order of increasing weight in one image frame. Alternatively, subfields may be arranged in an order of decreasing weight in one image frame. Subfields may be arranged regardless.

At least one of the plurality of subfields included in the frame may be a selective erase subfield (SE), and at least one of the plurality of subfields may be a selective write subfield (SW). Do.

If one frame includes at least one selective erase subfield and an optional write subfield, the first subfield or the first and second subfields of the plurality of subfields of the frame are the selective write subfields, It may be desirable for the remainder to be selective erasure subfields.

Here, the selective erasing subfield is a subfield that turns off the discharge cells supplied with the data signal Data to the address electrodes in the address period in the sustain period after the address period.

The selective erasure subfield may include an address period for selecting a discharge cell to be turned off and a sustain period for generating sustain discharge in discharge cells not selected in the address period.

The selective write subfield is a subfield that turns on the discharge cells supplied with the data signal Data to the address electrodes in the address period in the sustain period after the address period.

The selective write subfield may include a reset period for initializing the discharge cells, an address period for selecting the discharge cells to be turned on, and a sustain period for generating sustain discharge in the discharge cells selected in the address period.

4 is a view for explaining an example of a driving waveform for operating the plasma display device. The driving waveform to be described below is supplied by the driving unit 110 of FIG. 1.

Referring to FIG. 4, in the reset period RP for initializing at least one subfield among a plurality of subfields of a frame, the reset signal RS is applied to the scan electrode Y. Can supply Here, the reset signal RS may include a rising ramp signal (Ramp-Up: RU) in which the voltage gradually rises and a falling ramp signal (Ramp-Down: RD) in which the voltage gradually falls.

For example, the rising ramp signal RU may be supplied to the scan electrode in the setup period SU of the reset period, and the falling ramp signal RD may be supplied to the scan electrode in the setdown period SD after the setup period. .

When the rising ramp signal is supplied to the scan electrode, a weak dark discharge, that is, setup discharge, occurs in the discharge cell by the rising ramp signal. By this setup discharge, the distribution of wall charges can be uniform in the discharge cells.

After the rising ramp signal is supplied, when the falling ramp signal is supplied to the scan electrode, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated can be uniformly retained in the discharge cells.

In the address period AP after the reset period, the scan reference signal Ybias having a voltage higher than the lowest voltage of the falling ramp signal may be supplied to the scan electrode.

In addition, in the address period, the scan signal Sc that falls from the voltage of the scan reference signal Ybias may be supplied to the scan electrode.

Meanwhile, the pulse width of the scan signal supplied to the scan electrode in the address period of at least one subfield may be different from the pulse width of the scan signal of another subfield. For example, the width of the scan signal in the subfield located later in time may be smaller than the width of the scan signal in the preceding subfield. In addition, the reduction of the scan signal width according to the arrangement order of the subfields can be made gradually, such as 2.6 Hz (microseconds), 2.3 Hz, 2.1 Hz, 1.9 Hz, or 2.6 Hz, 2.3 Hz, 2.3 Hz, 2.1 Hz. .... 1.9 ㎲, 1.9 ㎲ and so on.

As such, when the scan signal is supplied to the scan electrode, the data signal Dt may be supplied to the address electrode X corresponding to the scan signal.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage generated by the wall charges generated in the reset period are added. .

In addition, the sustain reference signal Zbias signal may be supplied to the sustain electrode in the address period in which the address discharge occurs so that the address discharge is effectively generated between the scan electrode and the address electrode.

In the sustain period SP after the address period, the sustain signal SUS may be supplied to at least one of the scan electrode and the sustain electrode. For example, a sustain signal may be alternately supplied to the scan electrode and the sustain electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal, and a sustain discharge, i.e., display between the scan electrode and the sustain electrode when the sustain signal is supplied. Discharge may occur.

In this way, an image can be realized.

5 is a view for explaining the driving unit in more detail, and FIGS. 6 to 9 are views for explaining the operation of the driving unit.

When the driving waveform supplied to the electrode of the plasma display panel exceeds one period (T) period of the vertical synchronization signal Vsync, the driving unit cuts off the supply of the driving waveform and maintains the voltage of the electrode in the minimum voltage holding period of the vertical synchronization signal. I can keep it. Preferably, in the lowest voltage holding period of the vertical synchronization signal, the electrode may maintain the voltage of the ground level GND.

To this end, the driving unit may include the operation unit 500 and the storage unit 510 as shown in FIG. 5.

The storage unit 510 may store information about a driving waveform to be used when another driving waveform exceeds one cycle period of the vertical synchronization signal in the displayed image.

In addition, the operation unit 500 receives the timing control signal TS1 and the vertical synchronization signal Vsync, and the driving waveform according to the image displayed using the timing control signal TS1 and the vertical synchronization signal Vsync is vertical. It can be determined whether or not one period of the synchronization signal is exceeded. Here, the case where the driving waveform according to the displayed image exceeds one cycle period of the vertical synchronization signal may be referred to as a case where the waveform overflows.

The timing control signal TS1 supplied to the calculator 500 may be supplied by a timing controller that controls the overall driving of the plasma display panel.

When the driving waveform according to the displayed image exceeds one cycle period of the vertical synchronization signal, the calculation unit 500 may output the timing control signal TS2 according to the information stored in the storage unit 510. Here, the timing control signal TS2 output from the calculator 500 may be supplied to switching elements for supplying a driving waveform to the electrode of the plasma display panel.

Then, the driving waveform according to the information stored in the storage unit 510 may be supplied to the plasma display panel by the timing control signal TS2 output from the calculator 500.

For example, the storage unit 510 may store information for maintaining voltages of the scan electrode, the sustain electrode, and the address electrode of the plasma display panel when the waveform overflows, and the calculation unit 500 may overflow the waveform. The supply of the driving waveform may be cut off and the information stored in the storage unit 510 may be fetched so that the voltages of the scan electrodes, the sustain electrodes, and the address electrodes of the plasma display panel may be substantially constant.

The operations of the operation unit 500 and the storage unit 510 will be described in detail with reference to FIGS. 6, 7, 8, and 9 as follows.

6A shows an example of a drive waveform in a normal situation in which the waveform does not overflow. Although only one example of the driving waveforms supplied to the scan electrodes is shown here, the driving waveforms supplied to the sustain electrodes and the address electrodes in addition to the scan electrodes can be similarly applied.

In a normal situation where the waveform does not overflow, the driving waveform is supplied to the electrode of the plasma display panel within the period of one period T of the vertical synchronization signal as shown in (a).

On the other hand, when the waveform overflows, as shown in (b), the supply of the driving waveform is not completed within the period of one period T of the vertical synchronization signal, and the period exceeds one period T of the vertical synchronization signal. The driving waveform over one period T of the vertical synchronization signal is indicated by the A region.

Such waveform overflow phenomenon may occur frequently due to noise generated during the supply of the normal drive waveform.

Alternatively, waveform overflow may occur even when a timing parameter is incorrectly set. In addition, a phenomenon may occur in which the timing parameter is changed due to noise.

As shown in FIG. 6B, when the waveform overflow occurs, a driving waveform of the previous frame and the next frame may overlap. In this case, an incorrect timing control signal is supplied to the switching elements for supplying the driving waveform. This can cause damage to the switching elements such as malfunctioning or even burning of the switching elements.

As shown in FIG. 6B, when the waveform overflow occurs, the supply of the driving waveform may be cut off to protect the switching elements from damage and to prevent the switching elements from malfunctioning.

For example, as shown in FIG. 7B, the supply of the sustain signal can be interrupted during the supply of the sustain signal in the sustain period.

FIG. 7A illustrates a driving waveform in a steady state in which waveform overflow does not occur, and FIG. 7B illustrates an example of a driving waveform when waveform overflow occurs.

When (a) and (b) of FIG. 7 are compared, the number of sustain signals supplied in the sustain period of the nth subfield SFn among the plurality of subfields when the waveform overflow phenomenon occurs as shown in (b) is (a). It can be seen that the length of the n-th subfield SFn is shortened as the number of the subfields SFn becomes smaller than that in the normal state.

If the supply of the driving waveform is cut off when the waveform overflow occurs as shown in FIG. 7B, incorrect timing control signals can be prevented from being supplied to the switching elements for supplying the driving waveform. It is possible to prevent, and also to prevent damage to the switching elements.

In addition, the supply of the driving waveform is interrupted when the waveform overflows, and the voltage of the electrode can be kept substantially constant.

For example, as in the case of FIG. 8, it is possible to cut off the supply of the sustain signal when the waveform overflows, and to maintain the voltage at the ground level GND in the lowest voltage sustain period P of the vertical synchronization signal.

Alternatively, as in the case of FIG. 9, the electrode may maintain the predetermined voltage Vx in the minimum voltage holding period P of the vertical synchronization signal when the waveform overflows. Here, the predetermined voltage Vx is a voltage for preventing the wrong timing control signal from being supplied to the switching elements from the minimum voltage holding period P of the vertical synchronization signal, or may be a positive voltage or a negative voltage. It may be possible.

In this manner, after the supply of the driving waveform is prevented when the waveform overflows to prevent malfunction and damage of the switching element, the normal driving waveform can be supplied again in one period T of the next vertical synchronizing signal.

10 to 12 are diagrams for describing in detail a method of reducing the length of a subfield when a waveform overflows.

First, in FIG. 10, (a) is an example of a drive waveform in a steady state where no waveform overflow occurs, and (b) is an example of a drive waveform in a situation where waveform overflow occurs.

Here, assume that (a) is a driving waveform according to the first frame and (b) is a driving waveform according to the second frame.

(a) and (b) may be driving waveforms according to the same image data.

Here, the meaning that the first frame and the second frame are driving waveforms based on substantially the same image data may mean that the first frame and the second frame are substantially 100% identical images. For example, this may be the case when the image of one specific pattern is continuously displayed. However, while the first frame and the second frame are substantially the same image, the first frame and the second frame operate in the normal state, whereas in the second frame, waveform overflow occurs due to noise or the like.

Alternatively, the driving waveform according to the same image data as the first frame and the second frame may mean that the average power level (APL) of the first frame and the second frame is substantially the same. That is, even if the image data of the first frame and the second frame is not substantially 100% identical, the driving waveform according to the same image data of the first frame and the second frame if the average power level of the first frame and the second frame is the same. It can be regarded as.

In addition, when the average power level of the first frame and the second frame are the same, the total number of the sustain signals allocated to the first frame and the total number of the sustain signals allocated to the second frame may be substantially the same. Even when the first frame and the second frame are substantially the same image data, the total number of the sustain signals allocated to the first frame and the total number of the sustain signals allocated to the second frame are substantially the same.

Referring to FIG. 10, the lengths of any one of the subfields included in any two frames of the same image data may be different.

In detail, the length of the sustain period of the n-th subfield SFn of the first frame in the normal state as shown in (a) may be d1.

On the other hand, when the waveform overflow occurs, the supply of the driving waveform is cut off in the minimum voltage holding period P of the vertical synchronization signal, so that as shown in (b), the nth subfield SFn of the second frame in which the waveform overflow occurs is generated. The length of the sustain period may be d2 shorter than d1. Accordingly, the length of the nth subfield SFn of the second frame may be shorter than the length of the nth subfield SFn of the first frame.

In the case of Fig. 10B, the waveform overflow occurs during the supply of the sustain signal in the sustain period, so that the supply of the sustain signal is interrupted.

Here, the arrangement order and the weight of the weight in the first frame of the nth subfield SFn of the first frame are the same as the arrangement order and the weight in the second frame of the nth subfield SFn of the second frame. can do.

As described above, since the first frame and the second frame are substantially the same image data, in the normal state, the total number and length of the sustain signals allocated to the first frame and the second frame are substantially the same, but in the waveform overflow state. The lengths of the n-th subfield SFn of the first frame and the n-th subfield SFn of the second frame having the same weight and arrangement order are different from each other.

Next, referring to FIG. 11, the length of the address period of the n-th subfield SFn of the first frame in the normal state may be d3 as shown in (a).

On the other hand, if the waveform overflow occurs while the scan signal and the data signal are supplied in the address period, the length of the address period of the n-th subfield SFn of the second frame where the waveform overflow occurs is d3. Shorter d4. In this way, it may be possible to make the length of the nth subfield SFn of the second frame shorter than the length of the nth subfield SFn of the first frame.

Next, referring to FIG. 12, the length of the reset period of the n-th subfield SFn of the first frame in the normal state may be d5 as shown in (a).

On the other hand, if the waveform overflow occurs during the supply of the reset signal in the reset period, the length of the reset period of the n-th subfield SFn of the second frame in which the waveform overflow occurs as in the case of (b) is shorter than d5. Can be. In this way, it may be possible to make the length of the nth subfield SFn of the second frame shorter than the length of the nth subfield SFn of the first frame.

As described above, the nth subfield SFn of the plurality of subfields included in the first frame, that is, the nth subfield SFn of the plurality of subfields included in the last subfield and the second frame, that is, the last subfield. By varying the length of the field, it is possible to prevent malfunction and damage of the switching elements when the waveform overflows.

In addition, when the waveform overflow phenomenon is eliminated due to the reduction of the length of at least one subfield among the plurality of subfields and the noise is removed as described above, it is reduced to the normal state again. The length of the subfield can be returned to its original state.

Next, FIG. 13 is a diagram for describing a method of reducing the number of subfields when a waveform overflows. In the following, the description thereof will be omitted.

Referring to FIG. 13, the number of subfields included in any two frames for the same image data may be different.

In detail, the total number of subfields included in the first frame in the normal state as shown in (a) may be five (SF1 to SF5).

On the other hand, when the waveform overflow occurs due to noise or the like as in the region B shown in FIG. 13, the supply of the driving waveform is cut off during the minimum voltage holding period P of the vertical synchronization signal (b). As described above, the number of subfields included in the second frame in which the waveform overflow occurs may be four (SF1 to SF4) less than in the case of (a).

In FIG. 13B, the waveform overflow occurs before the fifth subfield SF5 is supplied, thereby omitting the fifth subfield SF5.

As such, when the waveform overflow occurs, it may be possible to prevent malfunction and damage of the switching element by reducing the number of subfields.

Next, FIG. 14 is a diagram for describing a method of simultaneously reducing the number of subfields and the length of a subfield when a waveform overflows.

Referring to FIG. 14, the number of subfields included in two arbitrary frames of the same image data and the length of the arbitrary subfields may be different from each other.

In detail, the total number of subfields included in the first frame in the normal state as shown in (a) is n (SF1 to SFn), and the length of the n-1th subfield (SFn-1) may be d10. have.

On the other hand, when the waveform overflow occurs, as in (b), the number of subfields included in the second frame in which the waveform overflow occurs is less n-1 (SF1 to SFn-1) than in the case of (a). In addition, the length of the n-th subfield may be d20 shorter than d10.

In the case of FIG. 14B, the waveform overflow occurs while the sustain signal is supplied in the sustain period of the n-th subfield SFn-1, thereby supplying a part of the sustain signal and omitting the n-th subfield ( SFn) is omitted.

As such, when the waveform overflow occurs, it may be possible to prevent malfunction and damage of the switching element by reducing the number of subfields while reducing the length of any subfield.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

1 is a view for explaining the configuration of a plasma display device according to an embodiment of the present invention.

2 is a diagram for explaining the structure of a plasma display panel;

FIG. 3 is a diagram for explaining a frame for implementing gradation of an image. FIG.

4 is a diagram for explaining an example of a driving waveform for operating a plasma display device.

5 is a diagram for explaining the driving unit in more detail.

6 to 9 are views for explaining the operation of the drive unit.

10 to 12 are views for explaining in detail the method of reducing the length of the subfield when the waveform overflows.

FIG. 13 is a diagram for describing a method of reducing the number of subfields when a waveform overflows; FIG.

FIG. 14 is a diagram for explaining a method of simultaneously reducing the number of subfields and the length of a subfield when a waveform overflows. FIG.

Claims (9)

A plasma display panel including an electrode; And A driving unit which cuts off the supply of the driving waveform and maintains the voltage of the electrode when the driving waveform supplied to the electrode exceeds one cycle period of the vertical synchronizing signal (Vsync); Plasma display device comprising a. The method of claim 1, And the electrode maintains a voltage at ground level (GND) in a minimum voltage holding period of the vertical synchronization signal. A plasma display panel configured to implement an image in a frame including a plurality of sub-fields; And A driver for varying the number of subfields included in any two frames for the same image data; Plasma display device comprising a. The method of claim 3, wherein Any two frames for the same image data include a first frame and a second frame, The number of subfields included in the second frame is less than the number of subfields included in the first frame, In the second frame, the driving waveform supplied to the electrode of the plasma display panel exceeds one cycle period of the vertical synchronization signal Vsync. In the first frame, the driving waveform supplied to the electrode of the plasma display panel does not exceed one period of the vertical synchronization signal (Vsync). The method of claim 4, wherein And a supply point of the first frame is earlier than a supply point of the second frame, or a supply point of the second frame is earlier than a supply point of the first frame. A plasma display panel configured to implement an image in a frame including a plurality of sub-fields; And A driver configured to different lengths of any one of the subfields included in any two frames of the same image data; Plasma display device comprising a. The method of claim 6, Any two frames for the same image data include a first frame and a second frame, The length of the first subfield among the subfields included in the second frame is shorter than the length of the tenth subfield corresponding to the first subfield of the second frame among the subfields included in the first frame, In the second frame, the driving waveform supplied to the electrode of the plasma display panel exceeds one cycle period of the vertical synchronization signal Vsync. In the first frame, the driving waveform supplied to the electrode of the plasma display panel does not exceed one period of the vertical synchronization signal (Vsync). The method of claim 7, wherein And the first subfield and the tenth subfield have the same weight and arrangement order. The method of claim 7, wherein Wherein the first subfield is a last subfield of a plurality of subfields of the second frame, and the tenth subfield is a last subfield of a plurality of subfields of the first frame.

Images