KR20100065446A - Refresh cycle settlement method of dynamic random access memory and the dynamic random access memory - Google Patents

Abstract

PURPOSE: A refresh cycle deciding method of a dynamic memory device using a monitoring bit and the dynamic memory device are provided to reduce power consumption by adjusting a self refresh cycle depending on whether or not an error occurs in a monitoring bit. CONSTITUTION: An ECC engine(20) selects at least one monitoring bit during a self refresh period. The ECC engine determines whether or not an error is in the selected monitoring bit. A monitoring address storage unit(30) stores the monitoring address of the selected monitoring bit. A refresh cycle determining circuit(40) adjusts a self refresh cycle depending on whether or not the error occurs in the monitoring bit. The monitoring address storage unit comprises a monitoring address register, a sampling flag register, and an error flag register.

Description

Refresh cycle settlement method of dynamic memory device and its dynamic memory access method

The present invention relates to a method for determining a refresh cycle of a dynamic memory device and an operating memory device thereof.

The memory cell of a dynamic memory device is composed of a transistor serving as a switch and a capacitor for storing data. However, leakage current may be generated at the PN junction of the MOS transistor, and the like, and initial data stored in the capacitor may be lost. Therefore, the dynamic memory device requires a refresh operation to recharge the data in the memory cell before the data is destroyed.

Such refresh operations include auto refresh, self refresh, and the like. In particular, self refresh means performing refresh while sequentially changing an internal address in response to the refresh indication signal.

However, the self refresh is repeated according to a cycle determined internally. Such a recharge cycle is called a refresh cycle tREF. The refresh period is determined by the data decay time. The data decay time is not constant according to the PVT (Process, Voltage, Temperature) change.

In addition, since the dynamic memory device performs a refresh operation, standby power consumption is greater than that of static RAM (SRAM) or flash memory. Therefore, a method for minimizing standby power consumption has been devised. The most effective method is to make the refresh period as long as possible.

An object of the present invention is to provide a method of determining a period of a dynamic memory device with reduced power consumption.

Another object of the present invention is to provide a dynamic memory device with reduced power consumption.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the refresh cycle determination method of the dynamic memory device of the present invention for achieving the above technical problem is at least one monitoring bit during the first to nth (where n is a natural number equal to or greater than 1) of the self refresh. Is selected, and detects whether at least one monitoring bit is in error during the n + 1 to mth (where m is a natural number equal to or greater than n + 1) period of the self-refresh, and at least one monitoring bit is in error. And adjusting the m + 1th period of self refresh according to whether or not.

Another aspect of the dynamic memory device of the present invention for achieving the above technical problem is an ECC engine for selecting at least one monitoring bit and detecting whether the selected at least one monitoring bit is error during a self refresh period, at least one selected The monitoring address storage unit for storing the monitoring address of the monitoring bit of the control bit, and adjusts the self-refresh cycle according to whether or not the monitoring bit.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

1 is a block diagram illustrating a dynamic memory device according to an embodiment of the present invention.

Referring to FIG. 1, a dynamic memory device 1 according to an embodiment of the present invention may determine a memory array 10, an error correction code engine (ECC) 20, a monitoring address storage unit 30, and a refresh cycle. Circuit 40.

The memory array 10 includes a plurality of memory cells arranged two-dimensionally (eg, in the form of a matrix). Although only one memory bank is illustrated as an example, the memory array 10 of FIG. 1 may include a plurality of memory banks. The memory cells in the row direction of the memory array 10 are electrically connected to word lines, and the memory cells in the column direction are electrically connected to bit lines (or complementary bit lines).

In addition, the row decoder 12 is disposed corresponding to the memory array 10 and selects a word line of the memory array 10 according to a decoding result of the row address signal. The sense amplifier and write driver 14 reads data stored in a memory cell by amplifying a potential difference between a pair of bit lines and a pair of data lines respectively connected in a read operation, and reads predetermined data in a write operation. The data is transferred through the data line pair and the bit line pair to be stored in the memory cell. The column decoder 16 is disposed corresponding to the memory array 10 and selects a memory cell to be read or written according to the decoding result of the column address signal.

However, the dynamic memory device 1 of the present invention may detect an error generated in data stored in the memory array 10 and correct it.

As described above, when the dynamic memory device 1 does not perform the refresh operation for more than a predetermined time, data stored in the capacitor of the memory cell may be destroyed. Nevertheless, the self refresh period tREF must be increased to reduce standby power consumption. Accordingly, in the present invention, an error detection and correction scheme may be used during the self refresh period tREF, thereby reducing standby power consumption and not damaging data stored in the capacitor of the memory cell. That is, the standby power consumption is reduced by increasing the self refresh period tREF, and data corruption that may occur as the self refresh period tREF is increased is restored using an error detection and correction scheme.

On the other hand, extra information about the stored data is needed to detect and correct errors. That is, the memory array 10 stores a plurality of data bits and error correction code (ECC) bits corresponding to redundant information about the data bits. For example, in the memory array 10, one bit of ECC bit may be added and stored for every eight bit of data.

These ECC bits are not limited to a particular type of code. For example, the ECC bits may be Hamming code, Huffman code, parity bit, turbo code, cyclic code, low density parity check code (low-density). It may be generated using any form of coding such as parity-check code, Reed-Muller code, or Reed-Solomon error correction code.

Therefore, in one embodiment of the present invention, the ECC engine 20 generates the ECC bits corresponding to the data bits using the data bits stored in the memory array 10 before the memory array 10 performs the self refresh operation. The ECC bit is stored in a predetermined area in the memory array 10. In addition, the ECC engine 20 detects whether an error has occurred in the data bit using the data bit and the ECC bit corresponding to the data bit during the self refresh operation. In addition, the ECC engine 20 corrects an error generated in the data bit during the self refresh operation and / or at the end of the self refresh operation.

Meanwhile, the dynamic memory device 1 of the present invention may adjust the self refresh cycle by using data bits and ECC bits stored in the memory array 10 during the self refresh mode. In particular, instead of detecting whether an error occurs in all data bits stored in the memory array 10, whether or not an error occurs in only a part of the data bits is detected and the self refresh period is adjusted according to the result. This is because the power consumption is large when detecting whether an error has occurred in all data bits. Hereinafter, the data bits and ECC bits selected in the memory array 10 are referred to as monitoring bits.

The monitoring bit is selected through a test in advance, and the address of the selected monitoring bit is stored in the monitoring address storage unit 30. The monitoring bit may be selected in the tail-bits region in the pause refresh characteristic diagram (see FIG. 6). In FIG. 6, the x-axis denotes a pause time and the y-axis denotes a normalized cumulative error bit number. The tail bit area is an area where an error occurs before the predicted pause time (see reference numeral a (dotted line)). That is, compared to the bits of the normal bit region, the bits of the tail bit region may easily generate a leakage current according to a process voltage temperature (PVT) change. Therefore, by monitoring only the bits of the tail bit region, it is possible to determine the characteristics of all the bits.

In addition, a plurality of selected monitoring bits may be selected within the tail bit region. For example, the first monitoring bit may have an error, and the second monitoring bit may have a self refresh period tREF to prevent an error. I can regulate it. When no separate monitoring is performed in the tail bit region as in the present invention, the bits in the tail bit region tend to be errored, so that the self refresh period tREF is sufficient to prevent all the bits in the tail bit region from being errored. It should be loud. However, in the present invention, a predetermined number of data bits may be modified using ECC bits within a range that does not consume much power, thereby increasing the self refresh period tREF.

In particular, it may include the most leaky bit (bit (0)) and the least leaky bit (bit (n)) in the tail bit region. For example, the bit most prone to leak bit (0) may cause an error, and the least bit bit (n) may adjust the self refresh period tREF so that no error occurs. A detailed method of adjusting the self refresh period tREF will be described later with reference to FIGS. 4 and 5.

The dynamic memory device 1 according to the embodiment of the present invention includes a monitoring address storage unit 30 for storing an address MA of such monitoring bits. The monitoring address storage unit 30 may be stored in a nonvolatile type, and may store an address using, for example, a fuse.

In addition, the dynamic memory device 1 includes a refresh cycle determination circuit 40 to adjust the self refresh cycle tREF by using an error of the monitoring bit detected by the ECC engine 20.

Specifically, the operation of the refresh period determination circuit 40 will be described. The refresh period determination circuit 40 may be enabled by receiving the refresh instruction signal PRFH from the refresh entry detection circuit 50. That is, the refresh entry detection circuit 50 detects the entry into the self refresh mode and generates a refresh indication signal PRFH. The self-refresh entry is sensed through a command specified by a combination of a plurality of control signals (/ CS, / CAS, / RAS, / WE, CKE, CLK), and a high level refresh entrance indication signal (PRFH) is provided. Specifically, for example, the chip select signal / CS, the column address strobe signal / CAS, the row address strobe signal / RAS, and the clock enable signal CKE are low level, and the write enable signal / When WE) is at the high level, the refresh instruction signal PRFH is at the high level. On the other hand, when the clock enable signal CKE is at the high level, the refresh indication signal PRFH is at the low level, indicating that the self refresh is terminated.

The refresh period determination circuit 40 causes the ECC engine 20 to generate ECC bits corresponding to the data bits using the data bits in the memory array 10.

The refresh period determination circuit 40 sets an initial self refresh period tREF and provides a corresponding refresh period determination signal CRFH to the internal address generator 60. The internal address generator 60 generates a pulse every certain operating period in the self refresh operation, and generates a counting address that sequentially increases in response to the pulse. The combination of counting addresses sequentially changes the designated row addresses RA1 to RAn. Here, the operation period may be changed in response to the refresh period determination signal CRFH.

In addition, the refresh cycle determination circuit 40 provides the monitoring address storage unit 30 with the timing signal TS every predetermined time [Delta] t. The monitoring address storage unit 30 provides the monitoring address MA to the row decoder 12 and the column decoder 16 in response to the timing signal TS. The sense amplifier / write driver 14 provides a monitoring bit corresponding to the monitoring address MA to the ECC engine 20, and the ECC engine 20 detects whether an error of the monitoring bit occurs.

Here, the refresh cycle determination circuit 40 provides the refresh cycle determination signal CRFH adjusted according to the detection result of the ECC engine 20 to the internal address generator 60 to adjust the self refresh cycle tREF. . Since the timing signal TS is provided to the monitoring address storage unit 30 at each predetermined time? T, the self refresh period tREF is adjusted every predetermined time? T.

FIG. 2 is a block diagram illustrating the refresh cycle determination circuit and the ECC engine of FIG. 1.

Referring to FIG. 2, the refresh cycle determination circuit 40 includes an ECC_operator 42 and a timer 44, and the ECC engine 20 includes an ECC_encode / decoder 22 and an ECC_corrector ( 24).

The ECC_operator 42 receives the refresh indication signal PRFH so that the ECC_encode / decoder 22 generates the ECC bits corresponding to the data bits by using the data bits in the memory array 10. . The sense amplifier / write driver 14 writes the generated ECC bits into the memory array 10.

Subsequently, the ECC_operator 42 sets the initial self refresh period tREF, and provides the internal address generator 60 with the corresponding refresh period determination signal CRFH.

In addition, the ECC_operator 42 provides the timer 44 with the pre-timing signal PTS. The timer 44 provides the timing signal TS to the monitoring address storage unit 30 every predetermined time DELTA t in response to the pre-timing signal TS. Here, the predetermined time Δt is not a predetermined value and may vary depending on a temperature or an application.

Therefore, the monitoring bits in the memory array 10 are read through the sense amplifier / write driver 14 every predetermined time [Delta] t. The ECC_encoding / decoding section 22 detects whether an error has occurred in the read monitoring bit. The ECC_operator 42 analyzes the detection result of the ECC_encode / decoder 22 and provides the internal address generator 60 with the refresh period determination signal CRFH, which adjusts the self refresh period tREF. .

On the other hand, upon detecting the self refresh exit, the ECC_operation unit 42 causes the ECC engine 20 to correct the error generated in the memory array 10. Therefore, the ECC_encoding / decoding section 22 reads data bits and ECC bits in the memory array 10 to detect whether there is an error. The ECC_corrector 24 modifies the data bits using the ECC bits. The sense amplifier / write driver 14 then rewrites the modified data bits.

3 is a circuit diagram illustrating a dynamic memory device according to another embodiment of the present invention. The same reference numerals are used for constituent elements that are substantially the same as in FIG. 1, and a detailed description of the corresponding constituent elements will be omitted.

Referring to FIG. 3, the dynamic memory device 2 according to another embodiment of the present invention differs from the embodiment in that ROM (Read Only Memory) is used as the monitoring address storage unit 32. Accordingly, the refresh period determination circuit 40 provides the timing signal TS to the monitoring address storage unit 30 through the predetermined control pin 71, and the monitoring address storage unit 30 supplies the predetermined address pin 72. The monitoring address MA is provided to the row decoder 12 and the column decoder 16 by way of example.

4 is a flowchart illustrating a method of determining a refresh period of a dynamic memory device according to an embodiment of the present invention. 4 illustrates an example of two selected monitoring bits.

1 and 4, first, the monitoring bit is selected, and the monitoring address MA is stored in the monitoring address storage 30 (S105). In detail, the monitoring bit may be selected in a tail bit region in a pause refresh characteristic diagram. In one embodiment of the present invention, the selected monitoring bit includes the most leaky bit (bit (0)) and the least leaky bit (bit (1)) in the tail bit region. ), But is not limited thereto.

Subsequently, it is detected whether to enter the self refresh mode (S110). Specifically, the refresh entry detection circuit 50 detects the entry into the self refresh mode through a command specified by a combination of a plurality of control signals (/ CS, / CAS, / RAS, / WE, CKE, CLK), The refresh instruction signal PRFH is provided to the refresh period determination circuit 40.

Subsequently, when entering the self refresh mode, an error correction code (ECC) bit is generated (S120). Specifically, the refresh period determination circuit 40 causes the ECC engine 20 to generate ECC bits corresponding to the data bits by using the data bits in the memory array 10.

Next, an initial self refresh period tREF is set (S130). In detail, the refresh period determination circuit 40 sets an initial self refresh period tREF and provides the internal address generator 60 with a refresh period determination signal CRFH corresponding thereto. The internal address generator 60 sequentially changes the row addresses RA1 to RAn at predetermined operation cycles, thereby performing self refresh.

Subsequently, whether the monitoring bit bit 1 is normal is examined (S140). In detail, when an error occurs in bit 1, the self refresh period tREF is reduced (S142). Since bit (1) is an error even though it is a bit that does not leak relatively compared to bit (0), the error occurrence is reduced by reducing the self refresh period tREF.

After reducing the self-refresh cycle tREF, it is again checked whether the monitoring bit bit 1 is normal, and if it is normal, it is examined whether the monitoring bit bit 0 is normal (S150). In detail, when bit (0) is normal, the self refresh period tREF is increased (S154). bit (0) is normal even though it is a bit more likely to leak compared to bit (1) (that is, since bit (0) and bit (1) are all normal), the self-refresh cycle tREF is too short. Since it is determined, the self refresh period tREF is increased.

If an error occurs in the monitoring bit bit (0), the self refresh period tREF is fixed (S156). That is, the self refresh period tREF is determined as tREF (0) <tREF <tREF (1). Here, tREF (1) and tREF (0) mean a self refresh period in which an error occurs in bit (1) and bit (0), respectively. When the self refresh period tREF is determined, the refresh period determination circuit 40 provides the refresh decision signal CRFH to the internal address generator 60 to perform a self refresh operation in accordance with the determined self refresh period tREF.

Next, the predetermined time (Δt) is waited (S160). Here, the predetermined time Δt is not a predetermined value and may vary depending on a temperature or an application.

Next, it is examined whether the self refresh mode is exited (S170). Specifically, for example, when the clock enable signal CKE is at the high level, the refresh indication signal PRFH is at the low level, indicating that self refresh is terminated.

Next, the data is corrected before exiting the self refresh mode (S180). Specifically, the ECC engine 20 modifies the data bits using the ECC bits in the memory array 10.

As described above, the self refresh period tREF may be actively changed in response to the PVT change by adjusting the self refresh period tREF by examining whether a plurality of predetermined monitoring bits have an error every predetermined time Δt. In addition, since the self refresh period tREF can be taken as long as possible, standby power consumption of the dynamic memory device 1 is minimized.

5 is a flowchart illustrating a method of determining a refresh period of a dynamic memory device according to another exemplary embodiment of the present invention. The same reference numerals are used for the components substantially the same as in FIG. 4, and detailed descriptions of the components will be omitted.

1 and 5, a method of determining a refresh period of a dynamic memory device according to another embodiment of the present invention will be described in the case where a plurality of selected monitoring bits are provided.

First, the monitoring bit is selected and the monitoring address MA is stored in the monitoring address storage unit 30 (S105). Here, the plurality of monitoring bits are selected in the tail bit area, and the selected plurality of monitoring bits are in the order of easy leakage. , bit (n).

Subsequently, it is detected whether to enter the self refresh mode (S110), and generates an ECC bit (S120). The initial self refresh period tREF is set (S130).

Subsequently, whether the monitoring bit bit (n) is normal is examined (S240). If an error occurs in bit (n), the self refresh period tREF is reduced (S242).

If bit (n) is normal, i = n-1 is substituted (S244).

Subsequently, whether bit (i) is normal (that is, whether bit (n-1) is normal) is examined (S250). If bit (n-1) is normal, it is checked whether i = 0 (S251). That is, it is determined whether there are any more bits to monitor. If the bit to be monitored remains i = i-1 (S252), it is checked whether bit (i) is normal (that is, bit (n-2) is normal) (S250).

When reviewed in this manner, all monitoring bits bit (0), bit (1),... If the bit (n) is normal, the self refresh period tREF is increased (S254).

On the other hand, while examining in this manner, if an error occurs in bit (i), the self refresh period (tREF) is fixed (S256). That is, the self refresh period tREF is determined as tREF (i) <tREF <tREF (i + 1). Here, tREF (i + 1) and tREF (i) denote self-refresh cycles such that an error occurs in bit (i + 1) and bit (i), respectively.

Next, the predetermined time (Δt) is waited (S160). It is examined whether the self refresh mode is exited (S170). The data is corrected before exiting the self refresh mode (S180).

In another embodiment of the present invention, it is determined whether an error occurs in the plurality of monitoring bits selected in the tail bit area, but whether or not an error occurs in the order of not leaking is not limited thereto. That is, it is possible to determine whether an error occurs in the order of easy leakage, and it is possible to determine whether an error occurs by selecting randomly. In addition, whether or not an error occurs may be determined using an order of not leaking and an order of leaking easily.

FIG. 7 is a diagram for describing a refresh period adjusting method of a dynamic memory device according to another exemplary embodiment.

Referring to FIG. 7, in another embodiment of the present invention, selecting at least one monitoring bit is made during the self refresh period.

On the other hand, in an embodiment of the present invention (see FIG. 1), the selection of the monitoring bit is selected through a test in advance, and the address of the selected monitoring bit is a nonvolatile type monitoring address storage unit. 30 is stored.

In another embodiment of the present invention, upon entering the self refresh period, first, at least one monitoring bit is selected during the first few periods of the self refresh (eg, SR1 to SR4) (step I). Step I is called Auto Sampling Mode (ASM). During one period, all word lines of the memory array perform self refresh sequentially.

Specifically, during the first period SR1 of the self refresh, the data bit stored in the memory array and the ECC bit corresponding thereto are examined to determine whether the data bit is in error. For example, data bits read from the memory array are corrected using ECC bits. If the corrected data bits are the same as the pre-corrected (ie, originally read) data bits, then the read data bits may be normal. On the other hand, if the corrected data bit is different from the data bit before correction, the read data bit may be determined as an error. As will be described later, these error data bits may be modified through a writeback operation. The length of the first period SR1 may be the shortest (that is, T0 in FIG. 7).

If an error of the data bit does not occur, the second period SR2 is increased to T1. Again, during the second period SR2, the data bits stored in the memory array and the corresponding ECC bits are examined for error of the data bits. Since the second period SR2 of the self refresh is increased than the first period SR1, the possibility of an error in the data bit is increased.

The length of the period of self refresh is increased until an error of a predetermined data bit occurs. For example, the third period SR3 increases from T1 to T2 and the fourth period SR4 increases from T2 to T3. In FIG. 7, an error occurs in the fourth period SR4.

When an error of a predetermined data bit occurs, the data bit in which the error occurs and the ECC bit corresponding thereto are defined as monitoring bits, and the address of the monitoring bit is stored in the monitoring address storage unit 330 of FIG. 8.

Here, it is not necessary to define all the data bits having an error in the memory array and the corresponding ECC bits as the monitoring bits in the fourth period SR4. That is, only a part can be defined as a monitoring bit. For example, only a few bits of an errored data may be defined as monitoring bits. This is because, first, an errored data bit is likely to correspond to a bad data retention characteristic in the dynamic memory device.

In FIG. 7, the monitoring bit is not selected during the first to third cycles SR1 to SR3, and the length of the cycle is continuously increased, but the present invention is not limited thereto. For example, when detecting a data bit in which an error occurs immediately in the first period SR1, the monitoring bit may be selected by performing only the first period SR1.

Subsequently, in the fifth to tenth cycles SR5 to SR10 of the self refresh performed after the I stage (ASM stage), only the monitoring bit selected during the self refresh is detected (step II).

Specifically, instead of detecting whether an error occurs in all data bits stored in the memory array, whether or not an error occurs in only a part of the data bits is detected and the self refresh period is adjusted according to the result. This is because the power consumption is large when detecting whether an error has occurred in all data bits.

Subsequently, the length of the eleventh period SR11 of the self refresh may be adjusted according to whether the selected monitoring bit is in error (step III).

For example, if an error occurs in the monitoring bit continuously during the fifth to tenth periods SR5 to SR10, it is determined that the self refresh period is not correct. Therefore, the length of the eleventh period SR11 is reduced. In FIG. 7, the eleventh period SR11 is reduced to T2.

Although not illustrated, on the contrary, if no error occurs in the monitoring bit continuously during the fifth to tenth periods SR5 to SR10, the self refresh period may be further increased. Therefore, the length of the eleventh period SR11 is further increased.

Meanwhile, although FIG. 7 examines whether an error continues to occur in the monitoring bit for six cycles SR5 to SR10, the present invention is not limited thereto. For example, it may be possible to examine only one period, or to check if the error continues to occur in the monitoring bit for seven or more periods.

As described above, selecting at least one monitoring bit during the first through nth cycles, where n is a natural number greater than or equal to 1, is as follows.

First, when n is a natural number greater than 2, the data bit stored in the memory array and the corresponding ECC bit are stored during a period of self-refresh a (where a is a natural number greater than or equal to 1 and less than n). Check the data bit for errors.

At this time, if an error of the data bit does not occur, during the a period of the self refresh, the data bit stored in the memory array and the ECC bit corresponding thereto are examined to determine whether the data bit is in error. The a + 1 period is increased than the a period of the self refresh. Meanwhile, when an error of the data bit occurs, the data bit in which the error occurs and the ECC bit corresponding thereto are defined as the monitoring bit, and the address of the monitoring bit is stored in the monitoring address storage.

8 is a block diagram illustrating a dynamic memory device according to another embodiment of the present invention. FIG. 8 is an example specifically implementing the refresh period determination method described with reference to FIG. 7. FIG. 9 is a diagram for describing the monitoring address storage of FIG. 8, and FIG. 10 is a diagram for explaining the refresh period determining unit of FIG. 8. The same reference numerals are used for constituent elements that are substantially the same as in FIG. 1, and a detailed description of the corresponding constituent elements will be omitted.

Referring to FIG. 8, the dynamic memory device 3 according to another embodiment of the present invention may include a memory array 10, an error correction code engine (ECC) 320, a monitoring address storage unit 330, and a refresh cycle. The decision circuit 340 is included.

The ECC engine 320 selects at least one monitoring bit (as described with reference to FIG. 7) during the self refresh period, and detects whether the selected at least one monitoring bit is in error.

Specifically, the ECC engine 320 selects at least one monitoring bit during the first to nth cycles of self refresh (where n is a natural number equal to or greater than 1), and the n + 1 to mth times of the self refresh. Where m is a natural number equal to or greater than n + 1, at least one monitoring bit may be detected.

When selecting at least one monitoring bit, if an error of the data bit does not occur, the data bit is stored using the data bit stored in the memory array 10 and the corresponding ECC bit during the a + 1 period of self refresh. Examine whether or not the error, but the a + 1 period of the self refresh is increased than the a period of the self refresh. Meanwhile, when an error of the data bit occurs, the data bit in which the error occurs and the ECC bit corresponding thereto are defined as the monitoring bit, and the address of the monitoring bit is monitored address storage 330 (that is, the monitoring address register 332). Save to)).

The monitoring address storage unit 330 stores the address of at least one selected monitoring bit.

For example, the monitoring address storage unit 330 may include a monitoring address register 332, a sampling flag register 334, and an error flag register 336.

The plurality of monitoring address registers 332 stores a plurality of monitoring addresses corresponding to each of the plurality of monitoring bits.

The plurality of sampling flag registers 334 correspond to each monitoring address register 332 and store a sampling flag indicating whether a monitoring address is stored in each monitoring address register 332. For example, when the monitoring address is stored in the monitoring address register 332, the sampling flag may be 1, otherwise it may be 0.

The plurality of error flag registers 336 correspond to each monitoring address register 332 and store an error flag indicating whether a monitoring bit corresponding to a monitoring address stored in each monitoring address register 332 is an error. do. For example, during the refresh period (eg, SR5), if the monitoring bit corresponding to the stored monitoring address is an error, the error flag may be 1, otherwise it may be 0.

Here, although each of the monitoring address register 332, the sampling flag register 334, and the error flag register 336 is illustrated in FIG. 9, the present invention is not limited thereto. As needed, ten or more may be sufficient and ten or less may be sufficient. The monitoring address register 332, the sampling flag register 334, and the error flag register 336 are illustrated as 8 bits, 1 bit, and 1 bit, but the present invention is not limited thereto.

In FIG. 1, the monitoring address storage unit 30 may be of a nonvolatile type since the monitoring address selected through a test is stored in the monitoring address storage unit 30. In contrast, in FIG. 8, since the monitoring address is selected and the selected monitoring address is stored every time the self refresh is performed (that is, the ASM step), the monitoring address storage unit 330 does not need to be limited to a nonvolatile form. That is, a volatile type is also possible.

The refresh cycle determination circuit 340 adjusts the self refresh cycle according to whether the monitoring bit is in error.

Specifically, the refresh period determining circuit 340 may perform self-refresh according to an error of the at least one monitoring bit detected during the n + 1 to mth (where m is a natural number equal to or greater than n + 1) period. Adjusting the m + 1 period of.

Here, referring to FIG. 10, the refresh cycle determination circuit 340 may include the SR latch 341, the AND gates 342, 344, 345, 347, 348, and 349, the error counter 343, and the delay unit 346. Can be configured.

The signal is explained as follows.

The SR_END signal is a signal indicating the end of self refresh, and the SRP_END signal is a signal indicating the end of the self refresh cycle. The SRP_END signal may be, for example, a signal provided by the internal address generator 360.

The ER_SUM signal is an OR combination signal of error flags stored in the error flag register 336. That is, when only one of the error flags is 1, the ER_SUM signal is 1. The ER signal is generated every time the ECC engine 320 finds an error. If an error occurs, the ER signal becomes 1.

The ADDR_MATCH signal is a signal indicating whether an address currently performing self refresh and an address stored in the monitoring address register 332 match each other. In other words, ADDR_MATCH is 1 when they match each other.

The ASM signal is a signal indicating that the ASM operation is completed (ie, storing the monitoring address in the monitoring address register 332). 1 when the ASM operation completes.

The SRP_DCM signal is a signal indicating a decrease in the self refresh period, and the SRP_ICM signal is a signal indicating an increase in the self refresh period. The SRP_DCM signal and the SRP_ICM signal are transmitted to the internal address generator 60 to adjust the self refresh period.

The WRITE signal is a signal indicating write back. That is, it is a signal which instructs to correct the data bit which an error generate | occur | produced using ECC bit, and to rewrite the corrected data. The REFRESH signal is a signal indicating only self refresh (without writeback operation), and the READ signal is a signal instructing data read in order for the ECC engine 320 to determine whether the monitoring data is in error.

An operation of increasing or decreasing the cycle of self refresh is as follows.

When the self-refresh cycle ends and the SRP_END signal becomes 1 and at least one error occurs during the self-refresh cycle, the ER_SUM signal becomes 1, and the output of the AND gate 342 becomes 1. The error counter 343 counts the number of times that the output of the AND gate 342 becomes 1. The error counter 343 enables the SRP_DCM signal when the number of counts exceeds a specific value. For example, if an error occurs for six periods (as illustrated in FIG. 7), the SRP_DCM signal may be enabled. Since the SRP_DCM signal is enabled, the self refresh period is reduced.

On the other hand, when the self-refresh cycle ends and the SRP_END signal becomes 1, and no error occurs during the self-refresh cycle, the ER_SUM signal becomes 0, and the SRP_ICM signal is enabled. That is, since the SRP_ICM signal is enabled, the self refresh period is increased.

The following describes how to control the operation of self refresh.

When the address currently performing self refresh and the address stored in the monitoring address register 332 match with each other, the ADDR_MATCH signal becomes 1. In this case, the READ signal is enabled. Therefore, the data of the address which is currently performing self refresh is read, and the ECC engine 320 determines whether there is an error.

If the address currently performing the self refresh and the address stored in the monitoring address register 332 do not match, the ADDR_MATCH signal is zero. In this case, the REFRESH signal is enabled. Therefore, the ECC engine 320 does not determine whether an error exists. It simply refreshes the data at the address that is performing the self refresh.

When the ER signal is 1, an error occurs in the data bit corresponding to the address where the self refresh is being performed. Accordingly, the WRITE signal is enabled after a predetermined time delay by the delay unit 346. Thus, the modified data is written back to the data bit in which the error occurred.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 is a block diagram illustrating a dynamic memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the refresh cycle determination circuit and the ECC engine of FIG. 1.

3 is a circuit diagram illustrating a dynamic memory device according to another embodiment of the present invention.

4 is a flowchart illustrating a method of determining a refresh period of a dynamic memory device according to an embodiment of the present invention.

5 is a flowchart illustrating a method of determining a refresh period of a dynamic memory device according to another exemplary embodiment of the present invention.

6 is a pose refresh characteristic diagram showing the normalized cumulative error bit number with respect to the pause time.

FIG. 7 is a diagram for describing a refresh period adjusting method of a dynamic memory device according to another exemplary embodiment.

8 is a block diagram illustrating a dynamic memory device according to another embodiment of the present invention.

FIG. 9 is a diagram for describing a monitoring address storage unit of FIG. 8.

FIG. 10 is a diagram for describing the refresh period determiner of FIG. 8.

(Explanation of symbols for the main parts of the drawing)

1-3: Dynamic Memory Device 10: Memory Array

12: Low Decoder 14: Sense Amplifier / Write Driver

16: column decoder 20, 320: ECC engine

30, 330: monitoring address storage unit

40, 340: refresh cycle determination circuit

50: refresh ingress detection circuit

60, 360: Internal address generator

Claims (11)

Selecting at least one monitoring bit during the first to nth cycles of self refresh, wherein n is a natural number greater than or equal to 1, and Detects whether the at least one monitoring bit is in error during the n + 1 to mth periods of the self refresh, wherein m is a natural number equal to or greater than n + 1, and And adjusting the m + 1th period of the self refresh according to whether the at least one monitoring bit is in error. The compound of claim 1, wherein n is a natural number greater than 2 Selecting the monitoring bit, During a period of self refresh (a is a natural number greater than or equal to 1 and less than n), the data bits stored in the memory array and the ECC bits corresponding to the data bits are examined for errors. , If an error of the data bit does not occur, during the a + 1 period of self refresh, the data bit stored in the memory array and the ECC bit corresponding to the data bit are examined for error of the data bit. The method of determining a refresh cycle of a dynamic memory device in which the a + 1th cycle of refresh is increased from the ath cycle of the self refresh. The method of claim 2, wherein selecting the monitoring bit, If an error of the data bit is generated, further comprising defining the data bit in which the error and the corresponding ECC bit as a monitoring bit, and storing the address of the monitoring bit in a monitoring address storage unit. How to determine the refresh cycle. The method of claim 1, And adjusting the self refresh period reduces the self refresh period when at least some of the at least one monitoring bit is an error. The method of claim 1, The adjusting of the self refresh period may increase the self refresh period when the at least one monitoring bit is normal. An ECC engine selecting at least one monitoring bit and detecting whether the selected at least one monitoring bit is in error during a self refresh period; A monitoring address storage unit which stores a monitoring address of the at least one selected monitoring bit; And And a refresh cycle determination circuit for adjusting a self refresh cycle according to whether the monitoring bit is in error. The method of claim 6, The ECC engine selects at least one monitoring bit during the first through nth cycles of self refresh (where n is a natural number greater than or equal to 1), and the n + 1 through mth stages of self refresh (where detects whether the at least one monitoring bit has an error during a natural number equal to or greater than n + 1), and The refresh period determination circuit may perform the m + 1th self refresh according to an error of the at least one monitoring bit detected during the n + 1 to mth periods, wherein m is a natural number equal to or greater than n + 1. Dynamic memory device comprising adjusting the period. 8. The compound of claim 7, wherein n is a natural number greater than two, The ECC engine selecting the monitoring bit, During a period of self refresh (a is a natural number greater than or equal to 1 and less than n), the data bits stored in the memory array and the ECC bits corresponding to the data bits are examined for errors. , If an error of the data bit does not occur, during the a + 1 period of self refresh, the data bit stored in the memory array and the ECC bit corresponding to the data bit are examined for error of the data bit. And a a + 1 period of refresh is increased than a a period of self refresh. The method of claim 7, wherein And wherein the refresh period determination circuit reduces the self refresh period if at least some of the at least one monitoring bit is an error and increases the self refresh period if the at least one monitoring bit is normal. The method of claim 6, wherein the monitoring address storage unit A plurality of monitoring address registers for storing the plurality of monitoring addresses; A sampling flag register corresponding to each of the monitoring address registers and storing a sampling flag indicating whether the monitoring address is stored in each of the monitoring address registers; And an error flag register corresponding to each of the monitoring address registers and storing an error flag indicating whether a monitoring bit corresponding to the monitoring address stored in each monitoring address register is an error. The method of claim 6, And the monitoring address storage unit is of volatile type.

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