KR20100064005A - Method for erasing a flash memory device - Google Patents

Method for erasing a flash memory device Download PDF

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Publication number
KR20100064005A
KR20100064005A KR1020080122402A KR20080122402A KR20100064005A KR 20100064005 A KR20100064005 A KR 20100064005A KR 1020080122402 A KR1020080122402 A KR 1020080122402A KR 20080122402 A KR20080122402 A KR 20080122402A KR 20100064005 A KR20100064005 A KR 20100064005A
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KR
South Korea
Prior art keywords
erase
voltage
memory cell
program
memory cells
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KR1020080122402A
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Korean (ko)
Inventor
노금환
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주식회사 하이닉스반도체
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Priority to KR1020080122402A priority Critical patent/KR20100064005A/en
Publication of KR20100064005A publication Critical patent/KR20100064005A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

The present invention sets the erase verify voltage low according to the cycling number. Therefore, even if the threshold voltage fluctuation of the memory cell during the soft program is much higher than the erase verify voltage in proportion to the number of cycles, in the present invention, the threshold voltage after the soft program increases the probability of maintaining the erase state.

Description

Method for erasing a flash memory device

The present invention relates to a method of erasing a flash memory device, and more particularly, to a method of erasing a flash memory device capable of improving a phenomenon in which an erase cell and a program fault are caused by an increase in a threshold voltage of an erase cell as the number of cycling increases. will be.

Flash memory devices include a plurality of string structures. The string structure includes a drain select transistor, a source select transistor, a plurality of memory cells connected in series between the drain select transistor and the source select transistor. Memory cells of a string structure arranged side by side are connected through a word line, side by side source select transistors are connected through a source select line, and side by side drain select transistors are connected through a drain select line. Here, the drain select transistor selectively connects the memory cells of the string structure and the bit line. In addition, the source select transistor selectively connects the memory cells of the string structure and the common source line connected to the ground terminal.

In the erase process of the flash memory device as described above, the threshold voltage of the erased cell increases due to various factors.

FIG. 1 is a diagram for explaining a problem of increasing a threshold voltage of a conventionally erased cell.

The erasing of the flash memory device is performed in block units in which a plurality of cell strings connected to a plurality of bit lines are connected in parallel to a common source line. For the erase operation, first, a source select line and a drain select line are floated, a voltage of 0 V is applied to all word lines included in a block unit, and then a high voltage is applied to a well provided in a semiconductor substrate. As a result, data of all memory cells of the corresponding block is erased, and the threshold voltage of the cell drops below 0V. In this case, excessively erased cells may occur according to characteristics of the memory cells. Excessively erased cells are distributed in the A1 state and have a threshold voltage that is excessively lower than a desired erase threshold voltage, and thus may not be properly programmed in a subsequent program operation.

Therefore, a soft program is implemented to correct threshold voltages of excessively erased cells. The soft program is executed by repeatedly performing the program and the verifying operation. Each time the program is repeated, the soft program voltage is increased by a constant step voltage, and it is verified each time that the soft program is completed when programmed by the increased program voltage. This process is called SOC (Soft program On Chip). After SOC, the excessively erased cells are distributed from the A1 state to the A2 state, and the threshold voltage thereof is adjusted near the erase verify voltage Vev.

Meanwhile, in executing a program during a soft program operation, programs are sequentially performed with a specific direction. That is, the soft program is implemented in units of pages composed of memory cells connected to the same word line, and is sequentially executed in units of pages with a specific direction. As a result, the BPD (Back Pattern Dependency) effect, the floating gate coupling, and the program disturb occur, and the threshold voltage of the erased cell excessively rises to the A3 state. As a result, the threshold voltage margin of the erase cell decreases from D1 to D2. In particular, after cycling between the erase and the program, the erase voltage rises more significantly in the erase cell, and the threshold voltage of the erase cell increases to 0 V or more, causing a failure to be read into the programmed cell. In addition, the incorrectly read cells are programmed to the wrong level during LSB and MSB program operation, causing defects.

The present invention provides a method of erasing a flash memory device capable of improving a phenomenon in which the threshold voltage of an erase cell increases as the number of cycling increases, thereby causing an erasure failure and a program failure.

A method of erasing a flash memory device according to a first exemplary embodiment of the present invention accumulates a selected memory cell block among memory cell blocks formed on a bulk of a semiconductor substrate and including a plurality of memory cell strings connected in parallel to a common source line. Counting the number of programmed / erase operations, determining an erase verify voltage according to the accumulated number of program / erase operations, an erase step of applying an erase voltage to a selected memory cell block, and an erase verify voltage and the selected memory cell. An erase verification step of comparing the threshold voltages of the memory cells forming the blocks may be included.

In the determining of the erase verify voltage according to the first embodiment, the erase verify voltage is set lower as the accumulated program / erase operation count increases.

In the erase verifying step of the first embodiment, the voltage applied to the common source line and the bulk increases as the accumulated program / erase operation count increases.

In the erase verification step of the first embodiment, the sensing level of the page buffer connected to the selected memory cell block increases as the accumulated program / erase operation count increases.

If the threshold voltages of the memory cells are higher than the erase verify voltage in the erase verify step of the first embodiment, the erase voltage is increased to repeatedly perform the erase operation.

A method of erasing a flash memory device according to a second embodiment of the present invention erases a selected memory cell block among memory cell blocks formed on a bulk of a semiconductor substrate and including a plurality of memory cell strings connected in parallel to a common source line. An erase step of applying a voltage, an erase verify step of comparing the erase verify voltage with threshold voltages of the memory cells constituting the selected memory cell block, and when the threshold voltage of the memory cells is higher than the erase verify voltage, the erase voltage is increased and the erase verify voltage is increased. By lowering the erase step and the erase verification step are repeated.

In the second embodiment, when the erase verifying step is repeated by lowering the erase verifying voltage, the voltage applied to the common source line and the bulk increases.

In the second embodiment, when the erase verifying step is repeated by lowering the erase verifying voltage, the sensing level of the page buffer connected to the selected memory cell block increases.

If the threshold voltages of the memory cells are lower than the erase verify voltage in the erase verify step of the first and second embodiments, after the erase verify step, a soft program step of applying a soft program voltage to the memory cells, and erase the threshold voltages of the memory cells. Further soft program verification steps are performed to compare with the verify voltage.

In the soft program verifying step of the first and second embodiments, if the threshold voltage of the memory cells is lower than the erase verify voltage, the soft program voltage is increased to repeat the soft program operation.

If the threshold voltages of the memory cells are higher than the erase verify voltage in the soft program verifying step of the first embodiment, the number of program / erase operations is accumulated and stored.

The present invention sets the erase verify voltage low according to the cycling number. Therefore, even if the threshold voltage fluctuation of the memory cell during the soft program is much higher than the erase verify voltage in proportion to the number of cycles, in the present invention, the threshold voltage after the soft program increases the probability of maintaining the erase state. As a result, it has the following effects.

First, according to the present invention, since the erase verification voltage is lowered according to the number of cycling, the memory cell can maintain the erased state after the erase is completed even if cycling is repeated, thereby improving cycling characteristics of the flash memory device.

Second, the present invention can secure a read margin for an erase cell of a flash memory device.

Third, the present invention can improve a phenomenon in which an erase failure occurs during soft programming of an erase cell of a flash memory device. Accordingly, the present invention can improve the phenomenon that the erase cell is programmed to the wrong level in a subsequent program operation.

Fourth, the present invention can improve the yield of the flash memory device by reducing the erase failure rate and program failure rate of the flash memory device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 and 3 are diagrams for describing a method of erasing a flash memory device according to a first embodiment of the present invention. 2 is a diagram illustrating a flash memory device according to a first embodiment of the present invention, and FIG. 3 is a flowchart illustrating a method of erasing the flash memory device according to the first embodiment of the present invention.

Referring to FIG. 2, a flash memory device according to a first embodiment of the present invention includes a controller 240, a voltage generator 250, and a plurality of memory cell blocks 210.

Each memory cell block 210 includes a main string structure 220 and a flag string structure 230. The main string structure 220 includes a plurality of memory cells MC0 ... MCn− connected in series between the drain select transistor DST, the source select transistor SST, the drain select transistor DST, and the source select transistor SST. 1, MCn). The flag string structure 230 includes a plurality of flag cells FC0 ... FCn- connected in series between the drain select transistor DST, the source select transistor SST, the drain select transistor DST, and the source select transistor SST. 1, FCn). Memory cells of the main string structure 220 arranged side by side and memory cells of the flag string structure 230 are connected through word lines WL0... WLn−1 and WLn. In addition, the gates of the drain select transistors DST arranged side by side are connected through the drain select line DSL, and the gates of the source select transistors SST are connected through the source select line SSL. In addition, the memory cell block 210 may include a bit line BL that is formed to cross the word lines and is connected to the main string structure 220 or the flag string structure 230. The main string structures 220 and the flag string structures 230 connected to the bit lines BL in the memory block 210 are connected in parallel to the common source line CSL.

The memory cell block 210 is formed on the bulk 260 formed on the semiconductor substrate by implanting impurity ions into the semiconductor substrate.

The voltage generator 250 generates voltages required for memory cell operation of the selected memory cell block 210. That is, the voltage generator 250 includes a driving voltage applied to a word line, such as a pass voltage V PASS , a program voltage V pgm , a read voltage V read , and a driving voltage V DSL applied to a drain selection line. The driving voltage V SSL applied to the source selection line, the driving voltage V CSL applied to the common source line, and the driving voltage V BULK applied to the bulk are generated and applied to the selected memory cell block 210. .

The controller 240 controls the voltage generator 250 to output voltages necessary for the operation of the memory cell according to the operation of the memory cell. The controller 240 also controls the voltage generator 250 to output operating voltages of the memory cells according to the number of cycles stored in the flag cells of the selected memory cell block 210.

Hereinafter, a method of erasing a flash memory device according to a first embodiment of the present invention will be described in more detail with reference to FIGS. 2 and 3.

2 and 3, before performing the step S5 of applying the erase voltage, the step S1 of counting the number of cycles and the step of determining the erase verification voltage according to the number of cycles are performed. do.

The cycle number is a cumulative number of program / erase operations performed from the manufacture of the flash memory device until the previous erase operation is completed, and is stored in the flag cell of the memory block 210. Before performing the step of applying the erase voltage (S5), first, the number of cycles stored in the flag cell is counted (S1).

Thereafter, the erase verify voltage is determined according to the number of cycles (S3). For example, if the number of cycles stored in the flag cell is read out and the number of cycles is less than 1000, the erase verification voltage is set to be the first level. When the first level is -1 V, as shown in Table 1, the read voltage V read of the word line is set to 0 V during erase verification, and the voltage V CSL applied to the common source line and the voltage applied to the bulk. Set (V BULK ) to 0V. When the number of cycles stored in the flag cell is 1000 or more and less than 5000, the erase verification voltage Vev is set to be a second level lower than the first level. To this end, as shown in Table 1, the read voltage V read of the word line is set to 0 V during erase verification, and the voltage V CSL applied to the common source line and the voltage V BULK applied to the bulk are 0.5 V. Set to. In addition, when the number of cycles stored in the flag cell is 5000 or more and less than 10,000, the erase verification voltage is set to be a third level lower than the second level. To this end, as shown in Table 1, the read voltage (V read ) of the word line is set to 0 V during erase verification, and the voltage (V CSL ) applied to the common source line and the voltage (V BULK ) applied to the bulk are 1.5. Set to V.

Elimination verification first level
(Cycles <1000) Elimination verification second level
(Cycles <5000) Elimination Verification Level 3
(Cycles <10000) WL0 to WLn 0 V 0 V 0 V DSL Vcc Vcc Vcc SSL Vcc Vcc Vcc CSL 0 V 0.5 V 1 V Selected BL 1 V 1 V 1 V Unselected BL 0 V 0 V 0 V BULK 0 V 0.5 V 1 V

As described above, in the present invention, as the number of cycles increases, the erase verify voltage may be set as low as a predetermined step, and the voltage applied to the common source line as the number of cycles increases so that the erase verify voltage is set lower (V CSL). ) And increase the voltage (V BULK ) applied to the bulk.

In addition to increasing the voltage applied to the common source line and the substrate in order to lower the erase verify voltage, there is a method of increasing the sensing level of a page buffer (not shown) electrically connected to the selected memory cell block. The page buffer is electrically connected to the selected memory cell block through the bit line.

When the erase verify voltage is determined according to the number of cycles as described above, an erase voltage is applied to the bulk 260 of the selected memory cell block 210 to erase the memory cells (S5).

Thereafter, it is verified whether threshold voltages of the memory cells included in the selected memory cell block 210 are lowered below the erase verification voltage (S7). In more detail with reference to Table 1, the power source voltage Vcc is applied to the drain select line DSL and the source select line SSL, and 0V is applied to all word lines in order to perform step S7. Then, a predetermined voltage (for example, 1V) is applied to the bit line connected to the selected memory cell block 210 and 0V is applied to the remaining bit lines. In addition, the voltages V CSL and V BULK determined according to the erase verify voltage determined in step S3 are applied to the common source line CSL and the bulk 260, respectively.

Steps S5 and S7 are performed in an incremental step plus erase (ISPE) method. That is, steps S5 and S7 are repeated until the threshold voltage of the erase cell becomes lower than the erase verify voltage determined in step S3. According to the ISPE method, whenever the step S5 is repeated, the erase voltage is adjusted to be higher by a predetermined step voltage (S9). Step S7 is performed every time step S5 is performed with the increased erase voltage.

Since the erase verify voltage in step S7 is a voltage set according to the number of cycles in step S3, as the number of cycles increases, the threshold voltage of the erase cell is adjusted lower.

When the threshold voltage of the erase cell is lower than the erase verify voltage in step S7, the soft program voltage Vpgm is applied to implement a soft program for correcting the threshold voltage of an excessively erased cell according to the characteristics of the memory cell ( S11). 0 V is applied to the bulk 260 of the memory cell block selected in step S11, a power supply voltage Vcc is applied to the drain select line DSL, and 0 V is applied to the source select line SSL.

Thereafter, it is verified whether the threshold voltages of the memory cells are higher than the erase verify voltage (S13). Steps S11 and S13 are repeated until the threshold voltage of the erase cell becomes higher than the erase verify voltage. Each time the step S11 is repeated, the soft program voltage is adjusted as high as a constant step voltage (S15). The step S15 is performed every time the step S11 is performed with the increased soft program voltage.

When the threshold voltage of the erase cell becomes equal to or greater than the erase verify voltage in step S13, the accumulated number of cycles of the selected memory cell block is increased and stored in the flag cell (S17). After that, the erase operation is completed. At this time, as the number of cycling increases, the program speed of the memory cell increases, so that the threshold voltage of the erase cell tends to be much higher than the erase verify voltage. In the first embodiment of the present invention, in consideration of increasing the program speed of the memory cell as the number of cycling increases, the erase verify voltage is set according to the number of cycling after counting the number of cycling. More specifically, in the first exemplary embodiment of the present invention, the larger the number of cycling, the lower the erase verify voltage is. Therefore, as the number of cycles increases, the program rate of the memory cell during soft programming increases, so that the threshold voltage of the erase cell becomes 0V or less through the erase verify voltage set lower from the beginning of the soft program even though the program rate of the memory cell increases. That is, in the first embodiment of the present invention, since the threshold voltage distribution of the erase cell is distributed to a lower level after cycling, the erase state can be maintained even if the threshold voltage of the erase cell after the cycling increases greatly through a soft program.

4 and 5 are diagrams for describing a method of erasing a flash memory device according to a second embodiment of the present invention. 4 is a view illustrating a flash memory device according to a second embodiment of the present invention, and FIG. 5 is a flowchart illustrating a method of erasing a flash memory device according to a second embodiment of the present invention.

Referring to FIG. 4, the flash memory device according to the second embodiment of the present invention includes a plurality of memory cell blocks 310.

Each memory cell block 310 includes a plurality of memory cell string structures 320. Each memory cell string structure 320 includes a plurality of memory cells MC0 connected in series between a drain select transistor DST, a source select transistor SST, a drain select transistor DST, and a source select transistor SST. .MCn-1, MCn). Gates of the memory cells of the string structure 320 arranged side by side are connected through word lines WL0... WLn−1 and WLn. In addition, the gates of the drain select transistors DST arranged side by side are connected through the drain select line DSL, and the gates of the source select transistors SST are connected through the source select line SSL. In addition, the memory cell block 310 may include a bit line BL formed to cross word lines and connected to the memory cell string structure 320. The memory cell string structures 320 connected to the bit lines BL in the memory block 310 are connected in parallel to the common source line CSL.

The memory cell block 310 is formed on the bulk 360 formed on the semiconductor substrate by implanting impurity ions into the semiconductor substrate.

Hereinafter, a method of erasing a flash memory device according to a second exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5.

4 and 5, initial values of the erase voltage and the erase verify voltage of the memory cell block selected for erasing the flash memory device are determined (SS1).

Thereafter, the initial value of the erase voltage is applied to the bulk 360 of the selected memory cell block to erase the memory cells in the selected memory cell block (SS3).

Thereafter, it is verified whether the threshold voltages of the memory cells included in the selected memory cell block 310 are lowered below the erase verify voltage set in the SS1 step (SS5). Step SS5 is the same as step S7 described above with reference to FIG. 3.

The SS3 and SS5 steps are performed in an incremental step plus erase (ISPE) method. According to the ISPE method, the SS3 and SS5 steps are repeated. Each time the SS3 step is repeated, the erase voltage is adjusted not only by a high step voltage but also by the erase verify voltage by a constant step voltage (SS7). The SS3 and SS5 steps are repeated until the threshold voltage of the erase cell is lower than the erase verify voltage. The SS5 stage is performed every time the SS3 stage is performed with the increased erase voltage and the reduced erase verify voltage.

In order to reduce the erase verify voltage every time the SS7 step is performed, each voltage applied to the common source line CSL and the bulk 360 in the SS5 step is increased by a constant voltage each time the SS7 step is performed. In addition, there is a method of increasing the sensing level of a page buffer (not shown) connected to the selected memory cell block every time the SS7 step is performed in order to reduce the erase verification voltage every time the SS7 step is performed.

As described above, according to the second exemplary embodiment of the present invention, the erase verify voltage is adjusted to be lowered at the same time whenever the erase voltage rises by a predetermined step voltage, so that the erase verify voltage is adjusted lower as the erase count is increased, even if the number of cycles is not checked separately. Can be.

When the threshold voltage of the erase cell is lower than the erase verify voltage in step SS5, a soft program voltage is applied to correct the threshold voltage of an over erased cell according to the characteristics of the memory cell (SS11).

Thereafter, it is verified whether the threshold voltages of the memory cells are higher than the erase verify voltage (SS13). The SS11 and SS13 steps are repeated until the threshold voltage of the erase cell becomes higher than the erase verify voltage. Each time the SS11 step is repeated, the soft program voltage is adjusted as high as a constant step voltage (SS15).

Descriptions of steps SS11 to SS15 are the same as steps S11 to S15 described above with reference to FIG. 3.

When the threshold voltage of the erase cell becomes greater than the erase verify voltage in step SS13, the erase of the selected memory cell block is completed. At this time, as the number of cycling increases (that is, as the erase count increases), the program speed of the memory cell increases, so that the threshold voltage of the erase cell tends to be much higher than the erase verify voltage. In the second embodiment of the present invention, since the erase verify voltage is lowered every time the erase operation is performed by increasing the erase voltage by the ISPE method, the erase verify voltage may be set lower as the number of cycling increases. Therefore, as the number of cycles increases, the program rate of the memory cell during soft programming increases, so that the threshold voltage of the erase cell becomes 0V or less through the erase verify voltage set lower from the beginning of the soft program even though the program rate of the memory cell increases. That is, in the second embodiment of the present invention, since the threshold voltage distribution of the erase cell is distributed to a lower level after cycling, the erase state can be maintained even if the threshold voltage of the erase cell after the cycling increases greatly through a soft program.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a view for explaining a problem that the threshold voltage of a conventional erased cell rises.

2 is a view for explaining a flash memory device according to a first embodiment of the present invention;

3 is a flowchart illustrating a method of erasing a flash memory device according to a first embodiment of the present invention.

 4 is a diagram for describing a flash memory device according to a second embodiment of the present invention.

5 is a flowchart illustrating a method of erasing a flash memory device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210, 310: memory cell blocks 220, 320: memory cell strings

230: flag cell string 240: controller

250: voltage generator 260, 360: bulk

Claims (13)

Counting accumulated program / erase operations of a selected memory cell block among memory cell blocks formed on the bulk of the semiconductor substrate and including a plurality of memory cell strings connected in parallel to a common source line; Determining an erase verify voltage according to the accumulated number of program / erase operations; An erase step of applying an erase voltage to the selected memory cell block; And And an erase verifying step of comparing the erase verifying voltage with threshold voltages of the memory cells forming the selected memory cell blocks to determine whether to erase the erase verifying voltage. The method of claim 1, And in the determining of the erase verify voltage, the erase verify voltage is set lower as the accumulated number of program / erase operations increases. The method of claim 1, The voltage applied to the common source line and the bulk in the erase verifying step increases as the accumulated program / erase operation count increases. The method of claim 1, And a sensing level of a page buffer connected to the selected memory cell block increases as the accumulated program / erase operation count increases. The method of claim 1, And deleting the erase voltage by repeating the erase operation when the threshold voltage of the memory cells is higher than the erase verify voltage in the erase verifying step. The method of claim 1, If the threshold voltage of the memory cells in the erase verify step is lower than the erase verify voltage, after the erase verify step, A soft program step of applying a soft program voltage to the memory cells; And And performing a soft program verification step of comparing the threshold voltages of the memory cells with the erase verify voltage. The method of claim 6, And in the soft program verifying step, if the threshold voltage of the memory cells is lower than the erase verify voltage, the soft program voltage is increased to repeat the soft program operation. The method of claim 6, And storing the number of program / erase operations when the threshold voltages of the memory cells are higher than the erase verify voltage in the soft program verifying step. An erase step of applying an erase voltage to a selected memory cell block among memory cell blocks formed on the bulk of the semiconductor substrate and including a plurality of memory cell strings connected in parallel to a common source line; An erase verification step of comparing an erase verification voltage with threshold voltages of memory cells constituting the selected memory cell block; If the threshold voltage of the memory cells is higher than the erase verify voltage, the erase voltage is increased, and the erase verify voltage is repeated to repeat the erase step and the erase verify step. The method of claim 9, And repeating the erase verification step by lowering the erase verify voltage to increase the voltage applied to the common source line and the bulk. The method of claim 9, And when the erase verifying step is repeated by lowering the erase verifying voltage, the sensing level of the page buffer connected to the selected memory cell block increases. The method of claim 9, If the threshold voltage of the memory cells in the erase verify step is lower than the erase verify voltage, after the erase verify step, A soft program step of applying a soft program voltage to the memory cells; And And performing a soft program verification step of comparing the threshold voltages of the memory cells with the erase verify voltage. 13. The method of claim 12, And repeating the soft program operation by increasing the soft program voltage if the threshold voltage of the memory cells is lower than the erase verify voltage in the soft program verifying step.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012159490A1 (en) * 2011-05-26 2012-11-29 忆正科技（武汉）有限公司 Error estimation module and estimation method thereof for flash memory
US9842658B2 (en) 2015-04-20 2017-12-12 Samsung Electronics Co., Ltd. Methods of operating nonvolatile memory devices including variable verification voltages based on program/erase cycle information
CN109960468A (en) * 2019-01-29 2019-07-02 华中科技大学 A kind of non-volatile memory cells method for deleting having authentication function and system
CN111863093A (en) * 2019-04-29 2020-10-30 北京兆易创新科技股份有限公司 Erasing method and device of nonvolatile memory
US11177016B2 (en) 2019-05-30 2021-11-16 Winbond Electronics Corp. Non-volatile memory device and erasing operation method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012159490A1 (en) * 2011-05-26 2012-11-29 忆正科技（武汉）有限公司 Error estimation module and estimation method thereof for flash memory
US9842658B2 (en) 2015-04-20 2017-12-12 Samsung Electronics Co., Ltd. Methods of operating nonvolatile memory devices including variable verification voltages based on program/erase cycle information
CN109960468A (en) * 2019-01-29 2019-07-02 华中科技大学 A kind of non-volatile memory cells method for deleting having authentication function and system
CN111863093A (en) * 2019-04-29 2020-10-30 北京兆易创新科技股份有限公司 Erasing method and device of nonvolatile memory
US11177016B2 (en) 2019-05-30 2021-11-16 Winbond Electronics Corp. Non-volatile memory device and erasing operation method thereof

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