KR20100063982A - Plasma display apparatus - Google Patents

Abstract

PURPOSE: A plasma display apparatus is provided to generate sustain discharge by using self erase discharge in a sustain signal voltage falling period, so shortening a sustain signal period and a voltage drop period. CONSTITUTION: A plasma display panel comprises a scan electrode and a sustain electrode. A driver supplies a sustain signal to at least one of the two electrodes. A sustain signal comprises a rising time, a maintaining period, and a falling period. The sustain signal is provided in the sustain period of at least one sub-field.

Description

Plasma Display Apparatus {Plasma Display Apparatus}

The present invention relates to a plasma display device.

The plasma display apparatus includes a plasma display panel.

The plasma display panel includes a phosphor layer formed in a discharge cell divided by a partition wall, and also includes a plurality of electrodes.

When the drive signal is supplied to the electrode of the plasma display panel, the discharge is generated by the drive signal supplied in the discharge cell. Here, when discharged by a drive signal in the discharge cell, the discharge gas filled in the discharge cell generates vacuum ultraviolet rays, and the vacuum ultraviolet light emits the phosphor formed in the discharge cell to emit visible light. Generate. The visible light displays an image on the screen of the plasma display panel.

The present invention provides a plasma display device that generates a sustain discharge by using a self erase discharge in a voltage drop period of the sustain signal by shortening the period of the sustain signal and shortening the length of the voltage drop period (ER-Down). The purpose is to provide.

A plasma display apparatus according to the present invention includes a plasma display panel including a scan electrode and a sustain electrode and a scan electrode and a sustain electrode in a sustain period of at least one subfield of a plurality of subfields of a frame. A driving unit for supplying a sustain signal including at least one of a rising period in which the voltage rises, a sustain period in which the sustain voltage is maintained, and a falling period in which the voltage falls, and a supply sequence of at least two sustain signals in a continuous supply order The discharge occurring in the voltage drop period of the sustain signal earlier than the sustain signal may be continuous.

In addition, a period of the sustain signal may be 2.0 ms to 4.0 ms.

In addition, the length of the voltage drop period may be shorter than the length of the voltage rise period.

In addition, the length of the voltage rising period may be 400 kV to 600 kV.

In addition, the length of the voltage drop period may be 300 kV to 500 kV.

In addition, the sustain signal may be alternately supplied to the scan electrode and the sustain electrode in the sustain period.

In addition, a self erasing discharge occurs in the voltage drop period of the first sustain signal among the plurality of sustain signals, and continues in the voltage erasing period of the second sustain signal continuous with the first sustain signal. Sustain discharge can occur.

In addition, the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode may overlap each other.

In addition, the length of the period in which the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode overlap each other may be 0.5 times or less the length of the voltage falling period.

In addition, the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode may not overlap each other.

In addition, another plasma display apparatus according to the present invention is a plasma display panel including a scan electrode and a sustain electrode and a scan electrode in a sustain period of at least one subfield of a plurality of subfields of a frame. And a driving unit supplying a sustain signal to at least one of the sustain electrodes, the sustaining period in which the voltage rises, the sustaining period in which the sustain voltage is maintained, and the falling period in which the voltage falls. The length of the voltage drop period of the sustain signal can be adjusted differently according to the total number of.

In addition, the total number of sustain signals allocated to one frame may be determined by an average power level (APL) of an input image.

In addition, when the total number of the sustain signals allocated to one frame is N, the length of the voltage drop period of the sustain signal is the length of the voltage falling period of the sustain signal when the total number of sustain signals allocated to one frame is more than N. It may be shorter than the length of.

In addition, a period of the sustain signal may be 2.0 ms to 4.0 ms.

In addition, the length of the voltage drop period may be shorter than the length of the voltage rise period.

Further, among the at least two sustain signals in which the supply order is continuous, the discharge occurring in the voltage drop period of the sustain signal preceding the supply order and the discharge occurring in the voltage rise period of the other sustain signal may be continuous.

The plasma display device according to the present invention shortens the period of the sustain signal and shortens the length of the voltage drop period (ER-Down) to perform sustain discharge using self erase discharge in the voltage drop period of the sustain signal. By generating it, there is an effect of lowering the discharge voltage and increasing the driving efficiency.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining the configuration of a plasma display device according to an embodiment of the present invention.

Referring to FIG. 1, a plasma display apparatus according to an exemplary embodiment may include a plasma display panel 100 and a driver 110.

The plasma display panel 100 may include scan electrodes Y1 to Yn and sustain electrodes Z1 to Zn that are parallel to each other, and may include address electrodes X1 to Xm that cross the scan electrode and the sustain electrode. In addition, the plasma display panel 100 may implement an image in a frame including a plurality of subfields.

The driver 110 may supply a driving signal to at least one of a scan electrode, a sustain electrode, and an address electrode of the plasma display panel 100 to implement an image on the screen of the plasma display panel 100. Preferably, the driver 110 increases the voltage of at least one of the scan electrode and the sustain electrode of the plasma display panel 100 in the sustain period of at least one subfield of the plurality of subfields of the frame. The sustain signal can be supplied including a rising period, a sustaining period in which the sustain voltage is maintained, and a falling period in which the voltage falls.

Herein, the driving unit 110 may control such that the discharge occurring in the voltage drop period of the sustain signal preceding the supply signal and the discharge occurring in the voltage rising period of the other sustain signal among the at least two sustain signals having the continuous supply order are continuous. have.

In addition, although not shown, the driving unit 110 may include a data integrated circuit (Data IC) for supplying a data signal to the address electrode of the plasma display panel 100.

Here, in FIG. 1, only the case in which the driving unit 110 is formed in one board form is illustrated, but in the present invention, the driving unit 110 is divided into a plurality of board forms according to electrodes formed on the plasma display panel 100. It is also possible to lose. For example, the driver 110 may include a first driver (not shown) for driving the scan electrode of the plasma display panel 100, a second driver for driving the sustain electrode, and a third driver (not shown) for driving the address electrode. Can be divided into

2 is a diagram for explaining the structure of a plasma display panel.

Referring to FIG. 2, the plasma display panel 100 includes a front substrate 201 in which scan electrodes 202 and Y and sustain electrodes 203 and Z are parallel to each other, and scan electrodes 202 and Y and a sustain electrode ( The back substrate 211 on which the address electrodes 213 and X intersect with 203 and Z may be formed.

On the front substrate 201 where the scan electrodes 202 and Y and the sustain electrodes 203 and Z are formed, the discharge currents of the scan electrodes 202 and Y and the sustain electrodes 203 and Z are limited and the scan electrodes 202 and Y are restricted. ) And an upper dielectric layer 204 may be arranged to insulate between the sustain electrodes 203 and Z.

A protective layer 205 may be formed on the front substrate 201 where the upper dielectric layer 204 is formed to facilitate discharge conditions. The protective layer 205 may include a material having a high secondary electron emission coefficient, such as magnesium oxide (MgO) material.

The address electrodes 213 and X are formed on the rear substrate 211, and the address electrodes 213 and X are covered on the upper side of the rear substrate 211 on which the address electrodes 213 and X are formed. A lower dielectric layer 215 may be formed that insulates X).

On top of the lower dielectric layer 215, a partition space 212, such as a stripe type, a well type, a delta type, a honeycomb type, etc., is formed on the discharge space, that is, to partition the discharge cells. Can be. Accordingly, the first discharge cell emitting red (R) light, the second discharge cell emitting blue (B) light, and the green (Green) light between the front substrate 201 and the rear substrate 211. : G) A third discharge cell or the like that emits light can be formed.

Here, the partition 212 may include a first partition 212b and a second partition 212a having different heights, and the height of the first partition 212b may be lower than the height of the second partition 212a. .

A predetermined discharge gas may be filled in the discharge cell partitioned by the partition wall 212.

In addition, a phosphor layer 214 that emits visible light for image display may be formed in the discharge cells partitioned by the partition wall 212. For example, a first phosphor layer that generates red light, a second phosphor layer that generates blue light, and a third phosphor layer that generates green light may be formed.

In addition, the address electrode 213 formed on the rear substrate 211 may have substantially the same width or thickness, but the width or thickness inside the discharge cell may be different from the width or thickness outside the discharge cell. . For example, the width or thickness inside the discharge cell may be wider or thicker than that outside the discharge cell.

When a predetermined signal is supplied to at least one of the scan electrode 202, the sustain electrode 203, and the address electrode 213, discharge may occur in the discharge cell. As such, when discharge is generated in the discharge cell, ultraviolet rays may be generated by the discharge gas filled in the discharge cell, and the ultraviolet rays may be irradiated onto the phosphor particles of the phosphor layer 214. Then, a predetermined image may be displayed on the screen of the plasma display panel 100 by the phosphor particles irradiated with ultraviolet rays to emit visible light.

FIG. 3 is a diagram for describing an image frame for implementing gradation of an image.

Referring to FIG. 3, a frame for implementing gray levels of an image may include a plurality of subfields SF1 to SF8.

In addition, the plurality of subfields may include a sustain period for implementing gradation according to an address period and a number of discharges for selecting discharge cells in which discharge cells will not occur or discharge cells in which discharge occurs. Period) may be included.

For example, in case of displaying an image with 256 gray levels, for example, one frame is divided into eight subfields SF1 to SF8 as shown in FIG. 3, and each of the eight subfields SF1 to SF8 is an address. It can include a period and a sustain period.

Alternatively, at least one subfield of the plurality of subfields of the frame may further include a reset period for initialization.

In addition, at least one subfield of the plurality of subfields of the frame may not include a sustain period.

Meanwhile, the weight of the corresponding subfield may be set by adjusting the number of sustain signals supplied in the sustain period. That is, a predetermined weight can be given to each subfield using the sustain period. For example, the weight of each subfield is 2 ⁿ by setting the weight of the first subfield to 2 ⁰ and the weight of the second subfield to 2 ¹ (where n = 0, 1, 2). , 3, 4, 5, 6, 7) can be set to increase. As described above, gray levels of various images may be realized by adjusting the number of sustain signals supplied in the sustain period of each subfield according to the weight in each subfield.

In FIG. 3, only one image frame is composed of eight subfields. However, the number of subfields constituting one image frame may be variously changed. For example, one video frame may be configured with 12 subfields from the first subfield to the twelfth subfield, or one video frame may be configured with 10 subfields.

In addition, in FIG. 3, subfields are arranged in an order of increasing weight in one image frame. Alternatively, subfields may be arranged in an order of decreasing weight in one image frame. Subfields may be arranged regardless.

At least one of the plurality of subfields included in the frame may be a selective erase subfield (SE), and at least one of the plurality of subfields may be a selective write subfield (SW). Do.

If one frame includes at least one selective erase subfield and an optional write subfield, the first subfield or the first and second subfields of the plurality of subfields of the frame are the selective write subfields, It may be desirable for the remainder to be selective erasure subfields.

Here, the selective erasing subfield is a subfield that turns off the discharge cells supplied with the data signal Data to the address electrodes in the address period in the sustain period after the address period.

The selective erasure subfield may include an address period for selecting a discharge cell to be turned off and a sustain period for generating sustain discharge in discharge cells not selected in the address period.

The selective write subfield is a subfield that turns on the discharge cells supplied with the data signal Data to the address electrodes in the address period in the sustain period after the address period.

The selective write subfield may include a reset period for initializing the discharge cells, an address period for selecting the discharge cells to be turned on, and a sustain period for generating sustain discharge in the discharge cells selected in the address period.

4 is a diagram schematically illustrating a method of driving a plasma display device. The driving signals to be described below are supplied by the driving unit 110 of FIG. 1.

Referring to FIG. 4, in the reset period RP for initializing at least one subfield among a plurality of subfields of a frame, the reset signal RS is applied to the scan electrode Y. Can supply Here, the reset signal RS may include a rising ramp signal (Ramp-Up: RU) in which the voltage gradually rises and a falling ramp signal (Ramp-Down: RD) in which the voltage gradually falls.

For example, the rising ramp signal RU may be supplied to the scan electrode in the setup period SU of the reset period, and the falling ramp signal RD may be supplied to the scan electrode in the setdown period SD after the setup period. .

When the rising ramp signal is supplied to the scan electrode, a weak dark discharge, that is, setup discharge, occurs in the discharge cell by the rising ramp signal. By this setup discharge, the distribution of wall charges can be uniform in the discharge cells.

After the rising ramp signal is supplied, when the falling ramp signal is supplied to the scan electrode, a weak erase discharge, that is, a setdown discharge, occurs in the discharge cell. By this set-down discharge, wall charges such that address discharge can be stably generated can be uniformly retained in the discharge cells.

In the address period AP after the reset period, the scan reference signal Ybias having a voltage higher than the lowest voltage of the falling ramp signal may be supplied to the scan electrode.

In addition, in the address period, the scan signal Sc that falls from the voltage of the scan reference signal Ybias may be supplied to the scan electrode.

Meanwhile, the pulse width of the scan signal supplied to the scan electrode in the address period of at least one subfield may be different from the pulse width of the scan signal of another subfield. For example, the width of the scan signal in the subfield located later in time may be smaller than the width of the scan signal in the preceding subfield. In addition, the reduction of the scan signal width according to the arrangement order of the subfields can be made gradually, such as 2.6 Hz (microseconds), 2.3 Hz, 2.1 Hz, 1.9 Hz, or 2.6 Hz, 2.3 Hz, 2.3 Hz, 2.1 Hz. .... 1.9 ㎲, 1.9 ㎲ and so on.

As such, when the scan signal is supplied to the scan electrode, the data signal Dt may be supplied to the address electrode X corresponding to the scan signal.

When the scan signal and the data signal are supplied, an address discharge may be generated in the discharge cell to which the data signal is supplied while the voltage difference between the scan signal and the data signal and the wall voltage generated by the wall charges generated in the reset period are added. .

In addition, the sustain reference signal Zbias signal may be supplied to the sustain electrode in the address period in which the address discharge occurs so that the address discharge is effectively generated between the scan electrode and the address electrode.

In the sustain period SP after the address period, the sustain signal SUS may be supplied to at least one of the scan electrode and the sustain electrode. For example, a sustain signal may be alternately supplied to the scan electrode and the sustain electrode.

When such a sustain signal is supplied, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the sustain voltage Vs of the sustain signal, and a sustain discharge, i.e., display between the scan electrode and the sustain electrode when the sustain signal is supplied. Discharge may occur.

In this way, an image can be realized.

5 to 10 are views for explaining the sustain signal in more detail. Here, the sustain signal includes a voltage rising period d1 at which the voltage gradually increases due to LC resonance of the inductor, a voltage holding period d2 at which the maximum voltage, that is, the sustain voltage Vs, and the LC resonance of the inductor are maintained. It may include a voltage falling period (d3) that the voltage is gradually lowered by.

In addition, it is preferable that the discharge occurring in the voltage drop period of the sustain signal and the sustain signal preceding the supply signal out of the at least two sustain signals in which the supply order is consecutive among the plurality of sustain signals is continuous. Can be.

As such, at least one of the scan electrode and the sustain electrode may be such that the discharge occurring in the voltage drop period of the sustain signal preceded by the supply order of the at least two sustain signals is continuous with the discharge occurring in the voltage rise period of the other sustain signal. The period of the sustain signal supplied to the circuit can be shortened, and the length of the voltage drop period (ER-Down Period) of the sustain signal can be shortened. More preferably, the driving unit 110 may shorten the period of the sustain signal to about 2.0 kV to about 4.0 kV, and may shorten the length of the voltage drop period of the sustain signal to be shorter than the length of the ER-Up period. .

This will be described in more detail below.

In the sustain period of at least one subfield of the plurality of subfields of the frame as shown in FIG. 5, the sustain signal SUS is alternately supplied to the scan electrode and the sustain electrode, and the supply period T1 of the sustain signal is shortened. Can be. In this case, the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode may not overlap each other.

For example, in FIG. 6B, one period of the sustain signal is T2, and in (a), one period of the sustain signal is T1 smaller than T2.

In this case, if one cycle T1 of the sustain signal is shortened as shown in (a), since the sustain signal can be supplied in a larger number of sustain signals than in the case of (b), the luminance can be increased.

In addition, when the period T1 of the sustain signal is unconditionally reduced in order to supply more sustain signals within a predetermined sustain period, the sustain discharge may become unstable because the sustain period of the sustain discharge is excessively shortened.

Therefore, it may be desirable to make one period T1 of the sustain signal smaller than about 4.0 ms, and more preferably, the period of the sustain signal may be 2.0 ms to 4.0 ms.

However, the method of simply shortening one cycle T1 of the sustain signal causes self erase discharge (SED), and the wall charge is erased by the self erase discharge so that the discharge may not occur smoothly.

For example, after the first sustain signal SUS1 is supplied to the scan electrode as in the case of FIG. 7, the second sustain signal SUS2 continuous to the first sustain signal SUS1 is supplied to the sustain electrode. Let's assume.

In this case, when one cycle T1 of the sustain signal is about 4.0 kV, the first sustain signal SUS1 is again generated after the sustain discharge (SD) occurs in the voltage rising period of the first sustain signal SUS1. The self-erasing discharge (SED) may occur in the voltage drop period.

Then, the wall charges can be erased by the self erasing discharge, and accordingly, the intensity of the sustain discharge SD generated in the voltage rise period of the second sustain signal SUS2 which is supplied next can be excessively weakened. . Even when an excessively large amount of wall charge is erased by the self-erasing discharge, sustain discharge may not occur in the voltage rising period of the second sustain signal SUS2.

As described above, in order to prevent the sustain discharge from becoming unstable due to the short period of the sustain signal due to the self-erasing discharge, the length of the voltage drop period d3 of the sustain signal is defined as the voltage rise period of the sustain signal ( It may be desirable to make it shorter than the length of d1).

On the other hand, if the length of the voltage drop period d3 of the sustain signal is excessively short, the energy recovery efficiency of the energy recovery circuit including the inductor may be excessively lowered, so that the voltage drop of the sustain signal may be reduced. It may be desirable to set the length of the period d3 to approximately 300 ms to 500 ms.

On the other hand, the length of the voltage rising period d1 of the sustain signal may be longer than the length of the voltage falling period d3, and if the length of the voltage rising period d1 of the sustain signal is increased, The driving efficiency can be improved because sufficient time for supplying the voltage can be secured. However, if the length of the voltage rise period d1 of the sustain signal is excessively long, the period T1 of the sustain signal becomes long, and thus driving efficiency and luminance characteristics may be deteriorated.

In consideration of this, the length of the voltage rise period of the sustain signal may be 400 kV to 600 kV.

In addition, as in the case of FIG. 8, the period of the sustain signal is shortened, and in this case, when the length of the voltage drop period d3 of the sustain signal is shorter than the length of the voltage rise period d1, Erase discharge and sustain discharge may occur continuously.

In detail, as the period T1 of the sustain signal is shortened and the length of the voltage drop period d3 of the sustain signal becomes shorter than the length of the voltage rise period d1, the voltage fall period of the first sustain signal SUS1. The sustain discharge SD may be continuously generated in the voltage rising period of the second sustain signal SUS2 after the self erase discharge SED occurs in (d1) and before the self erase discharge is terminated. Point P shown in FIG. 9 may be a point where the self erase discharge and the sustain discharge are continuous. That is, the self erase discharge and the sustain discharge may overlap each other.

In this case, even if the amount of wall charges decreases due to the occurrence of the self erasing discharge in the voltage drop period d3 of the first sustain signal SUS1, the space charge generated by the self erasing discharge before the self erasing discharge ends. The sustain discharge SD may be generated in the voltage rising period d1 of the second sustain signal SUS2 by using the first and second sustain signals SUS2.

Accordingly, even when the sustain voltage Vs is lowered, sustain discharge may occur, thereby lowering the driving voltage and improving driving efficiency.

In other words, when the period T1 of the sustain signal is shorter than 4.0 Hz, if the length of the voltage drop period d3 of the sustain signal is shorter than the length of the voltage rise period d1, the period T1 of the sustain signal is As it becomes shorter, stable sustain driving is possible even if self-erase discharge occurs.

In addition, in order to more effectively use the space charges generated by the self-erasing discharge, the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode, as shown in (a), (b) and (c) of FIG. Can overlap each other.

As such, when the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode are superimposed, the voltage rise of the next sustain signal becomes more effective before the self-erasing discharge occurring in the voltage drop period of the previous sustain signal ends. Since sustain discharge can be generated in the period, it is possible to further improve the driving efficiency.

In addition, as a method of superimposing the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode, a method of continuously superimposing a continuous sustain signal as shown in (b), or the sustain signal as shown in (c) It may be possible to superimpose the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode only during one period T1.

In addition, the length of the period d4 in which the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode overlaps with each other is determined by using the space charge formed by the self-erasing discharge generated in the voltage drop period of the previous sustain signal. It may be desirable to be adjusted to satisfy the condition of generating sustain discharge in the voltage rise period of the tain signal.

Specifically, if the length of the period d4 where the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode overlaps excessively long, the sustain discharge is caused by the next sustain signal before the self-erasing discharge is sufficiently generated. This can happen. In such a case, the sustain discharge cannot sufficiently utilize the space charge due to the short period of the sustain signal, and thus the intensity of the sustain discharge may be excessively weakened or even the sustain discharge may not occur.

In consideration of this, it may be preferable that the length of the period d4 in which the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode overlap is approximately 0.5 times or less than the length of the voltage drop period d3 of the sustain signal. .

11 to 13 are views for comparing the embodiment and the comparative example according to the present invention.

First, (a) in FIG. 11 is a case where the period of the sustain signal is about 4.0 ms, the length of the voltage rising period is about 540 ms, and the length of the voltage falling period is about 600 ms.

In addition, (b) shows the sustain signal supplied to the scan electrode as the first embodiment, the period of the sustain signal is approximately 4.0 ms, the voltage rise period is approximately 500 ms, and the voltage fall period is approximately 400 ms. And the sustain signal supplied to the sustain electrode do not overlap.

In addition, (c) shows the sustain signal supplied to the scan electrode with the period of the sustain signal being approximately 4.0 ms, the voltage rising period being approximately 500 ms, the voltage falling period being approximately 400 ms, as a second embodiment. And the sustain signal supplied to the sustain electrode overlaps for about 160 ms.

First, looking at (a), it can be seen that in the case of the comparative example, the position of the point of time P at which the sustain discharge occurs during the voltage rise period of the sustain signal is relatively low.

This may mean that the voltage in the discharge cell is relatively low at the time point P at which the sustain discharge occurs in the voltage rising period of the sustain signal. Therefore, in order to stabilize the sustain discharge, the sustain voltage Vs must be increased. Can mean. As a result, the discharge voltage rises.

On the other hand, in the first embodiment as shown in (b), it can be seen that the voltage in the discharge cell is relatively high at the time point P when the sustain discharge occurs in the voltage rise period of the sustain signal.

This may mean that sustain discharge occurs continuously in the voltage rising period of the next sustain signal before the discharge generated in the voltage drop period of the sustain signal is completed. In addition, this may mean that the charges are more advantageous to the sustain discharge in the discharge cell at the time point P when the sustain discharge occurs in the voltage rising period of the sustain signal, and thus, the discharge cell in the first embodiment. It can be seen that the internal voltage is higher than that of the comparative example of (a).

In this case, even when the sustain voltage is lowered, stable sustain discharge may occur, thereby lowering the discharge voltage and improving driving efficiency.

In addition, in the second embodiment as shown in (c), the charges in the discharge cell are more advantageous to the sustain discharge at the point P when the sustain discharge occurs in the voltage rising period of the sustain signal than in the first embodiment of (b). Formed.

Accordingly, when the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode are superimposed, the driving efficiency can be further improved.

In FIG. 12, the comparative example is a case where the sustain signal has a period of approximately 3.2 ms, and the length of the voltage drop period and the voltage rise period of the sustain signal are substantially the same.

On the other hand, the embodiment is a case where the period of the sustain signal is the same as the comparative example, the length of the voltage sustain period of the sustain signal is the same, and the length of the voltage drop period of the sustain signal is shorter than the length of the voltage rise period. .

Comparing the embodiment with the comparative example, it can be seen that the driving voltage before the aging process and after the aging process is lower in the case of the embodiment.

This is because the self-erasing discharge and the sustain discharge may overlap each other in the case of the embodiment as shown in FIG. 9.

In the comparative example in Fig. 13, the sustain signal has a period of approximately 4.6 Hz, the length of the voltage rising period of the sustain signal is approximately 540 Hz, and the length of the voltage falling period is approximately 600 Hz.

On the other hand, in the embodiment, the sustain signal has a period of about 3.2 ms, the length of the voltage rising period of the sustain signal is about 500 ms, and the length of the voltage falling period is about 400 ms.

Referring to FIG. 13, it can be seen that the driving efficiency of the embodiment of the present invention is higher than that of the comparative example when the voltage of the sustain signal is 180V to 230V.

14 to 16 are diagrams for explaining an example of a method of differently adjusting a sustain signal according to the number of sustain signals allocated to one frame. Hereinafter, the description of the contents described above in detail will be omitted.

First, referring to FIG. 14, a concept of average power level (APL) is illustrated.

Average power level (APL) may be a method of adjusting the number of sustain signals in consideration of power consumption. In detail, the number of sustain signals allocated to one frame may be reduced in a direction of increasing power consumption, and the number of sustain signals allocated to a frame may be increased in a direction of decreasing power consumption.

For example, as shown in (a), when an image is displayed on a relatively small area on the screen of the plasma display panel (in this case, APL may be relatively low), power consumption may be relatively low. The number of sustain signals allocated to a frame can be relatively large. Then, the overall brightness of the image can be increased.

On the contrary, when the image is displayed on a relatively large area on the screen of the plasma display panel as shown in (b) (in this case, the APL may be relatively high), power consumption may be relatively high. The number of sustain signals allocated to one frame can be made relatively small. This prevents excessive power consumption.

As an example, when the average power level is a level, the number of sustain signals allocated to one frame in this case is N, and the sustain signal allocated to one frame when the average power level is b level higher than a level. The number of can be M less than N.

As such, when the average power level is relatively high and the number of sustain signals allocated to one frame is relatively small, as shown in FIG. 15B, the length of the voltage drop period d3 of the sustain signal is increased. It can be shorter than the length of the period d1.

In addition, when the average power level is relatively high and the number of sustain signals allocated to one frame is relatively small, the period T1 of the sustain signal can be relatively shortened as shown in FIG.

As described above, shortening the period of the sustain signal and making the length of the voltage drop period shorter than the length of the voltage rise period are for generating the next sustain discharge using the space charges formed by the self-erasing discharge. Since it has been described, further description will be omitted.

On the other hand, when the average power level is relatively low and the number of sustain signals allocated to one frame is relatively large, the length of the voltage drop period d3 of the sustain signal as shown in FIG. 15A is shown in FIG. 15B. It can be made longer than the case of.

As described above, when the total number of the sustain signals allocated to one frame is large, the reactive power may increase with the sustain signal. Therefore, in this case, shortening the length of the voltage drop period d3 of the sustain signal is not preferable because the energy recovery efficiency of the energy recovery circuit may be excessively lowered.

In addition, when the average power level is relatively low and the number of sustain signals allocated to one frame is relatively small, the period T1 of the sustain signal can be relatively long as shown in FIG.

Meanwhile, although only the case where the sustain signal is alternately supplied to the scan electrode and the sustain electrode in the sustain period, the discharge and the two occurring in the voltage drop period of the first sustain signal are different from each other. A single sustain driving method in which the sustain signal is supplied to only one of the scan electrode and the sustain electrode under the condition that discharges generated in the voltage rising period of the first sustain signal are continuous with each other can also be applied to the present invention.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the above-described embodiments are to be understood in all respects as illustrative and not restrictive, the scope of the present invention being indicated by the following claims rather than the foregoing description, and the meanings of the claims and All changes or modifications derived from the scope and the equivalent concept should be construed as being included in the scope of the present invention.

1 is a view for explaining the configuration of a plasma display device according to an embodiment of the present invention.

2 is a diagram for explaining the structure of a plasma display panel;

FIG. 3 is a diagram for explaining a frame for implementing gradation of an image. FIG.

4 is a view for schematically explaining a method of driving a plasma display device;

5 to 10 are views for explaining the sustain signal in more detail.

11 to 13 are views for comparing the embodiment and the comparative example according to the present invention.

14 to 16 are diagrams for explaining an example of a method of adjusting a sustain signal differently according to the number of sustain signals allocated to one frame.

Claims (16)

A plasma display panel including a scan electrode and a sustain electrode; And A rising period during which a voltage rises to at least one of the scan electrode and the sustain electrode in a sustain period of at least one subfield among a plurality of sub-fields of a frame, a sustain period during which a sustain voltage is maintained, and A driver supplying a sustain signal including a falling period in which a voltage falls; Including, 12. A plasma display apparatus comprising: at least two sustain signals in a continuous supply order, discharges generated in a voltage drop period of a sustain signal preceding the supply sequence and discharges generated in a voltage rise period of another sustain signal; The method of claim 1, And a period of the sustain signal is 2.0 ms to 4.0 ms. The method of claim 1, And a length of the voltage drop period is shorter than a length of the voltage rise period. The method of claim 1, And the voltage rise period has a length of 400 kV to 600 kV. The method of claim 1, And a voltage drop period of 300 mV to 500 mV. The method of claim 1, And the sustain signal is alternately supplied to the scan electrode and the sustain electrode in the sustain period. The method of claim 6, Self Erasing Discharge occurs in a voltage drop period of a first sustain signal among a plurality of sustain signals, And a sustain discharge is generated in succession to the self-erase discharge in the voltage rising period of the second sustain signal consecutive to the first sustain signal. The method of claim 6, And a sustain signal supplied to the scan electrode and a sustain signal supplied to the sustain electrode overlap each other. The method of claim 8, And a length of a period in which the sustain signal supplied to the scan electrode and the sustain signal supplied to the sustain electrode overlap each other is 0.5 times or less the length of the voltage falling period. The method of claim 6, And a sustain signal supplied to the scan electrode and a sustain signal supplied to the sustain electrode do not overlap each other. A plasma display panel including a scan electrode and a sustain electrode; And A rising period during which a voltage rises to at least one of the scan electrode and the sustain electrode in a sustain period of at least one subfield among a plurality of sub-fields of a frame, a sustain period during which a sustain voltage is maintained, and A driver supplying a sustain signal including a falling period in which a voltage falls; Including, And the driver controls the length of the voltage drop period of the sustain signal differently according to the total number of the sustain signals allocated to one frame. The method of claim 11, And a total number of the sustain signals allocated to one frame is determined by an average power level (APL) of an input image. The method of claim 11, When the total number of the sustain signals allocated to one frame is N, the length of the voltage drop period of the sustain signal is the length of the sustain signal when the total number of the sustain signals allocated to one frame is M more than the N number. A plasma display device shorter than the length of the voltage drop period. The method of claim 11, And a period of the sustain signal is 2.0 ms to 4.0 ms. The method of claim 11, And a length of the voltage drop period is shorter than a length of the voltage rise period. The method of claim 11, 12. A plasma display apparatus comprising: at least two sustain signals in a continuous supply order, discharges generated in a voltage drop period of a sustain signal preceding the supply sequence and discharges generated in a voltage rise period of another sustain signal;

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