KR20100063202A - Memory module and memory system having the same - Google Patents

Abstract

PURPOSE: A memory module and a memory system thereof are provided to reduce the capacitive load of a data bus by transmitting and receiving data through at least one memory device from a memory controller. CONSTITUTION: A memory controller(180) transmits write data and command/address signal. A memory module receives write data through data ports. The memory module(100) receives a command address signal through a command/address port. Memory devices(110) of a first set are connected to each data port and the command/address port. Memory devices(120) of a second set receives corresponding write data through the memory device.

Description

MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor memory module and a memory system, and more particularly, to a memory module and a memory system having a plurality of ranks.

In order to improve the performance of the memory system, it is necessary to increase the capacity of the memory module or increase the operating frequency of the memory module. That is, to improve the performance of the memory system, there is a method of increasing the operating frequency of the data bus connected to the memory module and connecting a plurality of memories in parallel to the data bus. However, there is a physical limitation in increasing the operating frequency due to the capacitive load component of the input of the memory connected in parallel to the data bus. Therefore, there is a need for a new method of connecting a plurality of memories to increase the capacity of the memory while reducing the capacitive load effect.

Accordingly, an object of the present invention is to provide a memory module that can reduce the capacitive load effect due to the data bus when used in a memory system having a high operating clock frequency.

Another object of the present invention is to provide a memory system including a plurality of the memory modules.

One object of the present invention is to provide a memory system capable of reducing the capacitive loading effect due to the data bus and the command / address bus.

In order to achieve the above object of the present invention, according to an embodiment of the present invention, the memory module includes a plurality of data ports and a plurality of memory devices. Each of the plurality of data ports receives / transmits corresponding data. The plurality of memory devices are each of a first set of memory devices connected to a corresponding one of the data ports and belonging to at least one rank, and each of the corresponding memory devices of at least the first set of memory devices. And a second set of memory devices belonging to at least one other rank to receive and transmit the corresponding data through.

In an embodiment, the first set of memory devices includes a plurality of first memory devices constituting a first rank, each of the first memory devices being connected to the corresponding data port via a first data bus; And the second set of memory devices includes a plurality of second memory devices constituting a second rank, each of the second memory devices having a corresponding memory of the first memory devices via a second data bus. It is connected to each device, and can receive / transmit the corresponding data through the second data bus.

The second set of memory devices further includes a plurality of third memory devices constituting a third rank and a plurality of fourth memory devices constituting a fourth rank, wherein each of the third memory devices is the first memory device. Each of the first memory devices is connected to a corresponding one of the first memory devices through a second data bus, receives and transmits the corresponding data through the second data bus, and each of the fourth memory devices is connected to the second data bus The first memory device may be connected to each of the corresponding memory devices through the second data bus, and may receive / transmit the corresponding data through the second data bus.

In example embodiments, the first set of memory devices includes a plurality of first memory devices constituting a first rank and a plurality of second memory devices constituting a second rank, each of the first memory devices. Is connected to the corresponding data port via a first data bus, each of the second memory devices is connected to the corresponding data port via a second data bus, and the second set of memory devices constitutes a third rank A plurality of third memory devices and a plurality of fourth memory devices constituting a fourth rank, each of the third memory devices being a corresponding one of the first memory devices through a third data bus; Connected to each other, receiving / transmitting the corresponding data through the third data bus, and transmitting the fourth memo Each of the devices 4 via the data bus being connected to the second memory device corresponding to each of the memory devices, and the fourth is the corresponding data via the data bus to receive / transmit.

In an embodiment, the first set of memory devices includes a plurality of first memory devices constituting a first rank, each of the first memory devices being connected to the corresponding data port via a first data bus; The second set of memory devices may include a plurality of second memory devices constituting a second rank, a plurality of third memory devices constituting a third rank, and a plurality of fourth memory devices constituting a fourth rank. Each of the second memory devices is connected to a corresponding one of the first memory devices via a second data bus, and each of the third memory devices is connected to the second memory via a third data bus. Connected to each of the corresponding memory devices, and the corresponding data device being connected through the third data bus. Receive / transmit data, each of the fourth memory devices is connected to a corresponding one of the third memory devices through a fourth data bus, and receive / transmit the corresponding data through the fourth data bus. I can send it.

The memory device of claim 1, wherein each of the first set of memory devices comprises: a first data pin coupled to each of the corresponding data ports; A second data pin coupled to a first data pin of at least one memory device of the second set of memory devices; And a connection circuit connecting the first data pin and the second data pin to each other.

Each of the first set of memory devices may also include dual input / output buffers.

In order to achieve the above object of the present invention, a memory system according to an embodiment of the present invention includes a memory controller and a memory module. The memory controller transmits write data and a command / address signal. The memory module receives the write data through data ports and the command address signal through a command / address port. The memory module may further include: a set of memory devices each connected to the corresponding respective data port and the command / address port and belonging to at least one rank; And a second set of memory devices, each receiving the corresponding write data through at least a corresponding one of the first set of memory devices and belonging to at least another rank, wherein the second set of memory devices Each of which receives the corresponding command / address signals via at least one memory device of the first set and the second set of other memory devices.

In example embodiments, each of the second set of memory devices may transmit read data corresponding to the memory controller through a corresponding memory device of the first memory devices.

In order to achieve the above object of the present invention, a memory system according to an embodiment includes a plurality of memory modules, each memory module including a plurality of data ports for receiving / transmitting corresponding data; A first set of memory devices each connected to a corresponding one of the data ports and belonging to at least one rank; And a second set of memory devices each belonging to at least another rank for receiving and transmitting the corresponding data through at least one of the first set of memory devices, the first set of memory devices; Each of the devices is connected to a corresponding memory device of another memory module by a corresponding data bus.

The memory system may further include a memory controller, wherein each memory device of the first set of each memory module may receive / transmit the corresponding data through the corresponding data bus.

According to the present invention, it is possible to reduce the capacitive loading effect of the data bus on the side of the memory controller by transmitting and receiving data through at least one memory device without directly transmitting and receiving data from the memory control to the plurality of memory devices.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It should be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present invention, and FIGS. 2A to 2C are block diagrams illustrating a connection relationship between memory devices of a memory module included in FIG. 1.

Referring to FIG. 1, a memory system according to an embodiment of the present invention includes a memory module 100 and a memory controller 180.

The memory module 100 has a multi rank structure. The memory module 100 may include first memory devices 110, that is, M11 111, M12 112, M13 113, and second memory devices 120, that is, M21 121 and M22 122. M23 123, third memory devices 130, that is, M31 131, M32 132, M33 133, and fourth memory devices 140, that is, M41 141, M42 142. , M43 143. The first memory devices 110 constitute a first rank Rank0, the second memory devices 120 constitute a second rank RNK1, and the third memory devices 130 comprise a third rank. (RANK2), and the fourth memory devices 140 constitute a fourth rank (RANK3).

The memory module 100 also includes data ports 151, 152, and 153 and a command / address port 150.

The data ports D1, D2, and D3 of the memory controller 180 are connected to the data ports 151, 152, and 153 of the memory module 100 through the data buses 161, 162, and 163. The command / address port C / A is connected to the command / address port 150 of the memory module 100 through the command / address bus 155. The data ports 151, 152, and 153 of the memory module 100 exchange data with the memory controller 180 through the data buses 161, 162, and 163. That is, the memory module 100 receives the write data WR from the memory controller 180 and transmits (transmits) the read data RD to the memory controller 180.

A connection relationship of a plurality of memory devices in the memory module 100 included in the memory system of FIG. 1 will be described below with reference to FIGS. 2A to 2C.

2A to 2C illustrate a connection relationship between memory devices according to embodiments in the memory module of FIG. 1. 2A through 2C illustrate memory devices 111, 121, 131, and 141 positioned on the same column among memory devices included in the memory module of FIG. 1. Since the memory devices 112, 122, 132, and 142 on the same column are the same as the connection relationship between the memory devices 112, 122, 132, and 142, the memory devices 113, 123, 133, and 143 are omitted. 2A to 2C, memory devices 111, 121, 131, and 141 have eight data pins, but four data pins are used.

Referring to FIG. 2A, in the memory module according to an exemplary embodiment, the memory device 111 belonging to the first rank Rank0 is connected to the data port 151 through the first data bus 171, and the data It is connected to the memory controller 180 of FIG. 1 through the bus 161. Other memory devices 121, 131, and 141 belonging to the second to fourth ranks RANK1, RANK2, and RANK3, respectively, are connected to the memory device 111 through the second data bus 173. That is, the memory devices 121, 131, and 141 are connected to the data port 151 through the memory device 111, and transmit and receive corresponding data through the second data bus 173 and the memory device 111. Here, the data may include write data and read data.

To this end, the memory device 111 includes a connection circuit 115 connecting the first data pin DQ10 and the second data pin DQ14. The second data pin DQ14 of the memory device 111 is connected to the first data pins DQ20, DQ30, and DQ40 of the other memory devices 121, 131, and 141, respectively.

In the embodiment of FIG. 2A, the first set of memory devices corresponds to the first memory devices 110 of FIG. 1, and the second set of memory devices includes the second to fourth memory devices 120 of FIG. 1. 130, 140).

When the memory devices 111, 121, 131, and 141 of the memory module 100 are connected to each other as shown in FIG. 2A, only the first data bus 171 is connected to the memory controller 180 of FIG. 1. The side effect of capacitive loading of the data bus is significantly reduced.

Referring to FIG. 2B, in the memory module according to another exemplary embodiment of the present invention, the memory device 111 belonging to the first rank Rank0 is connected to the data port 141 through the first data bus 171, and the data It is connected to the memory controller 180 of FIG. 1 through the bus 161. In addition, the memory device 131 belonging to the third rank Rank2 is connected to the data port 151 through the second data bus 183, and connected to the memory controller 180 of FIG. 1 through the data bus 161. do. The memory device 121 belonging to the second rank Rank1 is connected to the memory device 111 through the third data bus 185. That is, the memory device 121 is connected to the data port 151 through the memory device 111, and transmits and receives corresponding data through the third data bus 185 and the memory device 111. In addition, the memory device 141 belonging to the fourth rank Rank3 is connected to the memory device 111 through the fourth data bus 187. That is, the memory device 141 is connected to the data port 151 through the memory device 131, and transmits and receives corresponding data through the fourth data bus 187 and the memory device 131.

To this end, the memory device 111 includes a connection circuit 115 connecting the first data pin DQ10 and the second data pin DQ14. The second data pin DQ14 of the memory device 111 is connected to the first data pin DQ20 of the memory device 121. The memory device 131 also includes a connection circuit 135 connecting the first data pin DQ30 and the second data pin DQ34. The second data pin DQ34 of the memory device 131 is connected to the first data pin DQ40 of the memory device 141.

In the embodiment of FIG. 2B, the first set of memory devices corresponds to the first and third memory devices 110, 130 of FIG. 1, and the second set of memory devices includes the second and fourth memory devices ( 120, 140).

Similar to the embodiment of FIG. 2A, when the memory devices 111, 121, 131, and 141 are connected as shown in FIG. 2B, the first data bus 171 and the second data may be different from the memory controller 180 of FIG. 1. Since only the bus 183 is connected, the capacitive loading effect of the data bus on the side of the memory controller 180 is significantly reduced.

Referring to FIG. 2C, in the memory module according to another embodiment of the present invention, the memory device 111 belonging to the first rank Rank0 is connected to the data port 151 through the first data bus 171. It is connected to the memory controller 180 of FIG. 1 through the data bus 161. The memory device 121 belonging to the second rank Rank1 is connected to the memory device 111 through the second data bus 193. The memory device 131 belonging to the third rank Rank2 is connected to the memory device 121 through the third data bus 195. The memory device 141 belonging to the fourth rank Rank3 is connected to the memory device 131 through the fourth data bus 197.

That is, the memory device 121 is connected to the data port 151 through the memory device 111 and transmits and receives corresponding data. The memory device 131 is connected to the data port 151 through the memory devices 111 and 121 and transmits and receives corresponding data. The memory device 141 is connected to the data port 151 through the memory devices 111, 121, and 131 and transmits and receives corresponding data.

To this end, the memory device 111 includes a connection circuit 115 connecting the first data pin DQ10 and the second data pin DQ14. The memory device 121 includes a connection circuit 125 connecting the first data pin DQ20 and the second data pin DQ24. The memory device 131 includes a connection circuit 135 connecting the first data pin DQ30 and the second data pin DQ34. The second data pin DQ14 of the memory device 111 is connected to the first data pin DQ20 of the memory device 121. The first data pin DQ30 of the memory device 131 is connected to the second data pin DQ24 of the memory device 121. The first data pin DQ40 of the memory device 141 is connected to the second data pin DQ34 of the memory device 131.

In the embodiment of FIG. 2C, the first set of memory devices corresponds to the first memory devices 110 of FIG. 1, and the second set of memory devices corresponds to the second to fourth memory devices 120 of FIG. 1. 130, 140).

Similar to the embodiment of FIG. 2A, when the memory devices 111, 121, 131, and 141 are connected as shown in FIG. 2C, only the first data bus 171 is connected to the memory controller 180 of FIG. 1. The capacitive loading effect of the data bus on the side of the memory controller 180 is significantly reduced.

Although not shown in the figures in the embodiments of FIGS. 1 and 2A-2C, data strobe (DQS) signals are also provided to the memory devices simultaneously with the corresponding data via the data buses.

In addition, in the embodiments of FIGS. 1 and 2A to 2C, three ranks of memory devices are included in each rank, but each rank may include the same number of memory devices, and thus the number of memory devices included in each rank is not limited.

3 is a block diagram illustrating a memory system according to another exemplary embodiment of the present invention. FIG. 5 is a schematic internal block diagram of the memory device of FIG. 3.

Referring to FIG. 3, a memory system according to another embodiment of the present invention includes a memory module 200 and a memory controller 270.

The memory module 200 has a multi rank structure. The memory module 200 may include first memory devices 210, that is, M11 211, M12 212, M13 213, second memory devices 220, that is, M21 121 and M22 122. M23 123, third memory devices 230, that is, M31 231, M32 232, M33 233, and fourth memory devices 240, that is, M41 241, M42 242. , M43 (243). The first memory devices 210 make up the first rank Rank0, the second memory devices 220 make up the second rank Rank1, and the third memory devices 230 make the third rank. (RANK2), and the fourth memory devices 240 configure the fourth rank (RANK3).

The memory module 200 also includes data ports 201, 202, 203 and a command / address port 204.

The data ports D1, D2, and D3 of the memory controller 270 are connected to the data ports 201, 202, and 203 of the memory module 200 through the data buses 251, 252, and 253. The command / address port C / A of 270 is connected to the command / address port 1804 of the memory module 200 through the command / address bus 254.

The memory devices 211, 221, 231, and 241 included in the memory module 200 may be connected to the first data bus 261 and the memory device 111, 121, 131, and 141 described with reference to FIG. 2A. Since it is connected to the memory controller 270 through the second data bus 271, a detailed description thereof will be omitted. In addition, the memory devices 212, 222, 232, and 242 also use the memory controller 270 through the first data bus 263 and the second data bus 273 similarly to the memory devices 211, 221, 231, and 241. ). In addition, the memory devices 213, 223, 233, and 243 also use the memory controller 270 through the first data bus 262 and the second data bus 272 similarly to the memory devices 211, 221, 231, and 241. ).

The command / address signal CA provided from the memory controller 270 may include first to fourth command / address signals CA0, CA1, CA2, and CA3. The first command / address signal CA0 is provided to the memory device 211 belonging to the first rank Rank0 through the command / address bus 264. The second command / address signal CA1 is provided to the memory device 221 belonging to the second rank Rank1 through the command / address bus 274. The third command / address signal CA2 is provided to the memory device 231 belonging to the third rank Rank2 through the command / address bus 284. The fourth command / address signal CA3 is provided to the memory device 241 belonging to the fourth rank Rank3 through the command / address bus 294. The first to fourth command / address signals CA0, CA1, CA2, and CA3 may be provided in a packet form.

Referring to FIG. 5, a memory device includes a packet decoder 502, a command decoder 510, an address register 512, a row decoder 514, a column buffer 516, a data input register 520, and a memory array 530. ), Sands amplifier 532, column decoder 518, mode register 570, latency & burst length adjuster 564, prefetching unit 540, data buffer 542, output buffer 560, input And a buffer 562 and a repeater 550.

3 and 5, a first command / address signal CA0 is first input to the memory device 211 through the command address bus 264. The first command / address signal CA0 may include a data write command, a data read command, and address information. The first command / address signal CA0 may be in the form of a packet.

The command / address signal CA0 is inputted to the packet decoder 502 in the memory device 211, and is read-restored by the repeater 550 in the memory device 211 after a predetermined time delay. CAr is retransmitted to memory devices 212 and 213 via command / address buses 266 and 265.

Here, the command / address signal may have a packet form including an operand and address information indicating an instruction word type such as a write command and a read command. That is, the command / address signal may be transmitted in a packet through the command / address buses 254 and 264. The command / address signal is uni-directionally transmitted over the command / address buses 254 and 264.

Although not shown, a command / address clock signal is also provided from the memory controller 270 to the memory device 211 through a command / address bus, and then read-dried by the repeater 250 in the memory device 211 to store another memory in the same rank. May be retransmitted to the devices 212, 213.

Similarly, the second command address signal CA1, which is provided directly to the memory device 221, is redriven by the repeater 550 (see FIG. 5) in the memory device 221, so that the command address bus 275, 276 is retransmitted to other memory devices 223 and 222 in the second rank Rank1.

Similarly, the third command address signal CA2 provided directly to the memory device 231 is redriven by the repeater 550 (see FIG. 5) in the memory device 231 to be command-driven bus 285. Via 286 it is retransmitted to the other memory devices 233, 232 in the third rank (RANK2).

Similarly, the third command address signal CA3 provided directly to the memory device 241 is redriven by a repeater 550 (see FIG. 5) in the memory device 241 to command command bus 295. Via 296 it is retransmitted to other memory devices 243 and 242 in the fourth rank (RANK3).

For example, the memory devices 211, 221, 231, and 241 may each have the block configuration of FIG. 5.

In the memory device 211, the repeater 550 is active while repeating the first command / address signal CA0, and the repeater 550 is not active while not repeating the command / address signal CA0.

FIG. 5 illustrates an example of an internal block of a memory device composed of nxm memory cells, and embodiments of the present invention are not limited to the internal block configuration of the memory device shown in FIG. 5, and include a repeater having a command / address bypass path. The memory device may be applied to a memory device having a structure in which the internal block of FIG. 5 is modified.

In the embodiment of FIG. 3, three memory devices are included in each rank, but each rank may include the same number of memory devices, and thus the number of memory devices included in each rank is not limited.

4 is a block diagram illustrating a memory system according to another exemplary embodiment of the present invention.

Referring to FIG. 4, a memory system according to another embodiment of the present invention includes a memory controller 360, a first memory module 300, and a second memory module 400. Like the memory module 200 of FIG. 3, the first and second memory modules 300 and 400 may each include a plurality of memory devices M11, M12, M13, M21, M22, M23, M31, M32, M33, and M41. , M42, M43).

The data ports D1, D2, and D3 of the memory controller 360 are connected to the data ports 341, 342, and 343 of the first memory module 300 through the data buses 311, 312, and 313, respectively. 2 are connected to the data ports 441, 442, and 443 of the memory module 400, respectively. In addition, the command / address port C / A of the memory controller 360 is connected to the command / address port 350 of the first memory module 300 and the second memory module 400 through the command / address bus 314. It is connected to the command / address port 450.

In FIG. 4, although the first memory module 300 and the second memory module 400 are connected to the memory controller 360 through the same data buses and the command / address bus, the first memory module 300 and the second memory are connected to each other. Module 400 may be coupled to memory controller 360 via separate data buses and command address bus.

Memory modules having memory devices having a connection relationship of FIGS. 2A to 2C may be employed in the first and second memory modules 300 and 400 of FIG. 4, respectively. In addition, the memory module 200 of FIG. 3 may be employed in the first and second memory modules 300 and 400 of FIG. 4, respectively. Therefore, detailed descriptions of the first and second memory modules 300 and 400 of FIG. 4 will be omitted.

A memory module and a memory system including the same according to embodiments of the present invention transmit and receive data through at least one memory device without directly transmitting and receiving data from the memory control to the plurality of memory devices, thereby providing a data bus at the side of the memory controller. It can reduce the capacitive loading effect of. In addition, the memory controller provides a command / address signal to a specific memory device instead of providing all the memory devices in the memory module, and the specific memory device retransmits the command / address signal to other memory devices in the memory module. As a result, capacitive loading effects due to conventional command / address signals can be reduced.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 is a block diagram illustrating a memory system according to an example embodiment.

2A through 2C are block diagrams illustrating a connection relationship between memory devices of a memory module included in FIG. 1.

3 is a block diagram illustrating a memory system according to another exemplary embodiment of the present invention.

4 is a block diagram illustrating a memory system according to another exemplary embodiment of the present invention.

FIG. 5 is a schematic internal block diagram of the memory device of FIG. 3.

Claims (11)

A plurality of data ports each receiving / transmitting corresponding data; And A first set of memory devices each connected to a corresponding data port of the data ports and belonging to at least one rank, and each of the corresponding data through at least a corresponding memory device of the first set of memory devices; And a plurality of memory devices having a second set of memory devices belonging to at least one other rank of receiving and transmitting. The method of claim 1, The first set of memory devices includes a plurality of first memory devices constituting a first rank, each of the first memory devices being connected to the corresponding data port via a first data bus; The second set of memory devices includes a plurality of second memory devices constituting a second rank, each of the second memory devices each corresponding memory device of the first memory devices via a second data bus. And receive / transmit the corresponding data through the second data bus. The method of claim 2, The second set of memory devices further includes a plurality of third memory devices constituting a third rank and a plurality of fourth memory devices constituting a fourth rank, Each of the third memory devices is connected to each of the corresponding memory devices of the first memory devices through the second data bus, and receives / transmits the corresponding data through the second data bus. Each of the fourth memory devices is connected to each of the corresponding memory devices of the first memory devices through the second data bus, and receives / transmits the corresponding data through the second data bus. Memory modules. The method of claim 1, The first set of memory devices includes a plurality of first memory devices constituting a first rank and a plurality of second memory devices constituting a second rank, each of the first memory devices having a first data bus. Connected to the corresponding data port through a second data device, and each of the second memory devices is connected to the corresponding data port through a second data bus, The second set of memory devices includes a plurality of third memory devices constituting a third rank and a plurality of fourth memory devices constituting a fourth rank, each of the third memory devices comprising a third data bus. Connected to each of the corresponding memory devices of the first memory devices through the third data bus, and receiving / transmitting the corresponding data through the third data bus, and each of the fourth memory devices through the fourth data bus. A memory module connected to each of the corresponding memory devices among the second memory devices, and receiving / transmitting the corresponding data through the fourth data bus. The method of claim 1, The first set of memory devices includes a plurality of first memory devices constituting a first rank, each of the first memory devices being connected to the corresponding data port via a first data bus; The second set of memory devices includes a plurality of second memory devices constituting a second rank, a plurality of third memory devices constituting a third rank, and a plurality of fourth memory devices constituting a fourth rank. and, Each of the second memory devices is connected to a corresponding one of the first memory devices through a second data bus, and each of the third memory devices is connected to one of the second memory devices via a third data bus. A memory device connected to each of the corresponding memory devices, and receiving / transmitting the corresponding data through the third data bus, wherein each of the fourth memory devices is a corresponding memory device of the third memory devices through a fourth data bus. Memory modules connected to each other to receive / transmit the corresponding data through the fourth data bus. The method of claim 1, Each of the first set of memory devices, A first data pin coupled to each of the corresponding data ports; A second data pin coupled to a first data pin of at least one memory device of the second set of memory devices; And And a connection circuit connecting the first data pin and the second data pin to each other. The method of claim 6, Each of said first set of memory devices comprises dual input / output buffers. A memory controller for transmitting write data and a command / address signal; And A memory module for receiving the write data through data ports and the command address signal through a command / address port, wherein the memory module includes: A set of memory devices each connected to each corresponding respective data port and the command / address port and belonging to at least one rank; And A second set of memory devices, each receiving the corresponding write data through at least a corresponding one of the first set of memory devices and belonging to at least another rank, wherein the second set of memory devices Each receiving the corresponding command / address signals via at least one memory device of the first set and the second set of other memory devices. The memory system of claim 8, wherein each of the second set of memory devices transmits read data corresponding to the memory controller through a corresponding one of the first memory devices. A plurality of memory modules, each memory module, A plurality of data ports each receiving / transmitting corresponding data; A first set of memory devices each connected to a corresponding one of the data ports and belonging to at least one rank; And Each having a second set of memory devices belonging to at least another rank that receives and transmits the corresponding data through at least one of the first set of memory devices; Each of the first set of memory devices is connected to a corresponding memory device of another memory module by a corresponding data bus. 11. The apparatus of claim 10, further comprising a memory controller, Wherein each memory device in the first set of each memory module receives / transmits the corresponding data via the corresponding data bus.

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