JP5388406B2 - Memory system - Google Patents

Description

The present invention relates to a memory system formed by connecting a plurality of memory modules on which DRAM or the like is mounted.

  In recent years, with the improvement of semiconductor technology, the operating frequency inside processors and LSIs has increased dramatically, and the operating frequency has been improved even for memories connected to the outside of LSIs, especially for main memory devices using DRAM. Therefore, the speed of memory modules is increasing.

  A memory system composed of a plurality of memory modules also needs to be changed in structure and configuration as the speed increases. Conventionally, in a memory system configured with a memory module corresponding to a standard such as PC 133, even if unbuffered, signals output from the controller for both commands and data are distributed to the memory modules in the memory system as they are, and no problem occurs. .

  However, in a memory system configured by using a plurality of memory modules corresponding to a standard such as DDR400 that realizes further speedup, when command-related signals are distributed and supplied to many memory modules, The load increases and the signal propagation delay increases. In such a case, high-speed operation cannot be guaranteed with an unbuffered memory system configuration, so command signals are latched and distributed by registers mounted in each memory module to reduce signal load on the board and achieve high-speed operation. Guaranteed. At this time, the data has a smaller signal load on the substrate than the command system signal, so the influence on the high-speed operation is small.

  However, if a memory system using a memory module that can realize further higher speeds such as DDR2 and DDR3 is constructed, the load on the substrate due to the distribution of the data signal cannot be ignored, which affects high-speed operation.

  As a mechanism for guaranteeing this high-speed operation, as shown in FIG. 6, a method that transmits commands and data conforming to the DRAM protocol from the memory control circuit to the memory module using a high-speed serial interface technology of Point to Point is considered. (For example, Patent Document 1). This mechanism is a mechanism in which a buffer is provided in the memory module, and commands and data are once buffered and transmitted. Hereinafter, the operation of the memory module in the mechanism will be described.

  A command issued from the memory control circuit 601 is transmitted to the first memory module 602, and then sequentially transmitted to the memory module 603 and the memory module 604. In this case, the inside of each of the memory modules 602, 603, and 604 has a structure as shown in FIG.

  The memory module 602 includes memory devices 801, 802, 804, and 805 serving as cores of the memory module, and a buffer 803 for once buffering commands and data transmitted from the memory control circuit 601. The buffer 803 in the memory module determines whether the transmitted command or data is an access to its own memory module or an access to another module. Note that the memory modules 603 and 604 are configured in the same manner as described above.

  At this time, if the buffer 803 determines that the access is to the own module (that is, the memory module 602 to which the buffer 803 belongs), the command is distributed to the DRAMs 801, 802, 804, and 805 in the memory module 602. Further, when it is determined that the access is to another module (that is, the memory module 603 or the like), the access to the own module is not performed, but is transmitted to the next module (memory module 603). At this time, the write data is transmitted together with the command, and the read data is transmitted to the memory control circuit 601 side opposite to the command via the buffer 803.

JP 2006-065697 A

  In the configuration shown in FIG. 6, memory modules 602, 603 and 604 corresponding to the same protocol are connected in cascade to constitute a circuit. Therefore, when connecting another ROM module 606 treated as a different protocol, or a memory module 605 such as an SRAM, for example, a connection port different from that of the memory modules cascade-connected to the memory control circuit 601 is provided to connect the modules. There was a need. Therefore, when configuring the memory system, there is a problem that the number of wiring connections increases and the number of pins used for connection increases.

  Further, since a large number of pins are required for wiring connection, the system configuration depends on the configuration of the memory control circuit 601, and there is a problem that the number of pins increases and the system configuration is restricted.

  Further, as shown in FIG. 7, there is a problem similar to the above even when the connection from the memory control circuit 701 to the memory modules 702, 703 and 704 and another memory module 705 having different protocols are connected in parallel. That is, there is a problem that the wiring performance from the memory control circuit 701 is deteriorated, and similarly, memory modules having different speeds and protocols need to be connected in parallel, so that the memory access performance is lowered.

  The present invention has been made in view of the actual situation, and an object thereof is to provide a memory system in which a plurality of memory modules corresponding to different access commands are cascade-connected with a simple configuration while guaranteeing the operation thereof. To do.

The memory system of the present invention includes: a memory control means for issuing an access command, the buffer portion to which the access command with buffers receives an access command from said memory control means determines whether the access to memory device a plurality of memory modules comprising a has a memory unit are cascade-connected, and the memory unit, the latency is greater than the RAM contained a ROM included in the plurality of memory modules in said plurality of memory modules It is characterized by being cascade-connected .

The memory system of the present invention can be easily configured while guaranteeing the operation when a plurality of memory modules are cascade-connected .

  Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the memory system 100 according to the embodiment of the present invention is configured by cascade-connecting three sets of memory modules 102 to 104 (hereinafter referred to as RAM) and a ROM module 105 to a memory control circuit 101. Is done.

  At this time, the latency for the memory module 102 having the shortest physical distance from the memory control circuit 101 is the smallest and the latency for the ROM module 105 having the longest physical distance is the largest.

  As shown in FIG. 2, each of the RAMs 102 to 104 temporarily buffers memory devices 201, 202, 204, and 205 (hereinafter referred to as DRAM) and access commands and data transmitted from the memory control circuit 101. And a buffer 203.

  As shown in FIG. 3, the ROM module 105 includes memory devices 301 and 302 (hereinafter referred to as ROM) and a buffer for temporarily buffering access commands and data transmitted from the memory control circuit 101. 303.

  In the memory system 100 of this embodiment, when an access command or data is transmitted, first, a common access command or data (including both access data and data) is received from the memory control circuit 101 shown in FIG. The data is input to a buffer 203 built in the RAM 102. The buffer 203 temporarily buffers the input common access command or data, and determines whether the common access command or data is an access to the DRAM 201 or the like built in the RAM 102 to which the buffer 203 belongs. .

  If the buffer 203 determines that the access command is an access to the DRAM 201 or the like built in the RAM 102 to which the buffer 203 belongs, the access command that can be recognized by the DRAMs 201, 202, 204, and 205 is distributed to each.

  On the other hand, when the buffer 203 determines that the access command is an access to another RAM or the like (for example, the RAM 103), the access command is transmitted to the next cascaded RAM 103. The write data is transmitted together with the access command.

FIG. 4 shows a configuration example of the protocol conversion circuit 401 that converts a common access command into an access command that can be recognized by each memory device. Memory modules RAM 10 2 or the like constituting a memory system 100 according to this embodiment has the protocol conversion circuit 401 into each of the buffer 203.

  The protocol conversion circuit 401 includes a command decode circuit 402 that decodes a common command, and a memory device control circuit 403 that controls a memory device 404 including a DRAM connected to the protocol conversion circuit 401. The Here, the memory device 404 corresponds to, for example, the DRAM 201 in FIG. A hierarchy including the command decode circuit 402 and the memory device control circuit 403 is built in the buffer 203 in FIG. 2, the buffer 303 in FIG.

  The operation in the memory module when the protocol conversion circuit 401 is provided will be described below. First, the operation of the protocol conversion circuit 401 when the common access command conforms to the DRAM protocol will be described.

The command decode circuit 402 causes the memory device control circuit 403 to grasp the protocol by decoding the common access command.

  The memory device control circuit 403 generates an access command that can be recognized by the memory device 404 in order to generate an access command that can be recognized by the memory device 404.

  Here, if the protocol of the DRAM, which is a common access command, and the protocol required after conversion of the access command are the same DRAM protocol, the protocol conversion circuit 401 does not need to convert the protocol. In that case, a common access command can be used as it is as an access command to the memory device 404.

  In the case of FIG. 1, the RAMs 102, 103, and 104 are configured by the DRAM 201 and the like, and the ROM module 105 is configured by the ROM 301 and the like. The access command can be transmitted to the DRAM as it is.

  On the other hand, in the buffer 303 mounted in the ROM 105, the received common access command is converted into a ROM access command by the built-in protocol conversion circuit 401 and transmitted to the ROMs 301 and 302.

  Here, a case will be described in which a common access command (which conforms to the protocol of the DRAM) is converted into access commands for the ROMs 301 and 302. In a common access command, it is assumed that RowAddress and ColumnAddress are set as Address, and either Write / ReadCommand is used as Command.

  The protocol conversion circuit 401 generates Address as an access command and data that can be recognized by the memory device 404 (that is, the ROM 301 or the like) from RowAddress and ColumnAddress input to the command decoding circuit 402. Similarly, the Write / Read command of the common access command is converted into a Write / Read compatible command of the ROM device. At this time, it does not correspond to a command depending on a protocol peculiar to DRAM such as Pre-charge or refresh.

  As described above, the memory system 100 includes the protocol conversion circuit 401 that can convert a common access command or the like into an access command or the like corresponding to a memory device built in the module in the buffer of each memory module constituting the memory system 100. Provided. Thus, a memory system in which a plurality of memory modules corresponding to different access commands (in other words, memory modules having different access latencies) are cascade-connected can be easily configured without causing a problem in operation. In other words, since cascade connection is possible while guaranteeing operation, the number of connection ports, the number of wiring connections, and the number of pins used for connection, which have been problematic when using multiple memory modules corresponding to different access commands in the past, are increased. The memory system can be realized with a simple structure.

  In this embodiment, the memory system 100 includes the RAMs 102 to 104 and the ROM module 105. However, the number of modules is not limited, and the number of memory devices built in the memory module is also limited. It is not limited. Also in the memory system configured by cascading the memory modules 502 (RAM B) corresponding to different access commands as shown in FIG. 5 and the RAMs 102 to 104 shown in FIG. 1, a protocol is assigned to each memory module. By providing the conversion circuit 401, a suitable memory system can be realized.

  In the present embodiment, the protocol conversion circuit 401 is built in the buffer unit included in each memory module. However, the present invention is not limited to this, and the protocol conversion circuit 401 may be configured as a circuit independent of the buffer unit.

  Further, in this embodiment, the common command is the DRAM protocol, but even if the common command is a protocol other than the DRAM, by incorporating the protocol conversion circuit 401 in the buffer unit of each memory module, Can be matched.

  Further, even when various memory modules are combined or when the cascade connection order is changed, the embodiment can be suitably implemented without being restricted by the present embodiment.

It is a figure which shows the structure of the memory system which concerns on embodiment of this invention. It is a figure which shows the structure of the memory module which concerns on embodiment of this invention. It is a figure which shows the structure of the memory module which concerns on embodiment of this invention. It is a figure which shows the structure of the conversion circuit which the memory module which concerns on embodiment of this invention has. It is a figure which shows the structure of the modification of the memory module which concerns on embodiment of this invention. It is a figure which shows the structure of the conventional memory system. It is a figure which shows the structure of the conventional memory system. It is a figure which shows the structure of the conventional memory module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory system 101 Memory control circuit 102, 103, 104 Memory module 105 ROM module 201, 202, 204, 205 Memory device (DRAM)
203 Buffer 301, 302 Memory device (ROM)
303 Buffer 401 Protocol Conversion Circuit 402 Command Decode Circuit 403 Memory Device Control Circuit 404 Memory Device 502 Memory Module

Claims (6)

Memory control means for issuing an access command;
Said memory unit access command is a plurality of memory modules comprising a buffer unit for determining whether access to the memory devices are cascaded together to buffer receives an access command from the memory control unit, the Have
The memory system is characterized in that the ROM included in the plurality of memory modules is cascade-connected so that the latency is larger than that of the RAM included in the plurality of memory modules . When the buffer unit determines that the received access command is an access to a memory device in the memory module to which the buffer unit belongs, the buffer unit converts the access command into an access command that can be recognized by the memory device in the memory module to which the buffer unit belongs. The memory system according to claim 1, further comprising a conversion circuit that performs the conversion. The buffer unit, when determining that the access command is not an access to a memory device in a memory module to which the buffer unit belongs, transmits the access command to another memory module. 3. The memory system according to 1 or 2 . At least one of said cascaded plurality of memory modules, one of the claim 1-3, characterized in that it comprises a memory device corresponding to the different access commands and data from the memory device having the other memory modules The memory system according to claim 1 . Memory system according to any one of claims 1 to 4, characterized in that said access command memory module receives are those conforming to the DRAM protocol. The memory system according to claim 2 , wherein the conversion circuit is built in the buffer unit.

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