KR20100054481A - Method for cache read of non volatile memory device - Google Patents

Abstract

The cached method of the nonvolatile memory device of the present invention is provided with a nonvolatile memory device including a plurality of page buffers including a first register and a second register, respectively, and a first address is input according to a read command. Storing the first address in the address register, performing a read operation on the page according to the first address, inputting an address change value, and receiving the first address according to a cache read command. Summing the address change value to store the second address as a second address, and performing a cache read operation using the page according to the second address as a start page.

Description

Method for cache read of non volatile memory device

The present invention relates to a cached method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

A nonvolatile memory device typically includes a memory cell array in which cells in which data is stored is formed in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in the specific cell. The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling whether the specific bit line and the sensing node is connected.

Among the read methods of the nonvolatile memory device, a cache read method is known to reduce the time required for the read operation. When each page buffer includes two registers, one register performs a read operation, and the other register performs an operation of outputting already read data to the outside.

However, when repeatedly performing such a cache read method, the start page of the cache read is increased by only one page, thereby limiting its use.

An object of the present invention is to provide a cache read method of a nonvolatile memory device capable of changing a start page of a cache read to a value of various states.

The cached method of the nonvolatile memory device of the present invention for solving the above problems is provided with a step of providing a nonvolatile memory device including a plurality of page buffers each comprising a first register and a second register, Accordingly, a first address is input, a first address is stored in an address register, a read operation is performed on the page according to the first address, an address change value is input, and a cache read And adding the address change value to the first address according to an instruction and storing the changed address as a second address, and performing a cache read operation using the page by the second address as a start page.

According to the above-described problem solving means of the present invention, the start page may be changed to various values in performing the cache read operation. This can reduce the address cycling time and the read time which are unnecessary drawing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a view for explaining a cache read operation of a conventional nonvolatile memory device.

The nonvolatile memory device 100 may include a memory cell array 110 including a plurality of page unit memory cells, a page buffer unit 120 including a plurality of page buffers including two different registers, and data. It includes an input and output unit 130 for input and output.

The memory cell array 110 includes a plurality of memory cells in a page unit that is a unit of a program operation or a unit of a read operation.

The page buffer unit 120 includes a plurality of page buffers connected to each memory cell to temporarily store data. In this case, each page buffer includes a first register 122 and a second register 124 that store data.

The cache read operation will be described. Unlike normal read operations, the cache read operation requires two different data stores for each page buffer.

First, a read operation is performed on the first page, and the read data is stored in the first register of each page buffer (S10).

Next, the first page data stored in the first register is output to the outside, and a read operation is performed on the second page, and the read data is stored in the second register of each page buffer (S20). In this manner, the data output operation and the read operation can be performed simultaneously, thereby reducing the time required for the read operation.

Similarly, while reading the second page data stored in the second register to the outside, a read operation is performed on the third page, and the read data is stored in the first register of each page buffer (S30).

However, in the normal cache read operation, each page can be increased by only one page, and thus its use is limited.

2 is a diagram showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 200 may include a memory cell array 202, a page buffer 208, an X / Y-decoder 204 and 206, a high voltage generator 210, a command interface logic unit 212, and a command register ( 214, an address register / counter 216, a data register 218, and an IO buffer unit 220. An operation of the nonvolatile memory device will be described.

First, when the chip enable signal / CE is activated with respect to the command interface logic unit 212 and the write enable signal / WE is toggled, the command interface logic unit 212 may respond in response thereto. The command signal received through the IO buffer unit 210 and the command register 214 is received, and a program command, an erase command, a read command, etc. are generated according to the command. In this case, the command signal includes a page program setup code for determining an operation mode of the nonvolatile memory device. Meanwhile, the operation state signal R / B output from the command interface logic unit 212 is disabled for a predetermined time, and an external memory controller (not shown) receives the operation state signal R / B. Recognize that the nonvolatile memory device is in an operating state such as program / erase / read. That is, during the time when the operation state signal R / B is disabled, program / erase / read of one page of the memory cell array is executed.

In addition, the address register / counter 216 receives an address signal received through the IO buffer unit 220 and generates a row address signal and a column address signal. The address signal corresponds to one of pages included in one of the memory cells. The data register 118 temporarily stores various data received through the IO buffer unit 220 and transfers the data to the Y-decoder 206.

The high voltage generator 210 generates bias voltages in response to the program command, erase command or read command and supplies them to the page buffer 208, the X-decoder 204, and the like.

The X-decoder 204 supplies the bias voltages supplied from the high voltage generator 210 to one of the blocks of the memory cell array to the memory cell array 202 in response to the row address signal. The Y-decoder 206 supplies a data signal to bit lines (not shown) shared by the blocks of the memory cell array through the page buffer in response to the column address signal.

The page buffer 208 latches a data signal received through the IO buffer unit 210 and the Y-decoder 206 to bit lines (not shown) shared by the blocks of the memory cell array. Output

3 is a flowchart illustrating a cache read method of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 4 is a timing diagram illustrating a cache read operation of the nonvolatile memory device according to an embodiment of the present invention. .

First, a read start command '00h' for performing a normal read operation is input through an I / O buffer of a nonvolatile memory device (step 310). In the state where the chip enable signal / CE is activated, the command is input during the period in which the instruction latch enable signal CLE is activated.

Next, a first address indicating a cell to perform a read operation is input (step 312). During the period in which the address latch enable signal ALE is activated, an address is input over a total of five cycles. The first address includes a column address, a row address, and the like of a cell to be read.

Next, the input first address is stored in the address register 216 or the like (step 314).

Next, a command 30h for confirming the read operation is input (step 316). The command 30h is input during the period in which the command latch enable signal CLE is activated. In response to the input of the command, the operation state signal R / B is activated, and a read operation is performed on the cells of the input address (step 318).

Next, a page address variation value is input (step 320).

Before performing the cache read operation, the page address is increased or decreased by one or more according to the variation value. In the related art, only a function of increasing by one is performed, but in the present invention, an additional value (offset) is received and the page address is increased or decreased by the corresponding value. Preferably, the change value for the row address is input.

Next, the cache read start command 31h is input (step 322). The command 31h is input during the period in which the command latch enable signal CLE is activated. Before performing the cache read operation according to the cache read command, the input address change value is added to the first address stored in the step 314 (step 324), and the second address which is the summed address value is stored in the address register. (Step 326).

Then, the cache read operation is performed from the second address (step 328). The cache read operation is performed using the second addressed page as a start page. Since the second address value is determined by the fluctuation value, unlike the related art, a plurality of pages may be the start page of the cache read operation.

After performing the cache read operation (step 330), if the cache read operation is further performed, a new address change value is received and the steps 320 to 330 are repeatedly performed. That is, the cache read operation is performed by adding the address variation value to the value stored in the address register in the previous cache read operation.

If the cache read operation is completed, the operation ends (step 330).

FIG. 5 is a diagram illustrating an address variation value during a cache read operation of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 6 is a cache read operation of a nonvolatile memory device according to an embodiment of the present invention. It is a figure which shows the fluctuation state of an address at the time.

The address shift value is composed of 8 bits of data, one bit of which is used as a sign bit, and the remaining bits represent the change value. The increase or decrease is determined according to the sign bit, and the amount to be changed according to the remaining bits. Therefore, the target page of the cache read operation may be changed in the range of -128 to +127.

Referring to FIG. 6, assuming that a cache read operation is performed on N pages, a cache read target page may be changed from N-128 pages to N + 127 pages. As a result, unlike FIG. 1, a plurality of pages that are a target of a cache read operation may be provided.

7 is a diagram illustrating an address change process during a cache read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

The first address is stored in the address register during a normal read operation or a previous cache read operation. The address change value is then input and summed with the first address, which becomes the second address. The second address becomes a start page of a cache read operation.

As described above, the start page of the cache read operation may be changed in various forms by receiving an address change value.

1 is a view for explaining a cache read operation of a conventional nonvolatile memory device.

2 is a diagram showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

3 is a flowchart illustrating a cache read method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 is a timing diagram illustrating a cache read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating an address change value during a cache read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a change state of an address during a cache read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

7 is a diagram illustrating an address change process during a cache read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Claims (5)

Providing a nonvolatile memory device including a plurality of page buffers each including a first register and a second register; Inputting a first address according to a read command; Storing the first address in an address register; Performing a read operation on the page according to the first address; Inputting an address change value, Adding the address change value to the first address according to a cache read command and storing the changed address value as a second address; And performing a cache read operation using the second addressed page as a start page. The cache read method of claim 1, wherein the address change value has a value of −128 to +127. The cache read method of claim 1, wherein the address change value is 8 bits of binary data. The method of claim 1, wherein the performing of the read operation on the page by the first address is performed. And performing a read operation on a page specified by a row address included in the first address. The method of claim 1, wherein the performing of the cache read operation using the second addressed page as a start page comprises: And performing a read operation on a page specified by a row address included in the second address.

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