KR20100050730A - Flash memory device and method of drviing the same - Google Patents

Abstract

PURPOSE: A flash memory device and a method of driving the same are provided to over erase by combing a memory cell and a select transistor. CONSTITUTION: Source region(510) and drain regions(521,522) are formed on a substrate(100). A first channel region(CH1) is formed between the source region and the drain region. The second channel region(CH2) is formed on the side wall of the first channel region. A charge trap part(210) corresponds to the first channel region. Gate electrodes(310,320) are arranged on the first channel region and the second channel region. Spacers(331,332) are formed on the side of first and second gate electrodes.

Description

Flash memory device and driving method thereof {FLASH MEMORY DEVICE AND METHOD OF DRVIING THE SAME}

The embodiment relates to a flash memory device and a driving method thereof.

As information processing technology develops, highly integrated flash memory devices have been developed. In particular, flash memory devices having a SONOS structure have been developed.

Such flash memory devices may include a select transistor to prevent over erase. However, the flash memory device further includes a select transistor, so that high integration is difficult.

The embodiment provides a flash memory device capable of high integration and preventing over erasure and a driving method thereof.

In an embodiment, a flash memory device may include: a source region and a drain region spaced apart from each other on a substrate; A first channel region formed between the source region and the drain region; A second channel region formed between the source region and the drain region and formed on a side surface of the first channel region; A charge trap unit corresponding to the first channel region; And a gate electrode disposed on the first channel region and the second channel region.

A method of manufacturing a flash memory device according to an embodiment may include: injecting hot electrons into the charge trap unit and programming the same; And injecting hot holes into the charge trap unit to erase the hot holes.

The flash memory device according to the embodiment includes a first channel region and a second channel region, and a gate electrode is disposed on the first channel region and the second channel region.

Therefore, the flash memory device according to the embodiment has a structure in which a memory cell and a select transistor are combined. Accordingly, the flash memory device according to another embodiment may reduce over erasure.

In addition, the flash memory device according to the embodiment can drive the select transistor and the memory cell by using one gate electrode, and has an improved degree of integration.

In addition, the flash memory device according to the embodiment may program and erase hot electrons and hot holes by injecting them into the charge trap unit. Therefore, the flash memory device according to the embodiment can be driven in the form of NOR, and thus high integration can be achieved.

In the description of the embodiment, each panel, part, chassis, sheet, plate, or substrate is formed on or under the "on" of each panel, part, chassis, sheet, plate, or substrate, and the like. When described as being "in" and "under" includes both those that are formed "directly" or "indirectly" through other components. In addition, the upper or lower reference of each component is described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 to 7 are cross-sectional views illustrating processes of a method of manufacturing a flash memory device having a SONOS structure according to an embodiment.

Referring to FIG. 1, an isolation layer 110 is formed on a semiconductor substrate 100, and an active region is defined inside the isolation layer 110. Thereafter, a low concentration of n-type impurities is implanted into the active region to form an n-type well 120.

Referring to FIG. 2, after the n-type well 120 is formed, a tunnel oxide film 201, a nitride film 202, and a buffer layer 203 are formed on the semiconductor substrate 100.

The tunnel oxide film 201 is formed to a thickness of about 50 to 80 kPa by a thermal oxidation process, and the nitride film 202 is formed to a thickness of about 70 to 100 kPa by a CVD (chemical vapor deposition) process. Examples of the material used for the nitride film 202 include silicon nitride (SiNx) and the like.

The buffer layer 203 is formed on the nitride film 202, and examples of the material used as the buffer layer 203 include silicon oxide (SiOx).

In addition, a high K material such as aluminum oxide may be deposited between the tunnel oxide film 201 and the nitride film 202.

As a result, an ONO film 200a having an oxide film-nitride film-oxide film structure is formed on the semiconductor substrate 100. In this case, the ONO film 200a may be patterned by a mask process.

Thereafter, a sacrificial vertical structure SVS is formed on the buffer layer 203. Examples of the material used as the sacrificial vertical structure SVS include nitride or oxide.

The sacrificial vertical structure SVS may be formed to have a height of about 3000 to 4000 mm.

Referring to FIG. 3, after the sacrificial vertical structure SVS is formed, a silicon nitride layer is formed on the semiconductor substrate 100, and the silicon nitride layer is etched by an anisotropic etching process such as an etch back process.

Accordingly, first and second sacrificial spacers SS1 and SS2 are formed on side surfaces of the sacrificial vertical structure SVS. The first and second sacrificial spacers SS1 and SS2 are symmetrical with each other with the sacrificial vertical structure SVS interposed therebetween.

Since the first and second sacrificial spacers SS1 and SS2 are formed by an anisotropic etching process, the first and second sacrificial spacers SS1 and SS2 have substantially the same size. In more detail, bottom surfaces of the first and second sacrificial spacers SS1 and SS2 have the same width.

Thereafter, the ONO layer 200a is patterned using the first and second sacrificial spacers SS1 and SS2 and the sacrificial vertical structure SVS as a mask. That is, portions of the ONO layer 200a in which the first and second sacrificial spacers SS1 and SS2 and the sacrificial vertical structure SVS are not disposed are etched.

Referring to FIG. 4, the first and second sacrificial spacers SS1 and SS2 are removed. In this case, portions of the buffer layer 203 disposed under the first and second sacrificial spacers SS1 and SS2 are removed together.

Thereafter, an insulating film 204 is formed on the semiconductor substrate 100 by a CVD process. Examples of the material used for the insulating film 204 include silicon oxide and the like. The insulating layer 204 is also formed on the side and top of the sacrificial vertical structure SVS.

Referring to FIG. 5, a polysilicon layer is formed on the insulating film 204. The polysilicon layer is etched by an anisotropic etching process such as an etch back process, and first and second gate electrodes 310 and 320 are formed on side surfaces of the sacrificial vertical structure SVS.

The first and second gate electrodes 310 and 320 are disposed on the nitride film 202 and are disposed on the side surface of the nitride film 202. The first and second gate electrodes 310 and 320 are symmetrical to each other.

In addition, the first and second gate electrodes 310 and 320 have substantially the same size because they are formed by an anisotropic etching process.

Referring to FIG. 6, after the first and second gate electrodes 310 and 320 are formed, the sacrificial vertical structure SVS is removed.

Thereafter, the buffer layer 203, the nitride layer 202, and the tunnel oxide layer 201 are patterned using the first and second gate electrodes 310 and 320 as masks.

Accordingly, the first charge trap unit 210 including the first tunnel oxide layer 201a, the first charge trap layer 202a, and the first insulating layer 204a is formed on the semiconductor substrate 100. At the same time, a second charge trap unit 220 including a second tunnel oxide film 201b, a second charge trap layer 202b, and a second insulating film 204b is formed.

Thereafter, low concentrations of p-type impurities are implanted into the sides of the first and second gate electrodes 310 and 320 to form LDD regions 410 and 420, and the first and second gate electrodes 310 are formed. , A high concentration of p-type impurities are implanted in the region between the first and second regions 320 to form the source region 510.

Referring to FIG. 7, after the source region 510 is formed, spacers 331 and 332 are formed on side surfaces of the first and second gate electrodes 310 and 320. In this case, the spacers 331 and 332 are disposed on side surfaces of the first and second charge trap layers 202a and 202b to insulate side surfaces of the first and second charge trap layers 202a and 202b. .

Thereafter, high concentrations of p-type impurities are implanted into the sides of the first and second gate electrodes 310 and 320 to form drain regions 521 and 522.

Afterwards, silicide layers 610, 620, 630, 640, and 650 are formed on the first and second gate electrodes 310 and 320, the source region 510, and the drain regions 521 and 522. Is formed.

As a result, a flash memory device including first and second memory cells FL1 and FL2 symmetric with each other and having a SONOS structure is formed.

The first memory cell FL1 includes the first gate electrode 310 and the first charge trap unit 210.

The first charge trap unit 210 includes a first tunnel oxide layer 201a, the first charge trap layer 202a, and a first insulating layer 204a. The first tunnel oxide layer 201a is interposed between the first charge trap layer 202a and the semiconductor substrate 100, and the first insulating layer 204a is formed of the first gate electrode 310 and the first gate. It is interposed between the charge trap layers 202a. That is, the first charge trap unit 210 has an ONO structure.

The second memory cell FL2 includes the second gate electrode 320 and the second charge trap unit 220.

The second charge trap unit 220 includes a second tunnel oxide film 201b, the second charge trap layer 202b, and a second insulating film 204b. The second tunnel oxide layer 201b is interposed between the second charge trap layer 202b and the semiconductor substrate 100, and the second insulating layer 204b includes the second gate electrode 320 and the second layer. It is interposed between the charge trap layers 202b. Similarly, the second charge trap unit 220 has an ONO structure.

The first and second charge trap layers 202a and 202b may trap and retain charge. In more detail, the first and second charge trap layers 202a and 202b may trap and retain hot electrons or hot holes.

The first gate electrode 310 and the second gate electrode 320 have substantially the same size.

In addition, the width W1 of the first charge trap layer 202a is substantially the same as the width of the first spacer, and similarly, the width W2 of the second charge trap layer 202b is the second spacer. Is substantially equal to the width of.

Therefore, the width of the first charge trap layer 202a is substantially the same as the width of the second charge trap layer 202b.

Since the sizes of the first and second gate electrodes 310 and 320 are the same and the sizes of the first and second charge trap layers 202b are the same, the first memory cell FL1 and The second memory cell FL2 has substantially the same characteristics.

Therefore, the flash memory device of the SONOS structure according to the embodiment can reduce the deviation between the memory cells.

In particular, the flash memory device of the SONOS structure according to the embodiment can reduce the variation between the memory cells due to the variation in the width of the charge trap layers.

In addition, the first memory cell FL1 has a channel region CH that is divided into a first channel region CH1 and a second channel region CH2. The channel region CH is formed between the source region 510 and the drain region 521.

The first channel region CH1 corresponds to the first charge trap unit 210, and the second channel region CH2 is adjacent to the first channel region CH1.

In more detail, the first charge trap unit 210 is disposed on the first channel region CH1, and the first charge trap unit 210 is not disposed on the second channel region CH2. That is, the first charge trap unit 210 is disposed only on the first channel region CH1.

That is, the first channel region CH1 and the second channel region CH2 are divided by the first charge trap unit 210.

The first gate electrode 310 is disposed on the first channel region CH1 and the second channel region CH2. That is, the first gate electrode 310 is disposed on the first channel region CH1, in more detail, on the first charge trap unit 210 and also on the second channel region CH2. .

In addition, the first gate electrode 310 covers the side surface of the first charge trap unit 210. That is, the side surface of the first charge trap layer 202a is covered.

The second memory cell FL2 also has the same structure as the first memory cell FL1.

Since the first memory cell FL1 includes the first channel region CH1 and the second channel region CH2, one transistor and one memory cell are combined.

Therefore, the flash memory device according to the embodiment may implement an improved degree of integration.

That is, the first channel region CH1 and the second channel region CH2 may be controlled by the first gate electrode 310.

Accordingly, since the first memory cell FL1 and the second memory cell FL2 have a select transistor function, the flash memory device according to the embodiment may reduce overerase.

8 is a circuit diagram of a flash memory device according to an embodiment.

Referring to FIGS. 7 and 8, the flash memory device according to the embodiment injects hot electrons or hot holes into the charge trap layers 202a and 202b to form the memory cells FL1 and FL2. Program or erase it.

That is, hot electrons are injected into the charge trap layers 202a and 202b to lower the threshold voltage Vth of the channel region CH, thereby programming the memory cells FL1 and FL2. In addition, hot holes are injected into the charge trap layers 202a and 202b to remove the hot electrons, thereby erasing the memory cells FL1 and FL2.

In addition, since the charge trap layer is not disposed on the second channel region CH2, the portion corresponding to the second channel region CH2 performs a transistor function.

Referring to Table 1, the process of programming, reading, and raising the first memory cell FL1 is as follows.

First, in order to program the first memory cell FL1, a high bias VH is applied to the first word line WL1 and the source region 510, and a back is applied to the first bit line BL1. The bias VB is applied.

In addition, an inhibit bias VI is applied to other bit lines, and a reference voltage (0 V) is applied to the semiconductor substrate 100 and other word lines.

That is, a high bias VH is applied to the first gate electrode 310 and the source region 510, a back bias VB is applied to the drain electrodes 521 and 522, and the second gate. A reference voltage is applied to the electrode 320.

The high bias (VH) is about +9 to +11 V and the back bias (VB) is about +1 to +2 V. In addition, the inhibit bias VI may be about 4 to 6 V, or may be floating (FL).

Accordingly, hot electrons are injected into the first charge trap layer 202a.

In order to read the first memory cell FL1, a driving bias Vcc is applied to the first word line WL1, and a read bias Vread is applied to the first bit line BL1. do. In addition, a reference voltage is applied to the source region 510 and the semiconductor substrate 100.

That is, the driving bias Vcc is applied to the first gate electrode 310, and the read bias Vread is applied to the drain regions 521 and 522.

The driving bias Vcc is about 3 to 7 V and the read bias Vread is about 0.3 to 1 V.

In order to erase the first memory cell FL1, a negative voltage VL is applied to the first word line WL1, and about 3 to 5V is applied to the source region 510 in more detail. , A positive voltage of about 4V is applied.

In addition, a reference voltage is applied to the semiconductor substrate 100, a reference voltage or floating is applied to bit lines, and a reference voltage is applied to other word lines.

That is, a low bias VL is applied to the first gate electrode 310, and a reference voltage is applied to the second gate electrode 320.

The low bias (VL) is about -7 to -9V.

Similarly, a reference voltage or floating FL is applied to the drain electrodes.

In this manner, hot holes are injected into the first charge trap layer 202a, and accordingly, the first memory cell FL1 is erased.

The erasure process may be performed at the same time for each page or sector including a plurality of memory cells.

WL1 WL2 BL1 BL2 Source area Semiconductor substrate program VH 0 V VB VI VH 0 V lead Vcc 0 V Vread 0 V 0 V 0 V Eraise VL 0 V 0 V or FL 0 V or FL 4 V 0 V

As described above, the flash memory device according to the embodiment may program and erase hot electrons and hot holes by injecting them into the charge trap unit.

Therefore, the flash memory device according to the embodiment can be driven in the form of NOR, and thus high integration can be achieved.

Although described above with reference to the embodiment is only an example and is not intended to limit the invention, those of ordinary skill in the art to which the present invention does not exemplify the above within the scope not departing from the essential characteristics of this embodiment It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 7 are cross-sectional views illustrating processes of a method of manufacturing a flash memory device having a SONOS structure according to an embodiment.

8 is a circuit diagram of a flash memory device according to an embodiment.

Claims (8)

Source and drain regions spaced apart from each other on the substrate; A first channel region formed between the source region and the drain region; A second channel region formed between the source region and the drain region and formed on a side surface of the first channel region; A charge trap unit corresponding to the first channel region; And And a gate electrode disposed on the first channel region and the second channel region. The flash memory device of claim 1, wherein the charge trap unit has an ONO structure. The flash memory device of claim 1, wherein the gate electrode covers an upper surface and a side surface of the charge trap unit. Source and drain regions spaced apart from each other on the substrate; A first channel region formed between the source region and the drain region; A second channel region formed between the source region and the drain region and formed on a side surface of the first channel region; A charge trap unit corresponding to the first channel region; And In the flash memory device comprising a gate electrode disposed on the first channel region and the second channel region, Injecting hot electrons into the charge trap unit to program the hot electrons; And And injecting hot holes into the charge trap unit to erase the hot holes. The method of claim 4, wherein in the programming step: A high bias is applied to the source region and the gate electrode, And a back bias is applied to the drain region. 6. The method of claim 5, wherein the high bias is +9 to + 11V and the back bias is +1 to + 2V. The method of claim 4, wherein in the erasing step, A low bias of negative voltage is applied to the gate electrode, And the drain region is grounded. The method of claim 7, wherein in the erasure step, The low bias is -7 to -9V, and +3 to + 5V is applied to the source region.

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