KR20100044997A - Method for manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A manufacturing method of a flash memory device is provided to improve the reliability of a device by preventing the damage of the ONO layer by selectively etching a hard mask which is formed on a gate stack with a reactive ion etching process. CONSTITUTION: An insulating layer, a first polysilicon layer, the oxide-nitride-oxide layer, and a second polysilicon layer are successively formed on a semiconductor substrate(10). A hard mask is formed on a second polysilicon layer. A gate stack(80) including a tunnel oxide film(35), a floating gate(45), a dielectric layer(55), and a control gate(65) are formed on the semiconductor substrate. A photoresist pattern is formed on the semiconductor substrate so that the top side of the hard mask is exposed. The hard mask is removed by using the photoresist pattern as the etching mask.

Description

Manufacturing method of flash memory device {Method for Manufacturing Flash Memory Device}

The embodiment relates to a method of manufacturing a flash memory device.

Semiconductor memory devices are classified into volatile memory and nonvolatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and it is possible to input and save data when power is applied, but it is impossible to save data by volatilization when power is removed. Has On the other hand, nonvolatile memory, which occupies most of read only memory (ROM), is characterized in that data is preserved even when power is not applied.

Nonvolatile memory devices have an almost indefinite accumulation capacity, and demand for flash memory capable of electrically inputting and outputting data, such as electrically erasable and programmalbe ROM (EEPROM), is increasing. The flash memory is a nonvolatile storage medium in which stored data is not damaged even when the power is turned off. However, the flash memory has a relatively high processing speed for writing, reading, and deleting data.

In the flash memory device, a 130nm product is becoming more common, and recently, it is shrinking below 90nm. Accordingly, a hard mask formed of an oxide film (LT TEOS) is used to pattern the gate.

In the flash memory device, a tunnel oxide film and a first polysilicon layer are formed on a semiconductor substrate, and an ONO film including an oxide film-nitride-oxide film triple structure is formed on the first polysilicon layer and used as a control gate on the ONO film. A second polysilicon layer is formed. Thereafter, a hard mask pattern is formed on the polysilicon layer, and the second polysilicon layer, the ONO layer, the first polysilicon layer, and the tunnel oxide layer are etched at once using the hard mask pattern as an etching mask. Accordingly, a flash memory device having a tunnel oxide film pattern, a floating gate, an ONO pattern, and a control gate is formed on the semiconductor substrate.

After the flash device is formed using the hard mask pattern, the hard mask pattern is removed from the flash memory device.

The hard mask pattern is removed by an HF VPC process, which is a type of wet etching. The oxide mask pattern or the nitride film pattern included in the tunnel oxide film and the ONO pattern exposed on the sidewall of the flash device during the removal of the hard mask pattern may be a hard mask pattern. It can be damaged while being removed.

As described above, in the flash device, the ONO pattern is a very important pattern for storing and releasing charges, and thus, when the ONO pattern is damaged, the performance of the flash device is greatly degraded.

The embodiment provides a method of manufacturing a flash memory device capable of improving performance of a device by preventing damage to a tunnel oxide layer and an ONO pattern when the hard mask is removed.

A method of manufacturing a flash memory device according to an embodiment includes: sequentially forming an insulating layer, a first polysilicon layer, an ONO layer, and a second polysilicon layer on a semiconductor substrate; Forming a hard mask on the second polysilicon layer; Forming a gate stack including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on the semiconductor substrate by an etching process using the hard mask as an etching mask; Forming a photoresist pattern on the semiconductor substrate to expose the top surface of the hard mask; And removing the hard mask by using the photoresist pattern as an etching mask.

According to the method of manufacturing the flash memory device according to the embodiment, the hard mask formed on the gate stack may be selectively etched by a reactive ion etching process to prevent damage to the ONO layer, thereby improving reliability of the device.

A flash memory device and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

A method of manufacturing a flash memory device according to an embodiment will be described with reference to FIGS. 1 to 5.

Referring to FIG. 1, an isolation layer 20 is formed on a semiconductor substrate 10.

The device isolation layer 20 may be formed by a LOCOS process or an STI process to define the active region and the field region. For example, the device isolation layer 20 may be formed by HDP USG after forming a trench in the semiconductor substrate 10.

Next, the insulating layer 30, the first polysilicon layer 40, the ONO layer 50, and the second polysilicon layer 60 are sequentially stacked on the semiconductor substrate 10. The ONO layer 50 may be formed in a triple structure of an oxide film-nitride film-oxide film.

A hard mask 70 is formed on the second polysilicon layer 60 to define a gate. For example, the hard mask 70 may be formed of an oxide film such as LP TEOS. In addition, the hard mask 70 may be formed to a thickness of 300 ~ 500 ℃.

Although not shown, the hard mask 70 forms a hard mask layer (not shown) on the second polysilicon layer 60 and a photoresist pattern (not shown) defining a gate region on the hard mask layer. ) May be formed by selectively etching the hard mask layer using the photoresist pattern as an etching mask.

The hard mask 70 is formed because a general photoresist film is difficult to form a gate stack in a polysilicon patterning process due to lack of margin. For example, a hard mask is required to form a gate by etching polysilicon in a 90 nm flash device.

Referring to FIG. 2, a gate stack 80 is formed on the semiconductor substrate 10. The gate stack 80 may include the second polysilicon layer 60, the ONO layer 50, the first polysilicon layer 40, and the insulating layer 30 using the hard mask 70 as an etch mask. It may be formed by etching.

Therefore, a floating gate 45 in which data is stored on the semiconductor substrate 10, a tunnel oxide layer 35 formed between the floating gate 45 and the semiconductor substrate 10, and a control gate 65 functioning as a word line. In order to separate the control gate 65 and the floating gate 45, a gate stack 80 including a dielectric layer 55 formed therebetween is formed.

In this case, since the gate stack 80 is etched using the hard mask 70 as an etching mask, both side walls of the gate stack 80 are exposed.

Meanwhile, in the embodiment, the gate stack 80 is formed by one etching process, but the tunnel oxide film, the control gate, and the dielectric layer are first formed on the semiconductor substrate 10, and then the second polysilicon layer is deposited. The second polysilicon layer may be etched by a hard mask to form a control gate.

Referring to FIG. 3, a photoresist pattern 100 exposing the top surface of the hard mask 70 is formed. The photoresist pattern 100 is formed on the semiconductor substrate 10 including the hard mask 70 by spin coating to form a photoresist film (not shown), followed by exposure and development using a pattern mask (not shown). The process may be performed to expose the top surface of the hard mask 70.

The reason for forming the photoresist pattern 100 is to form a silicide layer on an upper surface of the gate stack 80 by removing the hard mask 70. This is required to remove the hard mask 70 because the hard mask 70 remaining on the control gate 65 after the gate stack 80 is formed to interfere with silicide formation.

In general, the hard mask may be removed by HF VPC (Vapor Phase Cleaning). In other words, HF may be vaporized using a temperature to remove an oxide hard mask. The reason for using the HF VPC is the selectivity between the device isolation layer formed of HDP USG and the hard mask formed of LP TEOS.

For example, HF Vapor has a selectivity of about 1: 100 for HDP USG and LP TEOS at a temperature of 30 to 40 ° C, which can prevent the loss of device isolation film when removing the hard mask. However, when the hard mask is removed using the HF VPC as described above, the ONO film is damaged because the oxide film uses HTO (High Temperature) similar to the hard mask in ONO (oxide / nitride / oxide). Therefore, in some embodiments, only the hard mask 70 may be removed from the photoresist pattern 100 in order to prevent damage to the ONO layer.

Referring to FIG. 4, the hard mask 70 on the gate stack 80 is removed. The hard mask 70 may be removed by performing a reactive ion etching (RIE) process using the photoresist pattern 100 as an etching mask. In particular, the hard mask 70 may be removed by an etching process using a remote plasma.

Specifically, the removal of the hard mask 70 may be performed using CHF ₃ or CH ₄ gas for 10-30 seconds at a power of 800 ~ 1500W and a pressure of 5 ~ 10mTorr.

Only the hard mask 70 may be selectively removed by a reactive ion etching process using the photoresist pattern 100 as a mask, thereby preventing damage to the dielectric layer 55, which is an ONO film. That is, since the photoresist pattern 100 exposes only the hard mask 70 and all remaining regions are hidden, only the hard mask 70 may be selectively removed.

In addition, since the hard mask 70 can be removed by the remote plasma etching process, the device is not damaged by the plasma.

Referring to FIG. 5, the photoresist pattern 100 is removed by an ashing and cleaning process. Therefore, the gate stack 80 including the tunnel oxide layer 35, the floating gate 45, the dielectric layer 55, and the control gate 65 is formed on the semiconductor substrate 10.

In a subsequent process, the silicide layer 90 may be formed on the surface of the control gate 65.

According to the embodiment, the hard mask on the control gate is selectively removed by the reactive ion etching process to prevent damage to the ONO pattern by the etching process, thereby improving the quality of the flash memory device.

The embodiments described above are not limited to the above-described embodiments and drawings, and it is to be understood that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be obvious to those who have it.

1 to 5 are cross-sectional views illustrating a manufacturing process of a flash memory device according to an embodiment.

Claims (8)

Sequentially forming an insulating layer, a first polysilicon layer, an ONO layer, and a second polysilicon layer on a semiconductor substrate; Forming a hard mask on the second polysilicon layer; Forming a gate stack including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on the semiconductor substrate by an etching process using the hard mask as an etching mask; Forming a photoresist pattern on the semiconductor substrate to expose the top surface of the hard mask; And And removing the hard mask by using the photoresist pattern as an etching mask. The method of claim 1, And said hard mask is removed by a reactive ion etching process. The method of claim 1, And the hard mask is removed by a remote plasma etching process. The method of claim 1, The hard mask is a method of manufacturing a flash memory device, characterized in that formed by LP TEOS. The method of claim 1, Removing the hard mask is supplied with CHF ₃ or CH ₄ gas, the flash memory device manufacturing method, characterized in that for 10 to 30 seconds at a power of 800 ~ 1500W and a pressure of 5 ~ 10mTorr. The method of claim 1, The hard mask has a thickness of 300 ~ 500Å Flash memory device manufacturing method characterized in that. The method of claim 1, And removing the hard mask to form silicide on a surface of the control gate. The method of claim 7, wherein The silicide is a method of manufacturing a flash memory device, characterized in that any one of cobalt silicide, nickel silicide and titanium silicide.

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