KR20100042968A - Semiconductor device having stacked array structure and fabrication method for the same - Google Patents

Abstract

PURPOSE: A semiconductor device with a stacked array structure and a manufacturing method thereof are provided to improve the control of each channel of a gate by surrounding each semiconductor layer with one gate. CONSTITUTION: A semiconductor layer is vertically separated from a substrate(100) and one or more semiconductor layer are stacked. A gate(510) passes through the semiconductor layer while interposing a gate insulation layer on each semiconductor layer. A source(222) and a drain(226) are formed on both sides of the gate on each semiconductor layer. An interlayer insulation layer(600) surrounds the source and drain of each semiconductor layer. The interlayer insulation layer is formed on an empty space around each semiconductor layer.

Description

A semiconductor device having a star structure and a method of manufacturing the same {SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE AND FABRICATION METHOD FOR THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor having a stacked array structure (a star structure: a star structure), which can be applied to not only a switching device but also a memory device. An element and a method of manufacturing the same.

Currently, since MOSFETs used as switching elements are mostly planar type structures, they occupy a large area in order to use them as memory array switching elements such as 1T-DRAM, and there have been certain limitations to high integration of the memory arrays.

In addition, since most of the memory devices used as memory cells have a planar type structure, there are problems as described above. To improve this, various types of memory devices having vertical channels have been developed. Since it is connected between the bit line and the word line, there is a problem that there is a certain limit to the high-density integration of the memory array with a conventional memory device.

In order to solve the problems of the prior art, it is possible to increase the width of the channel as much as possible while having a vertical channel, Single Gate, Double Gate and Gate All Around as needed. It is an object of the present invention to provide a semiconductor device having a star structure which can be realized by GAA, and a method of manufacturing the same.

In order to achieve the above object, the semiconductor device having a star structure according to the present invention comprises a semiconductor layer laminated at least one distance apart vertically spaced apart from the substrate; A gate formed through each of the semiconductor layers with a gate insulating film interposed therebetween on each of the semiconductor layers; A source and a drain formed on both sides of the gate in each of the semiconductor layers; And an interlayer insulating film surrounding the source and the drain of each of the semiconductor layers or filled in an empty space around each of the semiconductor layers.

In the method for fabricating a semiconductor device having a star structure according to the present invention, n < 1 < th > Forming a layer one more time, and then depositing an etch mask material on the n + 1th stacking layer; Patterning the etch mask material and sequentially etching the n + 1 < th > lamination layer " n " semiconductor layer / lamination media " to form the columnar stack structure by using the etching mask material as a first etch mask. A second step; Removing the first etching mask and forming a gate insulating layer on the columnar stacked structure; A fourth step of forming a gate by etching the gate material with a second etching mask after depositing a gate material on the entire surface of the substrate; Removing the gate insulating film exposed by the gate material etching, and then forming a source / drain; A sixth step of removing all of the n + 1 lamination media layers and then filling an empty space of the exposed structure with an interlayer insulating film, or

After the n < 1 > layer-> semiconductor layer is repeatedly formed n times on a predetermined substrate, the n + 1 < th > Depositing an etch mask material thereon; Patterning the etch mask material and sequentially etching the n + 1 < th > lamination layer " n " semiconductor layer / lamination media " to form the columnar stack structure by using the etching mask material as a first etch mask. A second step; Depositing a groove filling material on the entire surface of the substrate, and then planarizing the first etching mask to reveal the second etching mask; By using the second etching mask, the groove filling material exposed between the second etching masks is etched to form a partition, and the part of the stacked structure of the second step is exposed to both sides of the partition, and then the second etching mask. Removing the fourth step; A fifth step of etching the laminated layer of the exposed stacked structure to expose only the first etching mask and the semiconductor layer on both sides of the partition; A sixth step of forming a gate insulating film in the semiconductor layer exposed to both sides of the partition; Depositing a gate material on the entire surface of the substrate, and then planarizing the first etching mask to expose the first etching mask, and then removing the first etching mask; An eighth step of removing the partition and forming a source / drain in the semiconductor layer exposed by the partition removal; And a ninth step of filling the empty space of the structure with an interlayer insulating film.

According to the above configuration, the present invention can form a source / drain to the left and the right while having a vertical channel to increase the width of the channel, and cross or wrap one or more semiconductor layers stacked vertically with one gate. A semiconductor having one of a single gate, a double gate, and a gate all around (GAA) structure sharing a body with a neighboring device and allowing body contact in some cases. There is an effect that a plurality of elements can be formed vertically.

In particular, when the semiconductor device according to the present invention is formed to surround each semiconductor layer with one gate, and thus has a gate all around (GAA) structure, each channel has a rectangular cylindrical shape according to the cross-sectional shape of each semiconductor layer. Or it is formed in a cylindrical shape, there is an effect that the control of each channel of the gate is greatly improved.

Furthermore, when the semiconductor device having the GAA structure is used as a memory cell, the curvature radius is changed between the gate and each semiconductor layer, and an insulating film having a single or multi-layer structure is positioned to increase the operation characteristics of the cell.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 to 8 are perspective views illustrating a device structure in which the gate 500 passes through each of the semiconductor layers 220 and 240 and a method of manufacturing the same according to an embodiment of the present invention. In another embodiment of the present invention, a process perspective view showing a device structure and a method of manufacturing the gate 510, 520, and 530 that surrounds each of the semiconductor layers 220 and 240 and a method of manufacturing the same are illustrated in FIGS. 18 to 22. In another embodiment, a cross-sectional view of each semiconductor layer 220 and 240 surrounded by the gates 510, 520, and 530 is a circular perspective view showing a device structure and a method of manufacturing the same.

While the drawings show features of a cross section of a repeating structure, these are merely conceptual illustrations of representative examples that enable those skilled in the art to understand and practice the invention, and are therefore limited to the interpretation of the claims in the appended claims. It shall not be applied to (the same reference number indicates the same configuration even if the shape is different).

Embodiments Regarding Device Structure

The structure of the semiconductor device according to the present invention is basically spaced vertically apart from the substrate 100 as shown in FIG. 8 (see FIG. 7), 17 (see FIG. 16), or 22 (see FIG. 21). One or more stacked semiconductor layers 220 and 240; Gates 500, 510, 520 or 530 formed on each of the semiconductor layers and passing through all of the semiconductor layers with a gate insulating layer 400, 410 or 420 therebetween; A source 222 and a drain 226 formed at both sides of the gate in each semiconductor layer; And an interlayer insulating film 600 which surrounds the source and the drain of each of the semiconductor layers or is filled in the empty space around each of the semiconductor layers.

Accordingly, the present embodiment is characterized in that the semiconductor layer, which is an active region, is vertically spaced vertically apart from the substrate 100 and has one or more stacked structures, as shown in FIGS. 7 and 14 or 19. Both the stacked semiconductor layers 220 and 240 are connected to one gate 500, 510, 520 or 530 with the gate insulating film 400, 410 or 420 interposed therebetween, the source 222 and the drain 226. ) Is formed horizontally to the left and right of the gate, and surrounds the source and the drain of each semiconductor layer (FIG. 17 or 22), or fills in the empty space around each semiconductor layer (FIG. 8). In the field region for device isolation with the interlayer insulating film 600, the channel width of the device can be vertically increased according to the present embodiment (high performance devices can be implemented without affecting integration), and the single gate ( Also, a plurality of semiconductor devices having a gate all around (GAA, FIG. 16 or 21) structure surrounding the channel region as well as a single gate (Double Gate) and a double gate (FIG. 7) may be formed vertically. There are advantages to it.

In order to further embody the above embodiment, the cross section of each of the semiconductor layers 220 or 240 may have a square (as well as a square as well as a rectangle) as shown in FIG. 7 or 13, or a circle (of course, as shown in FIG. 18). Elliptical is also possible).

In this case, when the cross section of each of the semiconductor layers 220 or 240 is a quadrangle, the gate is double gated so as to cross each semiconductor layer at both sides as shown by 500 in FIG. 7. It is preferable to have a structure or to have a gate all around (GAA) structure by covering all four sides, as shown by reference numerals 510, 520 or 530 of FIG. 16. Each semiconductor layer may cross and pass from one side to have a single gate structure.

On the other hand, when the cross-section of each of the semiconductor layers 220 or 240 is circular or elliptical, the gate is wrapped around the outer peripheral surface of each semiconductor layer, as shown by reference numeral 510, 520 or 530 of FIG. It is desirable to have a Gate All Around (GAA) structure.

The gate insulating layer interposed between the semiconductor layers and the gates for the purpose of insulation may have a single-sided structure 400 when the gate 500 crosses each of the semiconductor layers 220 and 240, as shown in FIG. 7. 16 or 21, when the gates 510, 520, or 530 pass through the semiconductor layers 220 and 240, they have a rectangular cylindrical shape 410 or a cylindrical shape 420.

The source 222 and the drain 226 may be formed on one side (not shown) or both sides (FIG. 7) of each of the semiconductor layers 220 or 240 with the gate interposed therebetween, or the gate may be In the enclosed structure (FIG. 16 or 21), each semiconductor layer 220 or 240 in which the source 222 and the drain 226 are not formed is formed by forming a predetermined depth on the outer circumferential surface of each semiconductor layer 220 or 240. It is preferable to allow the body region to exist on the other side or the inside of the) so that body contact with the outside is possible and the body can be shared with the neighboring device (the device connected to the same semiconductor layer, hereinafter same).

Example 1 of Manufacturing Method of Device

An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1 to 8.

First, as shown in FIG. 1, after the " stacked media layer 210a-> semiconductor layer 220a " is formed n times on a predetermined substrate 100 (in FIG. 1, the film is repeatedly formed twice for convenience of drawing). In addition, an n + 1th stacking layer (250a in FIG. 1: a third stacking layer: 250a) is formed on the nth semiconductor layer (240a in FIG. 1) once more, and then the n + 1th stacking is formed. An etching mask material 300a is deposited on the intermediate layer 250a (first step).

The stacking layer 210a, 230a, 250a and the semiconductor layer 220a, 240a may be stacked by an epitaxial method for single crystal growth.

In addition, the stacking layers 210a, 230a, and 250a are for stacking the semiconductor layers 220a and 240a away from the substrate 100 at a predetermined distance vertically, and subsequently etching away to the next interlayer insulating film. It is used to electrically separate each semiconductor layer.

Accordingly, the lamination media layers 210a, 230a, and 250a have a lattice structure similar to those of the semiconductor layers 220a and 240a, and are easily stacked by epitaxy, and the semiconductor layers 220a and 240a. Any material can be used as long as the material and the etching selectivity are large. For example, when the material of the substrate 100 and the semiconductor layers 220a and 240a is silicon (Si), the material of the stacking media layers 210a and 230a is preferably silicon germanium (SiGe).

The etch mask material 300a may be any material having a high etching selectivity with respect to the stacking media layers 210a, 230a and 250a and the semiconductor layers 220a and 240a, but the stacking media layers 210a and Nitride is preferable when the material of 230a is silicon germanium (SiGe) and the material of the semiconductor layers 220a and 240a is silicon (Si).

When n is repeated n times when the “layered layer layer 210a-> semiconductor layer 220a” is repeated n times, a simple switching element may be manufactured, and when n is 2 or more, a plurality of vertically stacked memory elements (cells) Can be obtained.

Next, as shown in FIG. 2, after the etching mask material 300a is patterned, the semiconductor layer is stacked n times from the n + 1 th stacking layer 250a using the first etching mask 300. The stacking intermediate layer "is sequentially etched to form a columnar stacked structure 200 (second step).

Here, when forming the columnar stacked structure 200, the first stacking media layer 210a may give an etching process margin. That is, there is a margin to set the process conditions so that the first stacking layer 210a is not overdone during etching.

Subsequently, as shown in FIG. 3, the first etching mask 300 is removed, and a gate insulating layer 400a is formed on the columnar stacked structure 200 (third step).

The gate insulating film 400a forming process may be simply performed by a thermal oxide film process to manufacture a switching device, or a memory device may be formed by forming a single or multilayer structure including a high dielectric material.

Next, as shown in FIG. 4, after the gate material is deposited on the entire surface of the substrate, the gate material is etched with a second etching mask (not shown) to form a gate 500 (fourth step).

The gate material deposition is also filled between the at least one columnar stacked structure 200 covered by the gate insulating film 400a, and the gate material etching for forming the gate 500 is a planarization process (e.g., It is preferable to carry out after further CMP process).

Subsequently, as shown in FIG. 5, the gate insulating layer 400a exposed by the gate material etching is removed, and then a source 222 / drain 226 is formed in each exposed semiconductor layer 220 or 240 as shown in FIG. 6. (Step 5).

Here, the source 222 / drain 226 is formed by an epitaxy method or a plasma method in the state where an impurity dopant is implanted.

In FIG. 6, reference numeral 224 denotes a region in which a channel is formed when the device operates in contact with the gate insulating layer 400 under the gate 500. In FIG. 7, each of the semiconductor layers 220 or 240 spaced apart from each other is an active body region. Becomes

Subsequently, as shown in FIG. 7, all of the n + 1 stacking media layers 210, 230, and 250 forming the pillar structure are removed, and as shown in FIG. 8, the empty space of the exposed structure is filled with the interlayer insulating layer 600 ( 6th step).

Removal of the n + 1 stacking layers 210, 230, and 250 may use a difference in etching selectivity from the semiconductor layers 220 and 240.

The process of removing the exposed gate insulating layer 400 may be further performed before filling the empty space of the structure exposed by the removal of the n + 1 stacking media layers 210, 230, and 250 with the interlayer insulating layer 600.

The interlayer insulating layer 600 may be filled with an empty space by using a known CVD process, which may electrically close each of the semiconductor layers 220 or 240, the gate 500, and the substrate 100 to each other. Since it is intended to isolate, there may be some void.

<Example 2 of Manufacturing Method of Device>

Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 9 to 17.

Also in this case, first, after the same process as the first step and the second step of the first embodiment of the manufacturing method of the device, in the state of Figure 9, as shown in Figure 10, the groove filling material 700 on the entire surface of the substrate After the deposition, the first etching mask 300 is flattened to be exposed, and as shown in FIG. 11, the second etching mask 800 is formed (third step).

Here, the groove filling material 700 is preferably a material having the same or similar etching rate (etch selectivity) as the stacking media layers 210, 230, and 250, and the substrate 100 and the semiconductor layers 220 and 240. In the case where the material is silicon (Si), the lamination media layer 210, 230, and 250 and the groove filling material 700 are more preferably all of silicon germanium (SiGe).

In the planarization process, when the first etching mask 300 is formed of nitride, it is preferable to use a known CMP process using the first etching mask 300 as an etch stopper.

The second etching mask 800 may be formed so that the width A of the mask is larger than the gap B between the masks, or the lower width of the mask is larger than the upper width by using a slope etch. It is preferable.

In particular, in the latter case, even if the interval between the masks is formed by the resolution by the same photo etching, the interval between the actual second etching masks 800 may be narrower.

The gap B between the second etching masks 800 may be provided only to a gap through which the groove filling material 700 may be etched, and further, partitions 710 and 720 formed of the groove filling material 700 may be further formed. While etching, the width between the partitions 710 and 720 is reduced and the gap is considered.

Subsequently, as shown in FIG. 12, the groove filling material 700 exposed between the second etching masks is etched using the second etching mask 800 to divide the grooves 715 between the partitions 710 and 720. To form a portion of the second stacked structure 200, 300 on both sides of the partition (see 210b, 220b, 230b, 240b, 250b), and then remove the second etching mask 800 ( 4th step).

In this case, the partitions 710 and 720 may be formed using an anisotropic etching method so that the groove filling material 700 exposed between the second etching masks 800 is vertically etched.

Next, as shown in FIG. 13, the first and second etching masks 300 and 220b and 240b are etched on both sides of the partitions 712 and 722 by etching the laminated media layers 210b, 230b and 250b of the exposed stacked structure. ) To reveal only (step 5).

The etching of the exposed layered media (210b, 230b, 250b) is preferably such that the partitions (710, 720) of the groove filling material 700 is also partially etched using an isotropic etching method. This is possible when the groove filling material 700 is made of the same material as the stacking media layers 210, 230, and 250 (eg, silicon germanium) or a material having similar etching rates. In FIG. 13, reference numerals 712 and 722 denote the semiconductor layers 220 or 240 when the groove filling material 700 is made of the same material (eg, silicon germanium) as the stacking media layers 210, 230, and 250. It shows the surroundings forming a partition.

Subsequently, as shown in FIG. 14, a gate insulating layer 410 is formed in the semiconductor layers 220b and 240b exposed to both sides of the partition 712 or 722 (sixth step).

The gate insulating film 410 forming process may be performed in the same manner as in the first embodiment of the method for manufacturing the device.

However, when the partition 712 or 722 material is a silicon-based material (eg, silicon germanium), the gate insulating layer 412 is formed here, and the same is true when the substrate 100 is silicon.

As a result, as shown in FIG. 14, the gate insulating layers 410 and 412 may be formed on the entire exposed structure.

Subsequently, after the gate material is deposited on the entire surface of the substrate, the first etching mask 300 is flattened to be exposed, and as shown in FIG. 15, the first etching mask 300 is removed to form gates 510 and 520. Or 530) (seventh step).

The gate material deposition is performed by filling the spaces between the partitions 712 and 722 with a silicon-based material such as doped polysilicon or a metal to surround each semiconductor layer 220b or 240b on which the gate insulating film 410 is formed. do.

Next, as shown in FIG. 16, the partitions 712 and 722 are removed and a source 222 / drain 226 is formed in each of the semiconductor layers exposed by the partition removal (eighth step).

Here, the source 222 / drain 226 is formed by an epitaxy method or a plasma method in the state where an impurity dopant is implanted.

When the impurity is implanted, impurities are injected around the outer circumferential surface of each of the semiconductor layers exposed by the removal of the partition, and as shown in FIG. 16, the body region is present inside the semiconductor layers. A portion of the body region that is covered by the gate (eg, 520) with the gate insulating layer 410 interposed therebetween is a region 224 in which a channel is formed during device operation.

The source 222 / drain 226 is formed after removing the gate insulating layer 412 formed on the side surfaces of the partitions 712 and 722 so that the gates 510, 520, or 530 may be formed of a silicon-based material. In this case, it is also preferable to allow impurity ion implantation.

Next, as shown in FIG. 17, the interlayer insulating film 600 is filled in the empty space created by removing the partitions 712 and 722 (ninth step).

Filling the interlayer insulating film 600 is the same as in the first embodiment of the manufacturing method, a description thereof will be omitted.

<Example 3 of Manufacturing Method of Device>

Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 18 to 22.

18. The surface of the semiconductor layer exposed to both sides of the partitions 712 and 722 between the fifth step and the sixth step is the same as that in the second embodiment of the manufacturing method, and reference numerals 220c and 240c of FIG. As described above, it is characterized in that a further step of curved surface is added.

In this way, the cylindrical gate insulating film 420 is formed on the surfaces of the semiconductor layers 220c and 240c of the cylindrical structure in a subsequent process (see FIG. 19), and the gate material is deposited to surround the cylindrical gate insulating film 420 so that the gate ( 510, 520, and 530 are formed between the partitions 712 and 722 (see FIG. 20), and a source 222 / drain 226 is formed in each semiconductor layer exposed after removing the partitions 712 and 722 (see FIG. 20). 21), a semiconductor device is manufactured by filling the interlayer insulating film 600 in an empty space formed by removing the partitions 712 and 722 (see FIG. 22).

Advantages of the manufacturing method include the formation of the cylindrical semiconductor layers 220c and 240c, the formation of the cylindrical gate insulating film 420, and the gate 510 between the partitions 712 and 722, covering the cylindrical gate insulating film 420. , 520, 530 can be formed.

Here, as shown in FIG. 13, in order to curved the surfaces of the semiconductor layers 220b and 240b exposed to both sides of the partitions 712 and 722 as shown by reference numerals 220c and 240c of FIG. 18, a hydrogen annealing process is used. Alternatively, an oxidation process and an oxide film etching process in which silicon erosion occurs may be repeatedly used.

In addition, since the processes are the same as in Example 2 of the manufacturing method, a description thereof will be omitted.

1 to 8 are process perspective views illustrating a device structure and a method of manufacturing the gate 500 passing through each of the semiconductor layers 220 and 240 in an embodiment of the present invention.

9 to 17 are process perspective views illustrating a device structure and a method of manufacturing the gates 510, 520, and 530 that pass through the semiconductor layers 220 and 240 in another embodiment of the present invention.

18 to 22 are perspective views illustrating a device structure having a circular cross section of each of the semiconductor layers 220 and 240 surrounded by the gates 510, 520, and 530, and a method of manufacturing the same, according to another exemplary embodiment. .

<Description of the symbols for the main parts of the drawings>

100: substrate 200: columnar laminated structure

210, 230, 250: stacked media layers 220, 240: semiconductor layers

300: first etching mask 400, 410, 420: gate insulating film

500, 510, 520, 530: gate 600: interlayer insulating film

700: home filling material 710, 720: partition

800: second etching mask

Claims (19)

At least one semiconductor layer spaced vertically apart from the substrate at a predetermined distance; A gate formed through each of the semiconductor layers with a gate insulating film interposed therebetween on each of the semiconductor layers; A source and a drain formed on both sides of the gate in each of the semiconductor layers; And an interlayer insulating film surrounding the source and the drain of each of the semiconductor layers or filled in an empty space around each of the semiconductor layers. The method of claim 1, A semiconductor device having a star structure, characterized in that the cross section of each of the semiconductor layers through which the gate passes with the gate insulating film interposed therebetween is one of a rectangle, a circle, and an oval. The method of claim 2, When the cross section of each of the semiconductor layers through which the gate passes is a quadrangle, the gate crosses with each of the semiconductor layers on one side or both sides or surrounds all four sides, And the gate passes around the outer circumferential surface of each of the semiconductor layers when the cross section of each of the semiconductor layers through which the gate passes is circular or elliptical. The method of claim 3, wherein The gate insulating layer is a semiconductor device having a star structure, characterized in that the gate crosses with each semiconductor layer when passing through a single-sided structure, when the gate passes around the semiconductor layer is a rectangular or cylindrical structure. The method according to any one of claims 1 to 4, The source and drain are formed at a predetermined depth on any one side, both sides and the outer peripheral surface of each semiconductor layer, the semiconductor device having a star structure, characterized in that the other side or inside the body region is present. In the method of manufacturing a semiconductor device having a star structure of claim 1, After the n &lt; 1 > layer-> semiconductor layer is repeatedly formed n times on a predetermined substrate, the n + 1 &lt; th &gt; Depositing an etch mask material thereon; Patterning the etch mask material and sequentially etching the n + 1 &lt; th &gt; lamination layer &quot; n &quot; semiconductor layer / lamination media &quot; to form the columnar stack structure by using the etching mask material as a first etch mask. A second step; Removing the first etching mask and forming a gate insulating layer on the columnar stacked structure; A fourth step of forming a gate by etching the gate material with a second etching mask after depositing a gate material on the entire surface of the substrate; Removing the gate insulating film exposed by the gate material etching, and then forming a source / drain; And removing the n + 1 layers, and filling the empty space of the exposed structure with the interlayer insulating film. 6. The method of claim 6, And etching the gate material in the fourth step after the planarization process is performed. The method according to claim 6 or 7, The stacking of the stacking media layer and the semiconductor layer is by an epitaxy method, The material of the stacking layer is a semiconductor device manufacturing method having a star structure, characterized in that the lattice structure is similar to the material of the semiconductor layer. The method of claim 8, The method of manufacturing a semiconductor device having a star structure, wherein the source / drain formation of the fifth step is performed by an epitaxial method or a plasma method. The method of claim 9, The material of the substrate and the semiconductor layer is silicon (Si), The material of the stacking layer is silicon germanium (SiGe), The first etching mask material is a nitride (nitride) method of manufacturing a semiconductor device having a star structure, characterized in that. In the method of manufacturing a semiconductor device having a star structure of claim 1, After the n &lt; 1 > layer-> semiconductor layer is repeatedly formed n times on a predetermined substrate, the n + 1 &lt; th &gt; Depositing an etch mask material thereon; Patterning the etch mask material and sequentially etching the n + 1 &lt; th &gt; lamination layer &quot; n &quot; semiconductor layer / lamination media &quot; to form the columnar stack structure by using the etching mask material as a first etch mask. A second step; Depositing a groove filling material on the entire surface of the substrate, and then planarizing the first etching mask to reveal the second etching mask; By using the second etching mask, the groove filling material exposed between the second etching masks is etched to form a partition, and the part of the stacked structure of the second step is exposed to both sides of the partition, and then the second etching mask. Removing the fourth step; A fifth step of etching the laminated layer of the exposed stacked structure to expose only the first etching mask and the semiconductor layer on both sides of the partition; A sixth step of forming a gate insulating film in the semiconductor layer exposed to both sides of the partition; Depositing a gate material on the entire surface of the substrate, and then planarizing the first etching mask to expose the first etching mask, and then removing the first etching mask; An eighth step of removing the partition and forming a source / drain in the semiconductor layer exposed by the partition removal; And a ninth step of filling an empty space of said structure with an interlayer insulating film. The method of claim 11, The groove filling material is a material having the same or similar etching rate as that of the multilayered material, The partition forming process of the fourth step uses anisotropic etching, The method of manufacturing a semiconductor device having a star structure, wherein the stacking layer etching of the fifth step is partially etched using the isotropic etching. The method of claim 12, The forming of the second etching mask in the third step may include making the width of the mask larger than the gap between the masks, or using a slope etch so that the lower width of the mask is larger than the upper width. A method of manufacturing a semiconductor device having a structure. The method of claim 13, Between the fifth step and the sixth step, a step of curving the surface of the semiconductor layer exposed to both sides of the partition is further added. The method of claim 14, The method of manufacturing a semiconductor device having a star structure is characterized in that the surface curvature of the semiconductor layer uses a hydrogen annealing process or an oxidation process and an oxide film etching process. The method according to any one of claims 11 to 15, The source / drain formation of the eighth step is formed on an outer circumferential surface of the semiconductor layer exposed by removing the partition so that a body region exists inside. The method of claim 16, The stacking of the stacking media layer and the semiconductor layer is by an epitaxy method, The material of the stacking layer is a semiconductor device manufacturing method having a star structure, characterized in that the lattice structure is similar to the material of the semiconductor layer. The method of claim 17, The method of manufacturing a semiconductor device having a star structure, wherein the source / drain formation of the eighth step is performed by an epitaxial method or a plasma method. The method of claim 18, The material of the substrate and the semiconductor layer is silicon (Si), The material of the stacking layer and the groove filling material is silicon germanium (SiGe), The first etching mask material is a nitride (nitride) method of manufacturing a semiconductor device having a star structure, characterized in that.

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