KR20100040422A - Pass/fail checking unit of non volatile memory device and programming method using thereof - Google Patents

Abstract

PURPOSE: A pass/fail check part and a programming method thereof are provided to reduce time for a verification operation by successively applying a plurality of check parts and executing a verification operation. CONSTITUTION: A program check unit(310) confirms whether a verification target cell is programmed over a test voltage. A first check unit(320) transfers a voltage delivered from the program check unit to a verification signal output terminal. A second check unit(330) transfers a voltage delivered from the program check unit to the verification signal output terminal. A third check unit(340) transfers the voltage delivered from the program check unit to the verification signal output terminal. The first or the third check unit is connected in parallel between the output terminal of the program check unit and the output terminal of the verification signal output terminal.

Description

Pass / fail checking unit of non volatile memory device and programming method using

The present invention relates to a pass / fail check unit of a nonvolatile memory device and a program method of the nonvolatile memory device using the same.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

Recently, a multi-level cell program method has been applied to such a nonvolatile memory device. That is, a method of programming two or more bits of data in one memory cell. According to the conventional multi-level cell program method, a verification operation for determining whether each cell is programmed in a specified state is performed in addition to the program operation. By this verification operation, it is possible to confirm whether each cell is programmed to a desired state. However, in the multi-level cell program method, since a verification operation based on a plurality of verification voltages is performed, the time required for the verification operation is increased, and thus it is necessary to minimize the verification operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pass / fail check that can reduce the verification time required for a multi-level cell program method of a nonvolatile memory device. The present invention also provides a program method of a nonvolatile memory device using the pass / fail check unit.

According to the above-described object of the present invention, the pass / fail check unit of the nonvolatile memory device of the present invention includes a program check unit for checking whether or not a cell to be verified is programmed to be greater than a verify voltage, and the program check unit in a first verify operation. A first check unit which transmits the transmitted voltage to the verify signal output terminal, a second check unit which transmits the voltage transmitted from the program check unit to the verify signal output terminal in a second verify operation, and the program check in a third verify operation And a third checker configured to transfer the voltage transferred from the unit to the verification signal output terminal.

In addition, the pass / fail check unit of the nonvolatile memory device of the present invention transfers a first voltage to an output node according to data stored in a latch unit included in a second register of a page buffer, and A first check unit configured to transfer a voltage applied to the output node to a verify signal output terminal according to data stored in a latch unit included in a first register; data stored in a latch unit included in a third register of the page buffer; A second check unit which transmits a voltage applied to the output node according to a verification check signal to a verification signal output terminal, and a third check unit which delivers a voltage applied to the output node according to a third verification check signal to a verification signal output terminal. It is characterized by including.

In addition, the program method of the nonvolatile memory device of the present invention comprises the steps of (a) performing a program operation, (b) performing a first verify operation, (c) performing a second verify operation; (d) performing a third verifying operation, (e) performing a first pass / fail check operation, and (f) performing all of the first verifying cells until it is confirmed that all of the first verification target cells have passed. repeating ˜e), (g) performing the steps (a, c, d) if all of the first cells to be verified are passed, and (h) the second pass / fail Performing a check operation, (i) repeating the steps (g, h) until it is confirmed that all of the second verification target cells have passed, and (j) all of the second verification target cells Performing the steps (a, d) when it is determined that the device has passed, (k) performing a third pass / fail check operation; (l) repeating the above steps (j, k) until all of the third cells to be verified are passed.

According to the configuration of the present invention described above, the verification operation which is confirmed that the verification has already been completed among the verification operations may not be performed, thereby reducing the time required for the verification operation during the entire program operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a view for explaining the concept of a multi-level cell program method of a conventional nonvolatile memory device.

The multi-level cell program method illustrates a 2-bit multi-level cell program method. According to the operation of the lower bit program LSB, two distributions having different threshold voltages are formed. The single level cell program method stores one bit of data in each memory cell only with this lower bit program operation.

When the upper bit program (MSB) operation is performed on the distribution, four distributions having different threshold voltages are formed. Therefore, four different states, that is, two bits of data, can be stored in each memory cell. At this time, the distribution of cells having the lowest threshold voltage is larger than the first state and the first verification voltage PV1 and lower than the second verification voltage PV2. The distribution of cells programmed to be larger and lower than the third verify voltage PV3 is called the third state, and the distribution of cells programmed to be greater than the third verify voltage PV3 is called the fourth state.

According to the conventional multi-level cell program method, a verification operation for determining whether each cell is programmed in a specified state is performed in addition to the program operation. By this verification operation, it is possible to check whether each cell is programmed to a desired state. However, in the multi-level cell program method, since a verification operation based on a plurality of verification voltages is performed, the time required for the verification operation is increased, and thus it is necessary to minimize the verification operation.

2 is a circuit diagram illustrating a page buffer of a nonvolatile memory device according to the present invention.

The page buffer 200 includes a bit line selection unit 210, a bit line sensing unit 212, a sense node precharge unit 214, a sense node sensing unit 216, a first register 220, and a second register. 230, a third register 240, and a pass / fail check unit 250.

The bit line selector 210 may include an NMOS transistor N215 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal The NMOS transistor N217 connects the odd bit line BLo and the sensing node SO in response to BSLo. In addition, the bit line selector 210 connects the even bit line BLe and the variable voltage input terminal in response to a variable voltage input terminal for applying a variable level VIRPWR of a specific level and a first discharge signal DISCHe. NMOS transistor N211 and an NMOS transistor N213 connecting the odd bit line BLo and a variable voltage input terminal in response to a second discharge signal DISCHo. According to the above configuration, a specific bit line and a sensing node may be selectively connected.

The bit line sensing unit 212 is turned on in response to the bit line sensing signal PBSENSE and includes the NMOS transistor N212 connected to the bit line selecting unit 210 and the sensing node SO. In the verify / read operation, a sensing voltage is applied to transmit a state of a specific memory cell to the sensing node. In some embodiments, the bit line sensing unit 212 may be removed, and the bit line selection transistors N215 and N217 of the bit line selecting unit 210 may perform the same operation.

The sensing node precharge unit 214 applies a high level voltage VDD to the sensing node SO in response to a precharge signal Prechb. To this end, it includes a PMOS transistor (P214) connected between the power supply voltage terminal (VDD) and the sensing node. Therefore, a high level power supply voltage is applied to the sensing node SO in response to a low level precharge signal.

The sensing node sensing unit 216 applies a ground voltage to each of the resistors 220, 230, and 240 according to the voltage level of the sensing node. To this end, the sensing node includes an NMOS transistor N216 connected to the gate and connected between each resistor and the ground terminal. Therefore, the ground voltage is applied to each register according to the voltage level of the sensing node.

The first register 220 transfers the ground voltage transmitted from the ground voltage supply unit 216 to the latch unit 222 according to the latch unit 222 in which data is stored and the data setting signals CRST and CSET. The data setting unit 226 includes a data transmission unit 224 transferring data stored in the first node QC_N of the latch unit 222 to the sensing node SO.

The latch unit 222 includes a first inverter IV222 and a second inverter IV223 in which an input terminal and an output terminal are connected to each other. The connection node of the output terminal of the first inverter IV222 and the input terminal of the second inverter IV223 is called the first node QC_N, and the input terminal of the first inverter IV222 and the output of the second inverter IV223 The connection node of the terminal is called a second node QC. Therefore, the data of opposite levels are stored in the first node QC_N and the second node QC.

The data setting unit 226 applies an ground voltage transmitted from the ground voltage supply unit 216 to the first node QC_N according to a first data setting signal CSET, and second data. The NMOS transistor N226 may be configured to apply the ground voltage transmitted from the ground voltage supply unit 216 to the second node QC according to a setting signal CRST.

The data transmitter 224 includes an NMOS transistor N224 that transfers data stored in the first node QC_N of the latch unit 222 to the sensing node SO according to a data transmission signal TRAN. . Accordingly, data stored in the first node QC_N may be transmitted to the sensing node according to the application of the data transmission signal TRAN.

The second register 230 transmits the ground voltage transmitted from the ground voltage supply unit 216 to the latch unit 232 according to the latch unit 232 in which data is stored and the data setting signals MRST and MSET. The data setting unit 236 includes a data transmitter 234 for transferring data stored in the first node QM_N of the latch unit 232 to the sensing node SO.

The latch unit 232 includes a first inverter IV232 and a second inverter IV233 having input terminals and output terminals connected to each other. The connection node of the output terminal of the first inverter IV232 and the input terminal of the second inverter IV233 is called the first node QM_N, and the input terminal of the first inverter IV232 and the output of the second inverter IV233 The connection node of the terminal is called a second node QM. Therefore, the data of opposite levels are stored in the first node QM_N and the second node QM.

The data setting unit 236 applies the ground voltage transmitted from the ground voltage supply unit 216 to the first node QM_N according to a first data setting signal MSET, and second data. The NMOS transistor N236 applies a ground voltage transmitted from the ground voltage supply unit 216 to the second node QM according to a set signal MRST.

The data transmitter 234 includes an NMOS transistor N234 for transferring data stored in the first node QM_N of the latch unit 232 to the sensing node SO according to a data transmission signal TRANM. . Accordingly, data stored in the first node QM_N may be transmitted to the sensing node according to the application of the data transmission signal TRAN.

The third register 240 transfers the ground voltage transmitted from the ground voltage supply unit 216 to the latch unit 242 according to the latch unit 242 in which data is stored and the data setting signals TRST and TSET. The data setting unit 246 includes a data transmission unit 244 for transferring data stored in the first node QT_N of the latch unit 242 to the sensing node SO.

The latch unit 242 includes a first inverter IV242 and a second inverter IV243 in which an input terminal and an output terminal are connected to each other. The connection node of the output terminal of the first inverter IV242 and the input terminal of the second inverter IV243 is called the first node QT_N, and the input terminal of the first inverter IV242 and the output of the second inverter IV243 are represented. The connection node of the terminal is called a second node QT. Therefore, the data of opposite levels are stored in the first node QT_N and the second node QT.

The data setting unit 246 applies the ground voltage transmitted from the ground voltage supply unit 216 to the first node QT_N according to a first data setting signal TSET, and second data. The NMOS transistor N246 applies a ground voltage transmitted from the ground voltage supply unit 216 to the second node QT according to a setting signal TRST.

The data transmitter 244 may transfer the data stored in the first node QT_N of the latch unit 242 to the sensing node SO according to a first data transmission signal TRANT, The NMOS transistor N244 transfers the data stored in the second node QT of the latch unit 242 to the sensing node SO according to the second data transmission signal TRANT_N. Accordingly, the data stored in the specific nodes QT and QT_N of the latch unit 242 may be transmitted to the sensing node SO according to the application of the data transmission signals TRANT and TRANT_N.

The pass / fail check unit 250 is data stored in the first node QC_N of the latch unit 222 included in the first register 220, and the latch unit 232 included in the second register 230. Data stored in the second node QM of FIG. 8), data stored in the first node QT_N of the latch unit 242 included in the third register 240, a second verification check signal PV2CHECK, and third verification. According to the check signal PV3CHECK, a pass / fail check is performed in each verification operation.

Before describing the detailed configuration, a program operation / verification operation using the page buffer will be described.

division QC_N QM_N QT_N First state One One One Second state One 0 0 Third state 0 0 One 4th state 0 0 0

As shown in Table 1, the data stored in the first node of each latch unit differs depending on the input data, that is, the state to be programmed. In this case, the program operation is performed according to the data stored in the first node QM_N of the latch unit 232 included in the second register 230. That is, it is a program target only when '0' data is stored in the node. In addition, when the verification target cell is programmed above the specific verification voltage during the verification operation, the ground voltage is applied through the sensing node sensing unit 216, and accordingly, the data stored in the first node QM_N is '1'. Is changed to

The data of the latch unit included in the first register and the third register serves to block the verification operation based on the remaining verification voltage when the verification operation based on the specific verification voltage is performed.

In the first verify operation based on the first verify voltage PV1, when the cells to be programmed to the second state are programmed to be greater than or equal to the first verify voltage PV1, '0' stored in the first node QM_N is stored. Change the data to '1' data. However, since the cells to be programmed to the third state and the fourth state will also have a larger threshold voltage than the first verify voltage PV1, '0' data stored in the first node QM_N by the first verify operation is '1'. Can be changed to data. However, once the data stored in the first node QM_N is changed once, no further program pulse is applied to the target node, so that the program cannot be programmed to the target state. Therefore, the first verification operation should be blocked for these cells. To this end, data stored in the latch unit 222 of the first register is used. In the verifying operation, an operation of precharging the sensing node to a high level by using the sensing node precharge unit 214 is performed. In this operation, a program is applied to the third state and the fourth state by applying the data transmission signal TRAN. Ground the sensing node SO connected to the cells to be grounded. Since '0' data is stored in the latch unit 222 of the first register of cells to be programmed to the third and fourth states, the sensing node SO is grounded when the data transmission signal TRAN is applied. do. Therefore, the sensing node SO of the cells to be programmed to the third state and the fourth state is maintained in the ground state so that the sensing node sensing unit 216 does not operate and data stored in the latch unit 232 of the second register is stored. It does not change.

Similarly, in the second verify operation based on the second verify voltage PV2, when the cells to be programmed to the third state are programmed to be greater than or equal to the second verify voltage PV2, the second verify operation PV ′ is stored in the first node QM_N. 0 'data is changed to' 1 'data. However, since the cells to be programmed to the fourth state also have a threshold voltage greater than the second verify voltage PV2, '0' data stored in the first node QM_N may be changed to '1' data by the second verify operation. Can be. To block this, data stored in the latch unit 242 included in the third register is used. Since '0' data is stored in the first node QT_N of the latch unit 242 of the third register of cells to be programmed to the fourth state, when the data transmission signal TRANT is applied, the sensing node SO The earth is grounded. Accordingly, the sensing node SO of the cells to be programmed to the fourth state is maintained in the ground state so that the sensing node sensing unit 216 does not operate and the data stored in the latch unit 232 of the second register is not changed.

When the first verification operation is performed as described above, the data transmission signal TRAN is applied to block the verification operation for the cells to be programmed in the third state and the fourth state, and the second verification operation is performed. In this case, the data transmission signal TRANT is applied to block the verification operation for the cells to be programmed in the fourth state.

Now, a detailed configuration of the pass / fail check unit 250 will be described.

3 is a circuit diagram illustrating a pass / fail check unit of a nonvolatile memory device according to an embodiment of the present invention.

The pass / fail check unit 250 is connected in parallel between the program check unit 310 and the program check unit 310 and the verify signal output terminal PBVER to check whether the cell to be verified has been programmed above the verify voltage. The first check unit 320, the second check unit 330, and the third check unit 340 may be configured to perform a pass / fail check operation only for a specific verification operation.

First, the program check unit 310 is turned on according to data stored in the second node QM of the latch unit 232 included in the second register, and is connected to the ground terminal and the first node N1. The transistor N310 is included. As described above, the latch unit 232 of the second register stores data regarding whether the corresponding cell is programmed above a specific verify voltage. That is, when '1' data is stored in the first node QM_N of the latch unit 232 when the first verification operation for checking whether the programmed voltage is greater than or equal to the first verification voltage is performed, the corresponding cell is programmed. Will be judged. That is, when '0' data is stored in the second node QM, it is determined that the corresponding cell is completed. When '0' data is stored in the second node QM, since the corresponding transistor N310 is turned off, the ground voltage is not applied to the verification signal PBVER output terminal, and thus the verification signal output terminal is in a floating state. . However, when '1' data is stored in the second node QM because the program is not completed, the corresponding transistor N310 is turned on, so that the first check unit 320, the second check unit 330, or the third check is performed. The ground voltage is applied to the verification signal PBVER output terminal through the unit 340. In this case, when the entire verification signal PBVER output terminal is in the floating state, it is determined that the verification operation is completed.

The first check unit 320 is turned on according to the data stored in the first node QC_N of the latch unit 222 included in the first register, and the first node N1 and the verification signal PBVER. And an NMOS transistor N320 connected between output terminals. Accordingly, the NMOS transistor N320 is turned on only when '1' data is stored in the first node QC_N of the latch unit 222, that is, in a case of cells intended for a first state and a second state.

After performing the first to third verification operations, when performing a pass / fail check operation, only the first check unit 320 operates first. That is, based on the data stored in the latch unit 230 of the second register of the cells to be programmed to the second state, the first check whether the cells to be programmed to the second state are all programmed above the first verification voltage. Performs a pass / fail check operation. Since the remaining check units 330 and 340 are blocked by data stored in the first node QC_N, a pass / fail check for the first verification operation is possible. At this time, when all the cells to be programmed to the second state are programmed to be greater than or equal to the first verification voltage, the program check unit 310 is cut off so that the verification signal output terminal is in a floating state. When the floating state is reached, the first verifying operation is considered to be completed, and in the subsequent operation, the first verifying operation is no longer performed. In addition, a second pass / fail check operation is performed to confirm whether all the cells to be programmed to the third state are programmed to the second verification voltage or higher.

Meanwhile, in the case of cells intended for the first state, since '0' data is stored in the second node QM of the latch unit 232, the program check unit (regardless of the threshold voltage state of the cells) may be used. 310 is blocked.

 The second check unit 330 is stored in the first NMOS transistor N330 turned on according to the second verification check signal PV2CHECK and in the first node QT_N of the latch unit 242 included in the third register. The second NMOS transistor N332 is turned on according to the data. In this case, the first NMOS transistor N330 and the second NMOS transistor N332 are connected in series between the first node N1 and the output terminal of the verification signal PBVER.

In the second pass / fail check operation for confirming whether all cells to be programmed to the third state are programmed to be greater than or equal to the second verification voltage, based on the data stored in the first node QT_N of the latch unit 242. The blocking of the second check unit 330 may be controlled. That is, '1' data is stored in the first node QT_N in the cell to be programmed to the third state, and '0' data is stored in the first node QT_N in the cell to be programmed to the fourth state. Since it is stored, it can be used to control whether the second checker 330 is blocked. However, since the operation of the second check unit 330 should be blocked when the first verify operation or the third verify operation is performed, the first NMOS transistor N330 turned on according to the second verify check signal PV2CHECK is added. . Therefore, when the second verification check signal PV2CHECK is applied, the second verification operation may be performed only on cells in which '1' data is stored in the first node QT_N. When the second pass / fail check operation is performed, only the second check unit 330 operates, and when all of the cells to be programmed to the third state are programmed to have a second verification voltage or higher, the program check unit 310 is all The verification signal output terminal is cut off to become a floating state. When the floating state is reached, the second verifying operation is considered to be completed, and in the subsequent operation, the second verifying operation is no longer performed. In addition, a third pass / fail check operation is performed to confirm whether all cells to be programmed to the fourth state are programmed to the third verification voltage or higher.

The third checker 340 is turned on according to a third verification check signal PV3CHECK and includes an NMOS transistor N340 connected between the first node N1 and the output signal of the verification signal PBVER.

When performing the third pass / fail check operation for confirming whether all cells to be programmed to the fourth state are programmed above the third verification voltage, the first pass / fail check operation and the second pass / fail check operation in the foregoing operation are performed. In the first node QM_N of the latch unit 232 included in the second register of cells other than the cell to be programmed to the fourth state, all of the '1' data are stored. Accordingly, the third pass / fail check operation may be performed according to the third verification check signal PV3CHECK regardless of data stored in the latch unit of the first register and the latch unit of the third register.

 When the third pass / fail check operation is performed, only the third check unit 340 operates, and when all of the cells to be programmed in the fourth state are programmed to the third verification voltage or higher, the program check unit 310 performs all The verification signal output terminal is cut off to become a floating state. When the floating state is reached, the third verifying operation is considered to be completed.

Now, the sequence of the program method of the present invention will be described.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, a program operation is performed (step 410).

The program method repeatedly performs a program operation by adding a step voltage Vstep to a program start voltage Vstart according to an ISPP (Incremental step pulse program) program method. The verification operation is performed before further applying the step voltage. Meanwhile, the program method corresponds to an upper bit program method in a 2-bit multi-level cell program method.

Next, the first to third pass / fail check states are checked and a verification operation is performed according to the result (steps 420, 430, 440, 450). The check result is determined by storing the result of the pass / fail check unit of FIG. 3.

If there is a failed cell among the first verification target cells as a result of the pass / fail check, the first verify operation, the second verify operation, and the third verify operation are performed, and the first pass / fail check operation is performed (step 420, 430, 440, 450, 460).

As a result of the pass / fail check, when all of the first verification target cells are passed but there are failed cells among the second verification target cells, the second verification operation and the third verification operation are performed, and the second pass / fail check operation is performed. (Steps 420, 440, 450, 460).

As a result of the pass / fail check, when the second verification target cells are all passed but there are failed cells among the third verification target cells, the third verification operation is performed and the third pass / fail check operation is performed (steps 420 and 450). , 460).

If it is determined that all of the cells to be verified in the third pass have been passed as a result of the pass / fail check, that is, it is determined that all of the cells to be programmed to the fourth state are programmed to be higher than or equal to the third verify voltage, the upper bit program operation ends (step). 420).

On the other hand, when the program operation is repeated, the operation of increasing the program voltage by the step voltage is performed (step 470).

5 is a flowchart illustrating a program method of a nonvolatile memory device according to another exemplary embodiment of the present invention.

First, a program operation is performed (step 510).

The program method repeatedly performs a program operation by adding a step voltage Vstep to a program start voltage Vstart according to an ISPP (Incremental step pulse program) program method. The verification operation is performed before further applying the step voltage. Meanwhile, the program method corresponds to an upper bit program method in a 2-bit multi-level cell program method.

Next, a verification operation is performed according to the first to third pass / fail check results (steps 520, 530, and 540). The check result is determined by storing the result of the pass / fail check unit of FIG. 3.

If the third pass / fail check determines that all of the third verification target cells have passed, that is, it is determined that all of the cells to be programmed to the fourth state have been programmed above the third verification voltage, the higher bit program operation is terminated. (Step 520).

If there is a failed cell as a result of the check, the second pass / fail check result is checked (step 520). If the second pass / fail check determines that all of the second verification target cells have passed, that is, if it is determined that all of the cells to be programmed to the third state are programmed above the second verification voltage, the third verification operation is performed. A third pass / fail check operation is performed (steps 520, 530, 532, 534).

If there is a failed cell as a result of the second pass / fail check, the first pass / fail check result is checked (steps 520 and 540). If the first pass / fail check determines that all of the first cells to be verified have passed, that is, if the cells to be programmed to the second state are all programmed to be greater than or equal to the first verification voltage, the second verification operation is performed. The second pass / fail check operation is performed (steps 520, 530, 540, 542, 544, and 546).

If there is a failed cell as a result of the first pass / fail check, a first verify operation, a second verify operation, and a third verify operation are performed, and a first pass / fail check operation is performed (steps 520, 530, and 540). , 550, 552, 554, 556).

However, when the first program pulse is applied, the pass / fail check result is initialized, and according to the initial value, the first verification operation is sequentially performed from the first verification operation to the third verification operation. The first verification operation is an operation of checking whether the first verification target cells are programmed to be greater than or equal to the first verification voltage PV1 (step 550). In this case, as described above, the first and second verification target cells are blocked by the data stored in the latch unit included in the first register.

The second verification operation is an operation of checking whether the second verification target cells are programmed to be greater than or equal to the second verification voltage PV2 (steps 552 and 542). In this case, as described above, the third verification target cells are blocked by the second verification operation by the data stored in the latch unit included in the third register.

The third verifying operation is an operation of checking whether the third verifying cells are programmed to be greater than or equal to the third verifying voltage PV3 (steps 554, 544, and 532).

After the third verification operation is performed, the program operation is repeated by increasing the program voltage by the step voltage (step 560).

Meanwhile, each pass / fail check operation is performed as described above.

That is, the first pass / fail check operation blocks the operations of the second check unit 330 and the third check unit 340 of the pass / fail check unit 250 and uses only the first check unit 320. Perform (step 556). The second pass / fail check operation is performed by operating only the second check unit 330 of the pass / fail check unit 250 (step 546). The third pass / fail check operation is performed by operating only the third check unit 340 of the pass / fail check unit 250 (step 534).

According to such an operation, the specific verification operation may be completed first according to the pass / fail check result, thereby minimizing the time required for the verification operation. That is, if it is determined that the result of the first pass / fail check operation is passed, the first verification operation is not performed thereafter. In addition, if it is determined that the result of the second pass / fail check operation is passed, the second verification operation is not performed thereafter. In addition, if it is determined that the result of the third pass / fail check operation is passed, the program operation is completed.

6 is a view for explaining the concept of a program method of a nonvolatile memory device according to an embodiment of the present invention.

4 or 5 clearly shows the program method. That is, after the first program pulse is applied, all of the first verify operation, the second verify operation, and the third verify operation are performed.

Next, a first pass / fail check operation is performed.

If this operation is repeatedly performed and the first pass / fail check determines that the first verification operation is completed, only the second verification operation and the third verification operation are performed without performing the first verification operation. Similarly, if the operation is repeatedly performed and the second pass / fail check determines that the second verification operation is completed, only the third verification operation is performed without performing the second verification operation.

According to this configuration, each verification operation is not continuously executed until the upper bit program is completed, and specific verification operations can be selectively omitted according to the pass / fail check results, thereby minimizing the time required for verification operations. Can be.

1 is a view for explaining the concept of a multi-level cell program method of a conventional nonvolatile memory device.

2 is a circuit diagram illustrating a page buffer of a nonvolatile memory device according to the present invention.

3 is a circuit diagram illustrating a pass / fail check unit of a nonvolatile memory device according to an embodiment of the present invention.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

5 is a flowchart illustrating a program method of a nonvolatile memory device according to another exemplary embodiment of the present invention.

6 is a view for explaining the concept of a program method of a nonvolatile memory device according to an embodiment of the present invention.

<Description of main parts of drawing>

250: Pass / fail check

310: program check unit

320: first check unit

330: second check unit

340: third check unit

Claims (23)

A program check unit which checks whether or not the cell to be verified has been programmed above the verification voltage; A first check unit for transferring a voltage transmitted from the program check unit to a verify signal output terminal during a first verify operation; A second check unit for transferring a voltage transmitted from the program check unit to a verify signal output terminal during a second verify operation; And a third checker configured to transfer a voltage transmitted from the program checker to a verify signal output terminal during a third verifying operation. 2. The pass / fail check unit of claim 1, wherein the first to third check units are connected in parallel between an output terminal of the program check unit and the verification signal output terminal. The nonvolatile memory device of claim 1, wherein the program checker transfers a ground voltage to the first to third checkers according to data stored in a second node of a latch included in a second register of a page buffer. Pass / fail check The nonvolatile memory device of claim 1, wherein the first check unit connects the program check unit and the verify signal output terminal according to data stored in a first node of a latch unit included in a first register of a page buffer. Pass / fail check. The method of claim 1, wherein the second check unit connects the program check unit and the verify signal output terminal according to data stored in a first node of a latch unit included in a second register and a third register of a page buffer. Pass / fail check of nonvolatile memory device. The pass / fail check unit of claim 1, wherein the third check unit connects the program check unit and the verify signal output terminal according to a third verify check signal. The method of claim 1, wherein the program check unit is turned on according to data applied to a second node of a latch unit included in a second register of a page buffer, and includes an NMOS transistor connected between a ground terminal and the respective check units. A pass / fail check unit of a nonvolatile memory device. The NMOS transistor of claim 1, wherein the first check unit is turned on according to data applied to a first node of a latch unit included in a first register of a page buffer, and is connected between an output terminal of the program check unit and the verification signal output terminal. A pass / fail check unit of a nonvolatile memory device comprising a. The display device of claim 1, wherein the second check unit comprises: a first NMOS transistor turned on according to a second verify check signal; A second NMOS transistor turned on according to data stored in a first node of a latch unit included in a third register of the page buffer; And the first NMOS transistor and the second NMOS transistor are connected in series between an output terminal of the program check unit and the verification signal output terminal. The nonvolatile memory device of claim 1, wherein the third check unit comprises an NMOS transistor that is turned on according to the third verify check signal and is connected between an output terminal of the program check unit and the verify signal output terminal. Pass / fail check. A program check unit for transmitting a first voltage to an output node according to data stored in a latch unit included in a second register of a page buffer; A first check unit configured to transfer a voltage applied to the output node to a verify signal output terminal according to data stored in a latch unit included in a first register of the page buffer; A second check unit configured to transfer a voltage applied to the output node to a verify signal output terminal according to data stored in a latch unit included in a third register of the page buffer and a second verify check signal; And a third checker configured to transfer a voltage applied to the output node to a verifying signal output terminal according to a third verifying check signal. The method of claim 11, wherein the program check unit is turned on according to the data applied to the second node of the latch unit included in the second register, characterized in that it comprises an NMOS transistor connected between the ground terminal and the output node. Pass / fail check of nonvolatile memory device. 12. The method of claim 11, wherein the first check unit is turned on according to the data applied to the first node of the latch unit included in the first register, and comprises an NMOS transistor connected between the output node and the verification signal output terminal. A pass / fail check unit of a nonvolatile memory device. The semiconductor device of claim 11, wherein the second check unit comprises: a first NMOS transistor turned on according to the second verify check signal; A second NMOS transistor turned on according to data stored in a first node of a latch unit included in the third register; And the first NMOS transistor and the second NMOS transistor are connected in series between the output node and a verify signal output terminal. The pass / fail of the nonvolatile memory device of claim 11, wherein the third check unit comprises an NMOS transistor turned on according to the third verify check signal and connected between the output node and a verify signal output terminal. Check. (a) performing a program operation; (b) performing a first verify operation; (c) performing a second verify operation; (d) performing a third verify operation; (e) performing a first pass / fail check operation; (f) repeating the steps (a) to (e) until all of the first cells to be verified are passed; (g) performing the steps (a, c, d) when all of the first cells to be verified are passed; (h) performing a second pass / fail check operation; (i) repeating the steps (g, h) until all of the second cells to be verified are passed; (j) performing steps (a, d) when it is confirmed that all of the second verification target cells have passed; (k) performing a third pass / fail check operation; (l) repeating the steps (j, k) until all of the third cells to be verified are passed. 17. The nonvolatile method as claimed in claim 16, wherein the performing of the first verifying operation includes blocking the performing of the first verifying operation on the second verifying cell and the third verifying cell. Program method of memory device. 17. The nonvolatile method as claimed in claim 16, wherein the performing of the second verifying operation comprises: performing the third verifying operation on the first verification target cell and the third verification target cell to be blocked. Program method of memory device. 17. The nonvolatile method as claimed in claim 16, wherein the performing of the third verifying operation includes blocking the performing of the third verifying operation on the first verification target cell and the second verification target cell. Program method of memory device. The method of claim 16, wherein the performing of the first pass / fail check operation comprises: operating a first check part of the pass / fail check part according to data stored in a first node of a latch part included in a first register of a page buffer. Program method of a nonvolatile memory device comprising a. The method of claim 16, wherein the performing of the second pass / fail check operation comprises: applying a second verification check signal to a pass / fail check unit;  And operating the second check unit of the pass / fail check unit according to data stored in the first node of the latch unit included in the third register of the page buffer. 17. The method of claim 16, wherein performing the third pass / fail check operation comprises applying a third verify check signal to a pass / fail check unit. 17. The method of claim 16, wherein each repeating step (f, i, l) comprises increasing a program voltage by a step voltage.

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