KR20100039485A - Internal voltage converter for multiple power supply and internal power supplying device including the same, semiconductor device including the internal voltage converter for multiple power supply - Google Patents

Abstract

The multiple internal voltage converters include a comparator, an output circuit and a feedback circuit. The comparator compares one of the plurality of internal voltages with a reference voltage. The output circuit receives the comparison value and the external voltage of the comparator, selectively generates one of the plurality of internal voltages in response to a control signal, and supplies the internal voltage to the internal circuit. The feedback circuit feeds back the output internal voltage to the comparator.

Description

Multiple Internal Voltage Converters and Internal Power Supply and Semiconductor Devices Including Them {

The present invention relates to a voltage conversion and power supply technology, and more particularly to an internal power supply technology of a semiconductor device.

As the degree of integration of a semiconductor device increases, the size of the MOS transistor also decreases, and if the external voltage is used as it is, the reliability of the MOS transistor may be deteriorated. Therefore, it is common to lower the external power supply voltage inside the chip. If internal voltage is used as constant voltage, stable internal voltage can be secured even if external voltage fluctuates. The internal voltage needs to supply a constant voltage inside the chip for normal operation of the chip even with temperature changes or external voltage fluctuations, and a stable voltage must be supplied even with rapid current changes in the load portion.

In the case of an internal power supply that supplies internal voltages to various functional blocks in the chip, internal voltage converters may be supplied through separate internal voltage converters to prevent noise from inducing a difference in power characteristics of each functional block or noise. do. In the case of a semiconductor memory device, internal voltage converters and power supply lines separated from each other are used to prevent noise of power supplied to an input / output device such as an input buffer or an output buffer from flowing into power supplied to a memory cell or a peripheral circuit. In this case, however, the internal circuit powered by one internal voltage converter is fixed, making it difficult to flexibly cope with changes in the power demand of the internal functional blocks.

Accordingly, an object of the present invention is to provide an internal power supply device that performs efficient power supply by using multiple internal voltage converters for selectively supplying internal voltages to one or more internal circuits.

An object of the present invention is to provide an internal power supply device that performs efficient power supply by controlling according to the power requirements of the internal circuit by using a plurality of internal voltage converters selectively supplying the internal voltage to one or more internal circuits.

The multiple internal voltage converter according to an embodiment of the present invention includes a comparator, an output circuit, and a feedback circuit. The comparator compares one of the plurality of internal voltages with a reference voltage. The output circuit receives a comparison value and an external voltage of the comparator, selectively generates one of the plurality of internal voltages in response to a control signal, and supplies the same to an internal circuit. The feedback circuit feeds back the output internal voltage to the comparator.

The output circuit may include a plurality of load units selectively activated in response to the control signal and outputting one of the plurality of internal voltages based on a comparison value of the comparator and the external voltage.

Each of the plurality of load units may include a first MOS transistor and a second MOS transistor. The first MOS transistor may be biased by a comparison value of the comparator to output one of the plurality of internal voltages. The second MOS transistor may activate or deactivate the first MOS transistor in response to the control signal.

The feedback circuit may include a multiplexer. The multiplexer may provide the output internal voltage to the comparator by connecting the activated load part to the comparator in response to the control signal.

The comparison unit may include a differential amplifier circuit that receives the reference voltage and the output internal voltage and outputs a value corresponding to the voltage difference.

An internal power supply apparatus according to an embodiment of the present invention includes multiple internal voltage converters and a controller. The multiple internal voltage converters generate one of a plurality of internal voltages in response to a control signal and selectively supply some of the plurality of internal circuits. The controller controls a power supply direction of the multiple internal voltage converters according to power information of the plurality of internal circuits.

The power information may include a required power amount and a supply power amount of the plurality of internal circuits.

The controller may include a power amount determiner and an adjuster. The power amount determiner may determine a required power amount and a supply power amount of the plurality of internal circuits. The controller may control a supply direction of the multiple internal voltage converters according to a required power amount and a supply power amount of the plurality of internal circuits.

A semiconductor device according to an embodiment of the present invention includes a memory cell array, an input / output circuit, and an internal power supply device. The memory cell array stores data. The input / output circuit inputs and outputs the data. The internal power supply includes multiple internal voltage converters. The multiple internal voltage converter generates an internal voltage in response to a control signal and selectively supplies the internal voltage to any one of the memory cell array and the input / output circuit.

The multiple internal voltage converter may supply the internal voltage to an input / output circuit when the semiconductor device performs a data read operation, and supply the internal voltage to a memory cell array when the semiconductor device performs a data write operation.

According to the present invention, an internal voltage can be selectively supplied to a plurality of internal circuits by using multiple internal voltage converters, thereby controlling power supply direction according to an operating state of a semiconductor device to efficiently distribute power to the plurality of internal circuits. In addition, even if the power supply capability of some internal voltage converters is insufficient, power distribution can be controlled to stably supply power to internal circuits.

Hereinafter, a method of manufacturing a semiconductor device in accordance with embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and has ordinary skill in the art. It will be apparent to those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit of the invention.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, when an embodiment is otherwise implemented, a function or operation specified in a specific block may occur out of the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, and the blocks may be performed upside down depending on the function or operation involved. Like reference numerals in the drawings denote like elements.

1 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, the semiconductor device 100 includes an internal power supply 110, an input circuit 120, a peripheral circuit 130, a memory cell array 140, and an output circuit 150. The internal power supply 110 is selectively internal to some of a plurality of internal circuits such as the input circuit 120, the peripheral circuit 130, the memory cell array 140, the output circuit 150, and the like in response to the control signal. It includes multiple internal voltage converters for supplying voltage. In one embodiment, when the peripheral circuit 130 and the memory cell array 140 form a first internal circuit, and the input circuit 120 and the output circuit 150 form a second internal circuit, multiple internal voltages The converter can selectively supply the internal voltage to the first internal circuit and the second internal circuit. The first internal circuits 130 and 140 and the second internal circuits 120 and 150 may be supplied with power through power supply lines separated from each other to prevent the inflow of noise. The semiconductor device 100 may be a memory device such as a DRAM or an SRAM.

2 is a block diagram illustrating an internal power supply 110 according to an embodiment of the present invention.

2, an internal power supply 110 according to an embodiment of the present invention includes at least one multiple internal voltage converters 231 and 232.

The multiple internal voltage converters 231 and 232 generate one of the plurality of internal voltages in response to the control signal and selectively supply some of the plurality of internal circuits. In one embodiment, the multiple internal voltage converters 231 and 232 supply the first internal voltage VINT to the first internal circuit or the second internal voltage VINTIO to the second internal circuit in response to the control signal.

The internal power supply 110 may further include internal voltage converters 211, 212, 213, 214, 221, and 222 which supply an internal voltage only to a predetermined internal circuit. For example, the first internal voltage converters 211, 212, 213, and 214 generate and supply the first internal voltage VINT corresponding to the reference voltage to the first internal circuit of the semiconductor device, and the second internal voltage converter. 221 and 222 may generate a second internal voltage VINTIO corresponding to the reference voltage and supply the second internal voltage VINTIO to the second internal circuit through a power supply line separated from the first internal voltage converter. According to an embodiment, the number of the multiple internal power transformers 231 and 232, the first internal voltage converters 211, 212, 213 and 214 and the second internal voltage converters 221 and 222 may be adjusted.

The first internal voltage VINT and the second internal voltage VINTIO may have the same level of voltage, but may be provided to the internal circuit through separate power supply lines.

The first internal circuit may include a peripheral circuit and a memory cell array, and the second internal circuit may include input / output circuits such as an input buffer and an output buffer.

The multiple internal voltage converters 231 and 231 may select an internal circuit to which power is supplied according to control signals WRITE and READ, unlike a general internal voltage converter supplying power to a predetermined internal block. Therefore, the power supply direction can be switched according to the amount of power required in the internal circuit, thereby enabling efficient internal power supply. The multiple internal voltage converters 231 and 232 may be selectively connected to two or more power supply lines connected to the internal circuits according to the control signals WRITE and READ to supply more power to the internal circuits that lack power. .

In one embodiment, in the data read operation of the semiconductor memory device, the second internal circuit including the output circuit requires relatively more power to drive the output driver, and in the data write operation, less power than in the data read operation. You may need In this case, the control signals WRITE and READ are set to the first internal power activation mode to supply the first internal voltage VINT to the first internal circuit including the memory cell array, or to supply the control signals WRITE and READ. The power supply direction of the multiple internal voltage converters may be controlled by supplying the second internal voltage VINTIO to the second internal circuit including the input / output circuit by setting the second internal power activation mode. That is, the multiple internal voltage converters 231 and 231 supply power to the second internal circuit that requires relatively high power in the data read operation, and switch the power supply direction to the first internal circuit in the data write operation. Power can be provided to ensure efficient power distribution.

3 is a circuit diagram illustrating a multiple internal voltage converter 231 according to an embodiment of the present invention.

Referring to FIG. 3, the multiple internal voltage converter 231 includes a comparator 310, an output circuit 320, and a feedback circuit 330.

The comparator 310 compares one of the plurality of internal voltages VINT and VINTIO with the reference voltage VREF. That is, the voltage difference between the reference voltage VREF and the first internal voltage VINT or the voltage difference between the reference voltage VREF and the second internal voltage VINTIO is compared.

The output circuit 320 receives the comparison value DG and the external voltage VEXT of the comparator 310 and receives one of the plurality of internal voltages VINT and VINTIO in response to the control signals WRITE and READ. Optionally generated and fed into the internal circuit. That is, in response to the control signals WRITE and READ, the first internal voltage VINT is generated and supplied to the first internal circuit or the second internal voltage VINTIO is generated and supplied to the second internal circuit.

The output circuit 320 is selectively activated in response to the control signals WRITE and READ, and generates one of the plurality of internal voltages based on the comparison value DG and the external voltage VEXT of the comparator 310. It may include a plurality of load unit 321, 322 to output. In one embodiment, the output circuit 320 includes a first load portion 321 and a second load portion 322. The first load unit 321 supplies the first internal voltage VINT to the first internal circuit in response to the control signal WRITEB, and the second load unit 322 supplies the second internal signal in response to the control signal READB. The internal voltage VINTIO is provided to the second internal circuit. The first internal voltage VINT and the second internal voltage VINTIO may have the same voltage value, but may be supplied to the internal circuit through power supply lines separated from each other to prevent mutual inflow of noise.

The feedback circuit 330 feeds back the output internal voltages VINT and VINTIO to the comparator 310. The feedback circuit 330 may include a multiplexer 331. The multiplexer 331 connects the activated load units 321 and 322 to the comparator 310 in response to the control signals WRITE and READ to convert the output internal voltages VINT and VINTIO to the comparator 310. to provide.

That is, the multiplexer 323 is the first internal voltage VINT or the second internal output from the load unit selected in response to the control signals WRITE and READ among the first load unit 321 and the second load unit 322. The voltage VINTIO is fed back to the input of the comparator 310 so that the multiple internal voltage converter 231 can supply stable power.

The control signals WRITE and READ activate either one of the first load unit 321 and the second load unit 322 and supply an internal voltage provided through the activated load unit to the first internal circuit or the second internal circuit. The multiplexer 323 is controlled to connect the activated load unit with the comparator 310 to form a feedback loop.

In an embodiment, the control signals WRITE and READ may indicate an operating state of the semiconductor device. For example, the control signals WRITE and READ may be in a first power activation mode during a data write operation, and the control signals WRITE and READ may be in a second power activation mode during a data read operation. That is, since the second internal circuit does not consume much power during the data write operation, the first load unit 321 is activated to enable the multiple internal voltage converters to supply power to the first internal circuit. The unit 321 may be connected to the comparator 310 to form a feedback loop, and during the data read operation, a large amount of power may be consumed by an output circuit included in the second internal circuit. In order to supply power to the second internal circuit, the second load unit 322 may be activated and connected to the comparator 320 to form a feedback loop.

Hereinafter, a configuration of a multiple internal voltage converter according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

The multiple internal voltage converter 231 of FIG. 3 may be implemented using a plurality of MOS transistors by a CMOS transistor manufacturing process. For example, the comparator 310 may be implemented as a differential amplifier circuit that receives the reference voltage VREF and the output internal voltages VINT and VINTIO and outputs a value DG corresponding to the voltage difference.

The comparator 310 may include first and second PMOS transistors MP1 and MP2 and first to third NMOS transistors MN1, MN2, and MN3.

The first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to a source terminal in common and are biased by a third NMOS transistor MN3 which is a current source. The reference voltage VREF and the fed back internal voltages VINT and VINTIO are input to the gate terminals of the first NMOS transistor MN1 and the second NMOS transistor MN2, respectively. The first and second NMOS transistors MN1 and MN2 may form a differential amplification comparison circuit, and the first PMOS transistor MP1 and the second NMOS transistor MP2 are loads of the differential amplification comparison circuit. It can be connected with.

Hereinafter, the connection relationship of each transistor is explained in full detail.

The first PMOS transistor MP1 receives an external voltage VEXT from a source terminal.

The second PMOS transistor MP2 is connected to an external voltage VEXT as a source terminal, a gate terminal is connected to the gate terminal of the first PMOS transistor, and a drain terminal is connected to the gate terminal.

The first NMOS transistor MN1 has a drain terminal connected to the drain terminal of the first PMOS transistor MP1 to output a comparison result, and receives a reference voltage to the gate terminal.

The second NMOS transistor MN2 has a drain terminal connected to the drain terminal of the second PMOS transistor MP2 and a gate terminal connected to the feedback loop.

The third NMOS transistor MP3 has a drain terminal connected to source terminals of the first and second NMOS transistors, a source terminal connected to a ground power source, and the first and second NMOS transistors MP3 according to a bias voltage applied to a gate. The bias current of the second PMOS transistor and the first and second NMOS transistors is provided.

Each of the plurality of load units 321 and 322 included in the output circuit 320 may be biased by the comparison value DG of the comparator 310 to output one of the plurality of internal voltages VINT and VINTIO. The MOS transistors MP4 and MP6 and the second MOS transistors MP3 and MP5 which activate the first MOS transistors MP4 and MP6 in response to a control signal.

In one embodiment, the first load portion 321 of the output circuit 320 includes third and fourth PMOS transistors MP3 and MP4. The third PMOS transistor MP3 is turned on when the source terminal is connected to the external voltage VEXT and the control signal is in the first power activation mode. In the fourth PMOS transistor MP4, a source terminal is connected to the drain terminal of the third PMOS transistor MP3, and an output voltage of the comparator 310 is applied to the gate terminal to drain the first internal voltage VINT. Output to the terminal.

In one embodiment, the second load portion 322 of the output circuit 320 includes fifth and sixth PMOS transistors MP5 and MP6. The fifth PMOS transistor MP5 is turned on when the source terminal is connected to the external voltage VEXT and the control signal READB is in the second power activation mode. The output voltage of the comparator 310 is applied to the drain terminal of the fifth PMOS transistor MP5 to output the second internal voltage VINTIO to the drain terminal.

The multiplexer 331 of the feedback circuit 330 may include the drain terminal of the fourth PMOS transistor MP4 of the first load unit 321 and the second load unit 322 in response to the control signals WRITE and READ. One of the drain terminals of the 6 PMOS transistor MP6 is selected and connected to the gate terminal of the second NMOS transistor MN2, which is an input of the comparator 310, to feed back an internal voltage to the input voltage of the comparator.

Hereinafter, the operation of the multiple internal voltage converter when the first load unit 321 is activated will be described in more detail.

In the circuit of FIG. 3, when the first internal voltage VINT becomes smaller than the reference voltage VREF, the first NMOS transistor is larger than the current flowing through the second NMOS transistor MN2 of the comparator 310. The current flowing through the MN1 becomes larger and the output voltage of the comparator 310 becomes lower. Therefore, the gate voltage of the fourth NMOS transistor of the first load unit 321 receiving the output voltage of the comparator 310 is lowered and the current between the source and drain increases, thereby raising the first internal voltage VINT again. Is given.

On the contrary, when the first internal voltage VINT becomes higher than the reference voltage VREF, the first internal voltage VINT is higher than the current flowing through the second NMOS transistor MN2 of the comparator 310 through the first NMOS transistor MN1. The flowing current becomes smaller and the output voltage of the comparator 310 becomes higher. Therefore, the gate voltage of the fourth NMOS transistor of the first load unit 321 receiving the output voltage of the comparator 310 is increased and the current between the source and drain becomes small, thereby lowering the first internal voltage VINT again. do. The principle of negative feedback keeps the internal voltage constant at a value corresponding to the reference voltage. In addition, the multiple internal voltage converter according to an embodiment of the present invention can selectively supply power to several internal circuits with one comparator, thereby reducing the number of devices and the chip area than using separate separate internal voltage converters. Efficient power supply can be achieved without significant increase.

When the second load unit 322 is activated, the operation of the multiple internal voltage converters is similar to the case where the first load unit 321 is activated, and thus detailed description thereof will be omitted.

4 is a block diagram illustrating an internal power supply device 110 according to another embodiment of the present invention.

Referring to FIG. 4, an internal power supply device according to an embodiment of the present invention includes multiple internal voltage converters 431, 432, 433, and 434.

The multiple internal voltage converter 430 generates one of the plurality of internal voltages VINT and VINTIO in response to the control signal, and selectively supplies one of the plurality of internal circuits. The internal power supply 110 may further include internal voltage converters 411, 412, 421, and 422 supplying internal voltage only to certain internal circuits.

The internal power supply according to the embodiment shown in FIG. 4 may include a plurality of multiple internal voltage converters 431, 432, 433, and 434, and some or all of them may be controlled by control signals VINTON and VINTIOON. The control unit may supply power to the first internal circuit or switch the power supply direction to supply the second internal circuit. Thus, efficient power distribution can be achieved.

FIG. 5 is a circuit diagram illustrating the multiple internal voltage converter 431 included in the power supply 110 of FIG. 4.

The multiple internal voltage converter 431 of FIG. 5 is similar in configuration and operation to the multiple power converter shown in FIG. 3. 3 and 5 may use a data write signal or a data read signal as a control signal. In addition, various types of signals for switching the power supply direction of the multiple power converter may be used. In the case of using multiple internal voltage converters, the multiple internal voltage converters may be individually controlled through control signals VINTON and VINTIOON to switch all or some of the power supply directions.

6 is a block diagram illustrating an internal power supply device 110 according to another embodiment of the present invention.

Referring to FIG. 6, an internal power supply 110 according to an embodiment of the present invention includes multiple internal voltage converters 431, 432, 433, and 434 and a controller 440. The internal power supply 110 may further include first internal voltage converters 411 and 412 and second internal voltage converters 421 and 422 supplying internal voltage only to a predetermined internal circuit.

The operation of the multiple internal voltage converters 431, 432, 433, 434 of FIG. 6 is similar to the multiple internal voltage converters 431, 432, 433, 434 of FIG. 4.

The controller 440 controls the power supply direction of the multiple internal voltage converters 431, 432, 433, and 434 according to power information of the plurality of internal circuits 451 and 452. The power information may include various information for evaluating the power supply capability of the first internal voltage converters 411 and 412 and the second internal voltage converters 421 and 422. For example, the power information may include a required power amount of the first internal circuit, a required power amount of the second internal circuit, a supply power supplied to the first internal circuit, a supply power supplied to the second internal circuit, and the like.

The controller 440 controls the power supply direction of at least one of the multiple internal voltage converters 431, 432, and 433 according to the power information of the first internal circuit 451 and the second internal circuit 452 so that efficient power distribution can be achieved. Can be done. In the internal power supply of the semiconductor device, there may be a power supply block which is relatively incapable of supplying power. Since the power characteristics may be affected by the poor supplying power, a part of the power supply having sufficient power supply capability is supplied. By supplying the capacity to the lack of ability to prevent the power supply shortage can be distributed efficiently. The controller 440 may consider the amount of power PW1 and PW2 required by the first internal circuit 451 and the second internal circuit 452 and the amount of power VINT and VINTIO supplied at a specific time point to determine the power supply capability. have. That is, the controller 430 controls the power of the multiple internal voltage converters 431, 432, 433, and 434 based on the amount of power PW1 and PW2 or the supply power VINT and VINTIO that change in time during the operation of the semiconductor device. Control the feed direction. According to an embodiment, there may be a plurality of internal voltage converters 431, 432, 433, and 434, and the controller 440 may control the power supply direction of some or all of them.

FIG. 7 is a block diagram illustrating the controller 440 included in the internal power supply 110 of FIG. 6.

Referring to FIG. 7, the controller 440 includes a power amount determiner 441 and an adjuster 442. The power amount determiner 441 determines the amount of power required and the amount of power supplied to the first and second internal circuits. The required power amount or supply power amount may have a predetermined value according to the operation of the semiconductor device, and a time change value may be detected from an internal circuit or power supply lines. The controller 442 generates control signals VINTON and VINTIOON that control the power supply directions of the plurality of internal voltage converters from the power amounts determined by the power amount determiner 441. By the control signal, a plurality of multiple internal voltage converters can be controlled collectively or individually.

In one embodiment, the power supply capability may be determined by comparing the ratio of the supply power amount to the required power amount for each of the first internal circuit and the second internal circuit. For example, if the ratio of the supply power amount VINT to the required power amount PW1 of the first internal circuit is smaller than the ratio of the supply power amount VINTIO to the required power amount PW2 of the second internal circuit, the first internal power supply. The circuitry determines that the supply capability of the circuit is small and causes a portion of the multiple internal voltage converters to supply power to the second internal circuit. This process may continue until the ratio of the amount of power supplied to the amount of power required of the first and second internal circuits is equal.

An internal multiple internal voltage converter according to an embodiment of the present invention, an internal power supply device and a semiconductor device including the same may efficiently supply power to internal circuits of the semiconductor device by controlling a power supply direction.

According to the present invention, an internal voltage can be selectively supplied to a plurality of internal circuits by using multiple internal voltage converters, thereby controlling power supply direction according to an operating state of a semiconductor device to efficiently distribute power to the plurality of internal circuits. In addition, even if the power supply capability of some internal voltage converters is insufficient, power distribution can be controlled to stably supply power to internal circuits.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 is a block diagram illustrating an internal power supply device according to an embodiment of the present invention.

3 is a circuit diagram illustrating a multiple internal voltage converter according to an embodiment of the present invention.

4 is a block diagram illustrating an internal power supply device according to another exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating multiple internal voltage converters included in the power supply of FIG. 4.

6 is a block diagram illustrating an internal power supply device according to another exemplary embodiment of the present invention.

FIG. 7 is a block diagram illustrating a controller included in the internal power supply of FIG. 6.

Description of the main parts of the drawing

100: semiconductor device 110: internal power supply

211, 212, 213, 214, 411, 412: first internal voltage converter

221, 222, 421, and 422: second internal voltage converter

231, 232, 431, 432, 433, 434: multiple internal voltage converters

440: control unit

Claims (10)

A comparison unit comparing one of the plurality of internal voltages with a reference voltage; An output circuit which receives a comparison value of the comparator and an external voltage, selectively generates one of the plurality of internal voltages in response to a control signal, and supplies the internal voltage to an internal circuit; And And a feedback circuit for feeding back the output internal voltage to the comparator. The method of claim 1, wherein the output circuit And a plurality of load parts selectively activated in response to the control signal and outputting one of the plurality of internal voltages based on a comparison value of the comparator and the external voltage. The method of claim 2, wherein each of the plurality of load portion A first MOS transistor biased by a comparison value of the comparator to output one of the plurality of internal voltages; And And a second MOS transistor for activating or deactivating the first MOS transistor in response to the control signal. The method of claim 2, wherein the feedback circuit is And a multiplexer configured to connect the activated load part to the comparator in response to the control signal to provide the output internal voltage to the comparator. The method of claim 1, wherein the comparison unit And a differential amplifier circuit receiving the reference voltage and the output internal voltage and outputting a value corresponding to the voltage difference. A multiple internal voltage converter configured to generate one of the plurality of internal voltages in response to the control signal and to selectively supply some of the plurality of internal circuits; And And a controller configured to control a power supply direction of the multiple internal voltage converters according to power information of the plurality of internal circuits. The internal power supply of claim 6, wherein the power information includes a required power amount and a supply power amount of the plurality of internal circuits. The method of claim 7, wherein the control unit A power amount determiner which determines a required power amount and a supply power amount of the plurality of internal circuits; And And an adjusting unit configured to control a supply direction of the multiple internal voltage converters according to a required power amount and a supply power amount of the plurality of internal circuits. A memory cell array for storing data; An input / output circuit for inputting and outputting the data; And And an internal power supply including a multiple internal voltage converter configured to generate an internal voltage in response to a control signal and selectively supply the internal voltage to any one of the memory cell array and the input / output circuit. 10. The method of claim 9, When the semiconductor device performs a data read operation, the multiple internal voltage converter supplies the internal voltage to an input / output circuit, And the multiple internal voltage converter supplies the internal voltage to a memory cell array when the semiconductor device performs a data write operation.

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