JP5380326B2 - Internal power supply circuit for semiconductor memory - Google Patents

Description

  The present invention relates to a power supply circuit mounted on a semiconductor memory, and more particularly to an internal power supply circuit that generates a power supply voltage to be supplied to a sense amplifier based on an externally supplied power supply voltage.

  Currently, DRAM (Dynamic Random Access Memory), which is a semiconductor memory mounted on computers, supplies power from the external power supply to the memory cell array and sense amplifier to reduce power consumption and ensure reliability. Based on the generated power supply voltage, an internal power supply circuit provided in the DRAM chip is used. In recent years, there has been a demand for an increase in the storage capacity of DRAM chips, and there is a concern about an increase in the instantaneous current that flows along with the increase in the storage capacity. That is, if the current supply is concentrated at one time, the power supply voltage may drop instantaneously, causing a malfunction in the memory operation.

  Therefore, in order to eliminate such problems, a normal power supply voltage (VARY) to be supplied to the sense amplifier and a power supply voltage (VOD) higher than this power supply voltage (VARY) are generated based on the power supply voltage supplied from the outside. However, a power supply voltage control method has been proposed in which a power supply voltage (VOD) is supplied to a sense amplifier when a large current supply is required, and a power supply voltage (VARY) is alternatively supplied to the sense amplifier. For example, see the description of FIG. 6 of Patent Document 1).

  However, in the method for controlling the power supply voltage as described above, since it is necessary to mount two sets of internal power supply circuits, the construction area on the chip becomes large and the cost increases. Further, as a transistor used for a selector for switching a power supply voltage supplied to the sense amplifier (see, for example, the transistors 15 and 16 in FIG. 6 of Patent Document 1), a transistor having a low on-resistance in order to suppress power consumption in this portion. It is necessary to use it. However, a transistor having a low on-resistance has a problem that the scale is increased correspondingly and the cost is increased.

JP 2008-159188 A

  It is an object of the present invention to provide an internal power supply circuit for a semiconductor memory that can perform a stable memory operation even when current supply is concentrated at low cost.

An internal power supply circuit of a semiconductor memory according to the present invention is an internal power supply circuit of a semiconductor memory that supplies a power supply voltage to a sense amplifier mounted on the semiconductor memory via a power supply line, and a predetermined first voltage and A first differential amplifier that generates a differential signal indicating a difference from the voltage on the power supply line and sends the differential signal to the drive line; a predetermined second voltage that is higher than the first voltage; and the power supply line A second differential amplifier that generates a differential signal indicating a difference from the voltage and sends it to the drive line; and a predetermined period of time elapses while the sense amplifier is in the inactive state and when the sense amplifier transitions to the active state. The second differential amplifying unit is maintained in an active state and the first differential amplifying unit is maintained in an inactive state until the first differential amplifying unit is in an active state after elapse of the predetermined period. As well as A power supply voltage switching unit for maintaining the second differential amplification unit in an inactive state; and generating the power supply voltage having the first voltage or the second voltage according to the differential signal on the drive line. possess an output transistor for delivering on the power supply line, a first differential amplifying unit, is and another gate edge between being applied to the external supplied external power supply voltage source terminal of each is connected First and second transistors, a third transistor having the first voltage applied to a gate terminal and a drain terminal connected to the drain terminal of the first transistor and the drive line, and a gate terminal. A fourth transistor, to which a voltage on the power supply line is applied and whose drain end is connected to the drain end of the second transistor, and a source of the third transistor to the drain end A fifth transistor having a source terminal connected thereto, a sixth transistor having a drain terminal connected to a source terminal of the fourth transistor, and a current source connected to a source terminal of each of the fifth and sixth transistors. And the second differential amplifier section includes a seventh transistor having a gate terminal to which the second voltage is applied and a drain terminal connected to each of the drain terminal of the first transistor and the drive line. And an eighth transistor having a gate terminal applied with a voltage on the power supply line and a drain terminal connected to the drain terminal of the second transistor, and a drain terminal connected to the source terminal of the seventh transistor. A ninth transistor, a tenth transistor having a drain terminal connected to a source terminal of the eighth transistor, and the ninth and first transistors. A current source connected to the source terminal of each of the 0 transistors, and the power supply voltage switching unit is configured to switch the power supply voltage switching unit while the sense amplifier is in an inactive state and when the sense amplifier transitions from an inactive state to an active state. Until the predetermined period elapses, the fifth and sixth transistors are maintained in the off state and the ninth and tenth transistors are maintained in the on state, respectively. A voltage designation signal for turning on the sixth transistor and turning off the ninth and tenth transistors is supplied to the gate terminals of the fifth, sixth, ninth and tenth transistors .

  In the present invention, the power supply voltage having a second voltage higher than the first voltage as the standard power supply voltage value of the sense amplifier is applied until a predetermined period has elapsed since the sense amplifier transitioned from the inactive state to the active state. The voltage is supplied to the sense amplifier, and the voltage value of the power supply voltage is switched to the first voltage after a predetermined period. As a result, it is possible to suppress the amount of power supply voltage drop that accompanies an increase in current consumption when the sense amplifier is active. Further, when the power supply voltage is switched, a first differential amplifier that generates a difference signal indicating a difference between the first voltage and the voltage on the power supply line, the second voltage and the voltage on the power supply line. A second differential amplifier that generates a differential signal indicating a difference between the first and second differential amplifiers according to the state (active state, inactive state) of the sense amplifier, and activates only one of them. And a single output transistor that supplies a power supply voltage generated in accordance with the differential signal supplied from the activated differential amplifier to the sense amplifier via the power supply line. Adopted. According to such a configuration, a power supply voltage having the first voltage and a power supply voltage having the second voltage are individually generated, and one of these power supply voltages is supplied to the sense amplifier. As a result, the circuit scale can be reduced and the price can be suppressed.

It is a figure which shows the internal structure of the semiconductor memory by which the internal power supply circuit by this invention is mounted. FIG. 6 is a diagram for explaining the operation of the internal power supply circuit 4. 3 is an equivalent diagram illustrating a configuration of a power supply voltage control unit. FIG.

  A first differential amplifier for generating a differential signal indicating a difference between a first voltage as a standard power supply voltage value of a sense amplifier mounted on a semiconductor memory and a voltage on a power supply line; and higher than the first voltage Only one of the second differential amplifiers that generates a differential signal indicating the difference between the second voltage and the voltage on the power supply line is activated according to the state (active state, inactive state) of the sense amplifier. Then, the power supply voltage generated according to the differential signal supplied from the activated differential amplifier is supplied to the sense amplifier via the power supply line. At this time, the second differential amplifying unit is maintained in the active state until a predetermined period elapses from the time when the sense amplifier transitions from the inactive state to the active state, and after the predetermined period elapses, the second differential amplifying unit Instead, the first differential amplifier is maintained in the active state.

  FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory equipped with an internal power supply circuit according to the present invention.

The semiconductor memory includes a memory control unit 1, a memory cell array 2, a sense amplifier 3, and an internal power supply circuit 4 that generates a power supply voltage _VARY for operating the sense amplifier 3.

  In response to the write signal WR, the memory control unit 1 controls the memory cell array 2 to write information data at the address indicated by the address data. In addition, the memory control unit 1 controls the memory cell array 2 and reads the logic level 1 sense for activating the sense amplifier 3 in order to read the information data from the address indicated by the address data in response to the read signal RD. An amplifier enable signal CE is supplied to the sense amplifier 3 and the internal power supply circuit 4.

  The sense amplifier 3 is inactive while the logic level 0 sense amplifier enable signal CE is supplied, while the sense level 3 is in the active state while the logic level 1 sense amplifier enable signal CE is supplied. As long as it is in this active state, the sense amplifier 3 detects a current flowing in a memory cell (not shown) of the memory cell array 2 and outputs information data corresponding to the detected current. That is, the sense amplifier 3 restores the information data stored in the memory cell based on the current flowing in the memory cell of the memory cell array 2 only while the sense amplifier enable signal CE at the logic level 1 is supplied. This is read out to the outside.

  The memory cell array 2 writes the externally supplied information data into a memory cell (not shown) belonging to the address indicated by the address data in response to the write signal WR. The memory cell array 2 supplies a current corresponding to the information data stored in the memory cell belonging to the address indicated by the address data to the sense amplifier 3 according to the read signal RD.

The internal power supply circuit 4 generates a power supply voltage _VARY for operating the sense amplifier 3 based on the externally supplied power supply voltage VDD, and supplies this to the sense amplifier 3 via the power supply line LV. The internal power supply circuit 4 switches the voltage value of the power supply voltage _VARY according to the sense amplifier enable signal CE for setting the sense amplifier 3 to the activated state or the inactive state.

  As shown in FIG. 1, the internal power supply circuit 4 includes a voltage switching timer 41, a power supply voltage control unit 42, an output transistor 43, a current source 44, and a stabilization capacitor element 45.

  The voltage switching timer 41 supplies the high voltage designation signal OD at the logic level 1 to the power supply voltage controller 42 while the sense amplifier enable signal CE supplied from the memory controller 1 is at the logic level 0 as shown in FIG. At the same time, the standard voltage designation signal STN of logic level 0 is supplied to the power supply voltage controller 42. Here, as shown in FIG. 2, when the sense amplifier enable signal CE is switched from the logic level 0 state to the logic level 1, the voltage switching timer 41 receives the time point t2 after a predetermined period TU has elapsed from the switching time point t1. The high voltage designation signal OD is switched to the logic level 0, and the standard voltage designation signal STN is switched to the logic level 1, respectively.

That is, the voltage switching timer 41 uses the voltage value of the power supply voltage V _ARY that operates the sense amplifier 3 during the active state after a predetermined period TU has elapsed since the sense amplifier 3 switched from the inactive state to the active state. Then, a standard voltage designation signal STN of a logic level 1 for designating a standard voltage V _REF (described later) is supplied to the power supply voltage controller 42. Further, the voltage switching timer 41 is in a period during which the sense amplifier 3 is in an inactive state and during a period from when the inactive state is switched to the active state until a predetermined period TU elapses, that is, during a period TZ in FIG. A high voltage designation signal OD of a logic level 1 for designating a high voltage V _RNS (described later) higher than the standard voltage V _REF as a voltage value of the power supply voltage V _ARY is supplied to the power supply voltage control unit 42. As described above, the voltage switching timer 41 increases the voltage value of the power supply voltage V _ARY for operating the sense amplifier 3 at the time t2 when the predetermined period TU has elapsed since the sense amplifier 3 was switched from the inactive state to the active state. Signals (STN, OD) to be switched from the voltage V _RNS to the standard voltage V _REF are supplied to the power supply voltage control unit 42.

As shown in FIG. 1, the power supply voltage control unit 42 includes transistors Q1 and Q2 that are p-channel MOS (Metal Oxide Semiconductor) transistors, transistors Q3 to Q10 that are n-channel MOS transistors, and a current source CG. An externally supplied power supply voltage VDD is applied to the source ends of the transistors Q1 and Q2, and the gate ends are connected to each other. The drain ends of the transistors Q1 and Q7 are connected in common to the drain end of the transistor Q1, and the common connection point is connected to the gate end of the output transistor 43 via the drive line LD. The standard voltage V _REF described above is applied to the gate terminal of the transistor Q3, and the source terminal is connected to the drain terminal of the transistor Q5. The high voltage V _RNS is applied to the gate terminal of the transistor Q7, and the source terminal is connected to the drain terminal of the transistor Q9. The drain end and the gate end of the transistor Q2 are connected to each other, and the drain ends of the transistors Q4 and Q8 are connected to the common connection point. The drain end of the transistor Q6 is connected to the source end of the transistor Q4. The drain end of the transistor Q6 is connected to the source end of the transistor Q4. The gate ends of the transistors Q4 and Q8 are connected to each other, and a power supply line LV is connected to the common connection point. The source ends of the transistors Q5 to Q10 are commonly connected, and a current source CG is connected to the common connection point. The high voltage designation signal OD is supplied to the gate terminals of the transistors Q5 and Q6, and the standard voltage designation signal STN is supplied to the gate terminals of the transistors Q9 and Q10.

  FIG. 3 is an equivalent diagram showing the configuration of power supply voltage control unit 42 shown in FIG.

  That is, the power supply voltage controller 42 includes the first differential amplifier CMP1 including the transistors Q1 to Q6 and the current source CG, and the second differential amplifier CMP1 including the transistors Q1, Q2, Q7 to 10 and the current source CG. The differential amplifier unit CMP2. Note that the transistors Q1 and Q2 and the current source CG are shared by the differential amplifiers CMP1 and CMP2. The power supply voltage control unit 42 activates one of the first differential amplification unit CMP1 and the second differential amplification unit CMP2 based on the logic levels of the high voltage designation signal OD and the standard voltage designation signal STN. Keep the other inactive. At this time, a signal output from the active differential amplifier is sent onto the drive line LD as a power supply voltage difference signal GO as follows.

For example, when the high voltage designation signal OD is at the logic level 1 and the standard voltage designation signal STN is at the logic level 0, the transistors Q5 and Q6 are both off and the transistors Q9 and Q10 are both on. Therefore, at this time, the second differential amplifier CMP2 including the transistors Q1, Q2, Q7, Q8, Q9, and Q10 and the current source CG is activated, and the first differential amplifier CMP1 is deactivated. It becomes. The activated second differential amplifier CMP2 receives the power supply voltage difference signal GO indicating the voltage value corresponding to the difference between the high voltage V _RNS and the voltage on the power supply line LV, for each of the transistors Q1 and Q7. The signal is transmitted onto the drive line LD through a connection point where the drain ends are connected to each other.

On the other hand, when the high voltage designation signal OD is at the logic level 0 and the standard voltage designation signal STN is at the logic level 1, the transistors Q5 and Q6 are both turned on and the transistors Q9 and Q10 are both turned off. Therefore, at this time, the first differential amplifier CMP1 including the transistors Q1, Q2, Q3, Q4, Q5, and Q6 and the current source CG is activated, and the second differential amplifier CMP2 is deactivated. Become. The activated first differential amplifier CMP1 generates a power supply voltage difference signal GO indicating a voltage value corresponding to the difference between the standard voltage _VREF and the voltage on the power supply line LV, for each of the transistors Q1 and Q3. The signal is transmitted onto the drive line LD through a connection point where the drain ends are connected to each other.

An externally supplied power supply voltage VDD is applied to the source end of the output transistor 43 as a p-channel MOS transistor, the drain end thereof is a power supply line LV, a current source 44, and a stabilizing capacitor whose one end is grounded. The other end of the element 45 is connected. The power supply voltage VDD is higher than the high voltage V _RNS described above. The output transistor 43 generates a voltage corresponding to the power supply voltage difference signal GO supplied to its gate terminal as a power supply voltage V _ARY for operating the sense amplifier 3. That is, the output transistor 43 has the same voltage value as the high voltage _VRNS according to the power supply voltage difference signal GO when the CMP2 is more active in the differential amplifiers CMP1 and CMP2. A power supply voltage V _ARY is generated. On the other hand, when the differential amplifier CMP1 is in an active state, the output transistor 43 generates the power supply voltage V _ARY having the same voltage value as the standard voltage V _REF according to the power supply voltage difference signal GO. . The output transistor 43 supplies the power supply voltage _VARY to the sense amplifier 3 through the power supply line LV.

As described above, the power supply voltage control unit 42 outputs the output transistor 43 so that the power supply voltage V _ARY applied to the power supply line LV by the output transistor 43 has the same voltage value as the high voltage V _RNS or the standard voltage V _REF. The output voltage is controlled for 43.

  Hereinafter, the operation of the internal power supply circuit 4 having the above-described configuration will be described with reference to FIG.

First, as shown in FIG. 2, while the sense amplifier enable signal CE is at the logic level 0, that is, during the period when the sense amplifier 3 is inactive, the CMP2 of the differential amplifiers CMP1 and CMP2 Only becomes active. Therefore, during this time, the power supply voltage V _ARY having the high voltage V _RNS higher than the standard voltage V _REF is supplied to the sense amplifier 3 through the power supply line LV by the differential amplifier CMP2 and the output transistor 43. At this time, the stabilization capacitor 45 is charged by the high voltage V _RNS applied to the power supply line LV.

Thereafter, when the sense amplifier enable signal CE transitions from the logic level 0 to the logic level 1, the sense amplifier 3 is activated, and the current consumed by the sense amplifier 3 gradually increases as shown in FIG. Accordingly, as shown in FIG. 2, the power supply voltage V _ARY on the power supply line LV gradually decreases from the high voltage V _RNS state. At this time, the stabilization capacitor element 45 is in a discharge state, and a discharge current from the stabilization capacitor element 45 as shown in FIG. 2 is sent onto the power supply line LV. That is, during this time, the current supplied on the power supply line LV as shown in FIG. 2 with the application of the high voltage V _RNS by the differential amplifier CMP2 and the output transistor 43, and the stabilization capacitance element 45 on the power supply line LV. The current consumed by the sense amplifier 3 is covered by the discharged discharge current.

As shown in FIG. 2, the current consumption in the sense amplifier 3 increases, and when the current consumption reaches the maximum, the current consumption gradually decreases thereafter. At this time, the current consumption in the sense amplifier 3 is in a lowered state at least at a time t2 when the predetermined period TU has elapsed from the time t1 when the sense amplifier 3 transitions from the inactive state to the active state. Therefore, the power supply voltage switching timer 41 switches the differential amplification unit to be activated from CMP2 to CMP1 at a time t2 when a predetermined period TU has elapsed from the time t1 when the sense amplifier 3 transitions from the inactive state to the active state. Thus, in such after time t2 shown in FIG. 2, to the differential amplifier section CMP1 and an output transistor 43, supplying the power supply voltage _{V ARY} having a standard voltage _{V REF} to a sense amplifier 3 via a power supply line LV Become. During this time, with the application of the standard voltage _{V REF} according to the differential amplifying unit CMP1 and the output transistor 43, a current as shown in FIG 2 is supplied to the power supply line LV. That is, after the time t2 when the current consumption in the sense amplifier 3 reaches the maximum and then decreases, the current is supplied by the sense amplifier 3 by the current supplied from the differential amplifier CMP1 and the output transistor 43. The current is covered.

As described above, in the internal power supply circuit 4 shown in FIG. 1, while the sense amplifier 3 is in the inactive state, only the CMP2 of the differential amplifiers CMP1 and CMP2 is activated, thereby enabling the standard voltage. A power supply voltage V _ARY having a high voltage V _RNS higher than V _REF is applied to the power supply line LV. Thereby, while the sense amplifier 3 is in an inactive state, the stabilization capacitor element 45 connected to the power supply line LV is charged by the high voltage V _RNS . Thereafter, even after the sense amplifier 3 shifts to the active state, the power supply voltage V _ARY having the high voltage V _RNS higher than the standard voltage V _REF is supplied to the sense amplifier 3 through the power supply line LV. Therefore, even if the power supply voltage V _ARY drops with an increase in current consumption of the sense amplifier 3, the voltage value of the power supply voltage V _{ARY is} a standard value that allows the sense amplifier 3 to operate normally as shown in FIG. It is possible to maintain a state higher than the standard voltage V _REF, which is a large power supply voltage value. Further, when the sense amplifier 3 transitions to the active state, the stabilization capacitor element 45 is discharged, and a discharge current from the stabilization capacitor element 45 is sent to the power supply line LV. Therefore, immediately after the sense amplifier 3 transitions from the inactive state to the active state, the sense amplifier 3 is supplied with the current supplied from the differential amplifying unit CMP2 and the output transistor 43 and the discharge current sent from the stabilizing capacitor 45. The current consumed will be covered. Therefore, as shown in FIG. 2, immediately after the sense amplifier 3 is switched from the inactive state to the active state, that is, it is possible to suppress the amount of power supply voltage drop due to the increase in current consumption in the initial active state.

Then, after the lapse of a predetermined period TU after the sense amplifier 3 transitions from the inactive state to the active state, the differential amplifier to be maintained in the active state is switched from the differential amplifying unit CMP2 to CMP1. That is, as shown in FIG. 2, after the sense amplifier 3 transitions from the inactive state to the active state, the current consumption becomes maximum and the current consumption at the sense amplifier 3 decreases at the time t2 when the current consumption continues to decrease. When the possibility of a power supply voltage drop disappears, the voltage value of the power supply voltage _VARY to be supplied to the power supply line LV is switched from the high voltage V _RNS to the standard voltage V _REF .

  Therefore, according to the operation as described above, it is possible to supply a power supply voltage that can normally operate the sense amplifier 3 to the sense amplifier 3 whose current consumption increases in the initial state of the active state. .

Further, in the internal power supply circuit 4 shown in FIG. 1 or FIG. 3, as the power supply voltage V _ARY for operating the sense amplifier 3, the standard voltage V _REF and the high voltage V _RNS higher than this voltage by a predetermined voltage are 2 The following configuration is adopted when switching the voltage of a kind and sending it on the power supply line LV.

That is, the differential amplifying unit CMP2 for obtaining a difference value between the voltage and the high voltage _{V RNS} each other on the power supply line LV, the differential amplifier unit CMP1 for obtaining a voltage and the difference value between the standard voltage _{V REF} on the power supply line LV One is activated and the other is deactivated. Then, by supplying the differential value (GO) supplied from the differential amplifier in the active state to the gate terminal of the output transistor 43, the single output transistor 43 responds to the differential value (GO). A voltage (V _RNS or V _REF ) is generated and supplied to the power supply line LV as the power supply voltage V _ARY . In other words, the differential amplifiers CMP1 and CMP2 perform control to switch the voltage value of the power supply voltage _VARY to be generated by the output transistor 43 to one of the high voltage V _{RNS and the} standard voltage V _REF .

  According to this configuration, the power supply unit that supplies the current consumed by the sense amplifier 3 includes an internal power supply circuit that generates a power supply voltage having a standard voltage and an internal power supply circuit that generates a power supply voltage higher than the standard voltage. Compared to the case where two internal power supply circuits are used, it is possible to reduce the device scale and reduce the price. That is, in the internal power supply circuit 4 shown in FIG. 1 or FIG. 3, the power supply unit that supplies the current consumed by the sense amplifier 3 is only an internal power supply circuit for one system including the power supply voltage control unit 42 and the output transistor 43. Therefore, the scale of the apparatus is smaller than that required for the two systems as described above. Furthermore, in order to further stabilize the fluctuation of the power supply voltage generated by the two internal power supply circuits, the capacitive element for stabilization must be individually connected to each power supply line. In the internal power supply circuit 4 shown in FIG. 3, there is only one internal power supply circuit. Therefore, stable power supply can be achieved with a small-scale configuration using a single stabilizing capacitive element. In the configuration in which two internal power supply circuits are provided as described above, one of the power supply voltages supplied from each of the two internal power supply circuits is relayed to the power supply line via the selector. The current consumed by the sense amplifier 3 flows. Therefore, a transistor having a low on-resistance, that is, a transistor having a large transistor size must be employed as a transistor used in such a selector. On the other hand, in the internal power supply circuit 4 shown in FIG. 1 or FIG. 3, the power supply voltage is supplied directly from the output transistor 43 to the power supply line LV. Therefore, it is possible to reduce the scale of the apparatus as compared with the case where the power supply voltage is supplied to the power supply line via the selector as described above.

3 Sense Amplifier 4 Internal Power Supply Circuit 41 Power Supply Voltage Switching Timer 42 Power Supply Voltage Control Unit 43 Output Transistor 45 Stabilizing Capacitance Elements CMP1, 2 Differential Amplification Unit

Claims (4)

An internal power supply circuit of a semiconductor memory for supplying a power supply voltage to a sense amplifier mounted on the semiconductor memory via a power supply line,
A first differential amplifier that generates a differential signal indicating a difference between a predetermined first voltage and a voltage on the power supply line, and sends the differential signal to the drive line;
A second differential amplifier that generates a differential signal indicating a difference between a predetermined second voltage higher than the first voltage and a voltage on the power supply line, and sends the differential signal to the drive line;
While the sense amplifier is in an inactive state and during a predetermined period after the transition to the active state, the second differential amplifier is maintained in an active state and the first differential amplifier is inactive. A power supply voltage switching unit that maintains the first differential amplification unit in an active state and maintains the second differential amplification unit in an inactive state after the predetermined period has elapsed,
Have a, an output transistor for delivering to generate the power supply voltage having the first voltage or the second voltage on the power supply line in response to said difference signal on the drive line,
The first differential amplifying unit includes first and second transistors to which an externally supplied external power supply voltage is applied to each source terminal and whose gate terminals are connected to each other. A first transistor to which a voltage is applied and a drain terminal connected to each of the drain terminal of the first transistor and the drive line; a gate terminal to which a voltage on the power supply line is applied; Is connected to the drain terminal of the second transistor, the fifth transistor has the drain terminal connected to the source terminal of the third transistor, and the drain terminal connected to the source terminal of the fourth transistor. A sixth transistor, and a current source connected to a source terminal of each of the fifth and sixth transistors,
The second differential amplifying unit includes a seventh transistor having a gate terminal to which the second voltage is applied and a drain terminal connected to the drain terminal of the first transistor and the drive line, and a gate terminal. An eighth transistor to which a voltage on the power supply line is applied and whose drain end is connected to the drain end of the second transistor, and a ninth transistor whose drain end is connected to the source end of the seventh transistor A tenth transistor having a drain terminal connected to a source terminal of the eighth transistor, and a current source connected to a source terminal of each of the ninth and tenth transistors,
The power supply voltage switching unit causes each of the fifth and sixth transistors to pass through a predetermined period from when the sense amplifier is in an inactive state and when the sense amplifier transitions from an inactive state to an active state. While maintaining the off state and the ninth and tenth transistors on, respectively, the fifth and sixth transistors are turned on and the ninth and tenth transistors are turned on after the predetermined period. An internal power supply circuit for a semiconductor memory, wherein a voltage specifying signal to be turned off is supplied to each gate terminal of the fifth, sixth, ninth and tenth transistors .   The predetermined period is a period from the time when the sense amplifier transitions from the inactive state to the active state until the time when the current consumption of the sense amplifier increases and reaches the maximum and then transitions to the lowered state. The internal power supply circuit of the semiconductor memory according to claim 1.   3. The internal power supply circuit for a semiconductor memory according to claim 1, wherein the first voltage is a standard voltage for operating the sense amplifier. A capacitor for stabilizing the voltage is connected on the power line,
The power supply voltage switching unit charges the capacitive element by maintaining the second differential amplifier in an active state while the sense amplifier is in an inactive state, and the sense amplifier is in an active state from an inactive state. 4. The capacitor element is discharged by maintaining the first differential amplifying unit in an active state instead of the second differential amplifying unit after the predetermined period from the transition to the point of time. An internal power supply circuit for a semiconductor memory according to any one of the above.

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