KR20100037968A - Semiconductor device with vertical channel transistor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device with a vertical channel transistor and a method for manufacturing the same are provided to improve the reliability of the semiconductor device by inserting a diffusion barrier between a gate electrode and an adhesive layer. CONSTITUTION: A substrate includes a plurality of active pillars(22). Round shape vertical gate electrodes(26) surround each active pillar. A gate insulation layer(24) is interposed between the gate electrodes and the active pillar. Word-lines connect the neighboring gate electrodes. An adhesive layer(30A) is interposed between the word-lines and the gate electrodes. A dopant diffusion preventive layer(29A) is interposed between the adhesive layer and the gate electrodes.

Description

Semiconductor device with vertical channel transistor and manufacturing method therefor {SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device having a vertical channel transistor and a method for manufacturing the same.

Recently, researches on vertical channel transistors have been actively conducted to improve the density of memory devices.

1 is a plan view showing a main part of a semiconductor device having a vertical channel transistor according to the prior art.

Referring to FIG. 1, a gate insulating film 12 surrounds a sidewall of a vertical silicon pillar 11 used as a channel of a transistor, and a rounding gate surrounding the gate insulating film on the gate insulating film. Electrode, 13) is formed. A word line 14 is formed to interconnect neighboring annular gate electrodes. The word line 14 is a damascene word line formed in a damascene manner.

The prior art uses tungsten (W) as the word line material to minimize the resistance of the word line.

FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1.

As shown in FIG. 2, a vertical silicon pillar 12 used as a channel of a transistor is formed on the substrate 11. A protective film 13 is formed on the vertical silicon column.

A gate insulating film 14 is formed on the surface of the substrate 11, the vertical silicon pillar 12, and the protective film 13, and the annular gate electrode 15 surrounding a part of the vertical silicon pillar 12 is formed on the gate insulating film 14. ) Is formed.

A buried bit line 16 is formed in the substrate 11 between the vertical silicon pillars 12 through ion implantation, and the buried bit line 16 is separated by the trench 17. An interlayer insulating film 18 is gap-filled in the trench, and the interlayer insulating film 18 also insulates the gate electrodes 15 from each other.

The word line 20 interconnecting the neighboring gate electrodes 15 is formed in a damascene form. The word line 20 includes a tungsten film, and an adhesive film 19 is interposed between the gate electrode 15 and the word line 20 to improve adhesion between the tungsten film and the gate electrode 15.

The prior art uses a titanium nitride film (TiN) as the adhesive layer (Glue Layer) 19, the titanium nitride film serves as a glue layer that must be used when using a tungsten film as the word line (20). In addition, the titanium nitride layer (TiN) should also have a very good step coverage property.

Accordingly, the titanium nitride film is mainly deposited using a sequential flow deposition (SFD) method using titanium tetrachloride (TiCl ₄ ) gas as a main reaction gas.

However, the prior art has a problem that the gate insulating film 14 is degraded when the titanium nitride film used as the adhesive film 19 is deposited. Deterioration of the gate insulating film 14 occurs because chlorine (Cl) contained as an impurity in the titanium tetrachloride gas used in the deposition of the titanium nitride film reaches the gate insulating film 14 in a subsequent thermal process.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can prevent deterioration of a gate insulating film due to diffusion of impurities in a vertical channel transistor manufacturing process. .

A semiconductor device of the present invention for achieving the above object is a substrate having a plurality of active pillars; An annular vertical gate electrode surrounding each of the active pillars; A gate insulating layer interposed between the gate electrode and the active pillar; A word line interconnecting the adjacent gate electrodes; An adhesive film interposed between the word line and the gate electrode; And a first impurity diffusion prevention film interposed between the adhesive film and the gate electrode, and further comprising a second impurity diffusion prevention film interposed between the gate electrode and the gate insulating film. The first and second impurity diffusion barriers are conductive materials containing tantalum, and the first and second impurity diffusion barriers include a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN). The word line may include a tungsten film (W), and the adhesive film may include a titanium nitride film (TiN).

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a plurality of active pillars on the substrate; Forming a gate insulating film on a surface of the substrate including the active pillar; Forming an annular gate electrode surrounding each of the active pillars on the gate insulating layer; Forming an impurity diffusion barrier on the entire surface including the gate electrode; Forming an adhesive film on the impurity diffusion barrier; And forming a word line on the adhesive layer to interconnect neighboring gate electrodes.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a plurality of active pillars on the substrate; Forming a gate insulating film on a surface of the substrate including the active pillar; Sequentially forming a first impurity diffusion prevention film and a gate conductive film on the gate insulating film; Selectively etching the gate conductive layer to form an annular gate electrode surrounding each of the active pillars; Forming a second impurity diffusion barrier on the entire surface including the gate electrode; Forming an adhesive film on the second impurity diffusion preventing film; And forming a word line on the adhesive layer to interconnect neighboring gate electrodes.

The present invention described above can prevent the deterioration of the gate insulating film due to the diffusion of impurities during the subsequent word line conductive film deposition process by inserting an impurity diffusion prevention film between the annular gate electrode and the adhesive film, thereby improving the reliability of the vertical channel transistor. It works.

In addition, the present invention prevents deterioration of the gate insulating film due to diffusion of impurities during deposition of the conductive film used as the gate electrode and the word line by inserting an impurity diffusion preventing film between the gate electrode and the gate insulating film, as well as between the gate electrode and the adhesive film. There is an effect that can improve the reliability of the vertical channel transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

In the present invention, a barrier metal is inserted between the annular gate electrode and the adhesive layer to prevent deterioration of the gate insulating layer. As the material to be applied as the impurity diffusion preventing film, a tantalum nitride film (TaN) or a tantalum carbonitride film (TaCN) excellent in preventing impurity diffusion such as chlorine is used.

3A is a plan view showing the structure of a semiconductor device according to the first embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

Referring to FIG. 3A, a gate insulating film 104 surrounds a sidewall of a vertical silicon pillar 102 used as a channel of a transistor, and surrounds the gate insulating film 104 on the gate insulating film 104. An annular gate electrode 105 is formed. A word line 111 is formed to interconnect neighboring annular gate electrodes. The word line 111 is a damascene word line formed in a damascene manner.

Tungsten (W) is used as the word line material to minimize the resistance of the word line 111. An adhesive film 110 is interposed to improve adhesion between the word line 111 and the gate electrode 105, and an impurity diffusion barrier 109 is formed between the gate electrode 105 and the adhesive film 110.

Referring to FIG. 3B, a vertical silicon pillar 102 used as a channel of a transistor is formed on the substrate 101. The hard mask film 103 is formed on the vertical silicon column 102.

A gate insulating film 104 is formed on the surface of the substrate 101, the vertical silicon pillar 102 and the hard mask film 103, and the annular gate electrode surrounding a part of the vertical silicon pillar 102 on the gate insulating film 104. 105 is formed.

The buried bit line 106 is formed in the substrate 101 between the vertical silicon pillars 102 through ion implantation, and the buried bit line 106 is separated by the trench 107. An interlayer insulating film 108 is gap-filled in the trench, and the interlayer insulating film 108 also insulates the gate electrodes 105 from each other.

The word line 111 connecting the neighboring gate electrodes 105 to each other is formed in a damascene form. The word line 111 includes a tungsten film, and an adhesive film 110 is interposed between the gate electrode 105 and the word line 111 to improve adhesion between the tungsten film and the gate electrode 105.

According to the first embodiment described above, an impurity diffusion preventing film 109 is inserted between the adhesive film 110 and the gate electrode 105.

The impurity diffusion preventing film 109 is a material that prevents the gate insulating film 104 from deteriorating due to the diffusion of impurities during the deposition of the adhesive film 110. Preferably, the impurity diffusion barrier 109 may include a conductive material containing tantalum, for example, a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN).

The adhesive film 110 is a material for improving the adhesive property of the word line 111. For example, when the word line 111 is a tungsten film W, it is preferable that the adhesive film 110 use a titanium nitride film TiN. The titanium nitride film used as the adhesive film 110 is deposited by using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and deposited by a sequential gas supply deposition method (SFD) to secure step coverage. Chlorine included in the titanium tetrachloride gas may be diffused into the gate insulating film 104 when the titanium nitride film is deposited. In the first embodiment, the diffusion of the chlorine may be prevented by forming the impurity diffusion preventing film 109 in advance.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 4A, vertical silicon pillars 22 are formed on the substrate 21.

The vertical silicon column 22 is a pillar structure arranged in a matrix form and is an active region in which a channel of a transistor is formed. The vertical silicon column 22 has a neck-free straight structure without neck pillars, and having a neck-free structure provides a stable structure resistant to collapse. The vertical silicon column 22 is formed through an etching process using the hard mask layer pattern 23. Hereinafter, the vertical silicon pillar 22 will be abbreviated as 'active pillar 22'. The substrate 21 includes a silicon substrate. Since the substrate 21 is a silicon substrate, the etching process for forming the active pillar 22 may be performed by using Cl ₂ or HBr gas alone, or by using a mixed gas of Cl ₂ and HBr gas. The hard mask film pattern 23 may be formed of a silicon nitride film (Si ₃ N ₄ ) or a silicon carbide film (SiC). A buffer film such as a silicon oxide film may be inserted between the hard mask pattern pattern 23 and the active pillar 22.

Subsequently, the gate insulating film 24 is formed on the entire surface including the hard mask film pattern 23. The gate insulating film 24 may include a silicon oxide film, and the gate insulating film 24 may be formed to have a thickness of 50 μs by a deposition process or an oxidation process.

Subsequently, the buried bit line BBL 25 is formed through ion implantation of impurities in the substrate 21. The buried bit line 25 may be formed by ion implanting N-type impurities such as phosphorus (Ph) and arsenic (As).

As shown in FIG. 4B, an annular gate electrode 26 is formed on the gate insulating film 24 to surround the sidewall of the active pillar 22. In this case, the gate electrode 26 may be formed by etching back the gate conductive layer. The gate conductive film used as the gate electrode 26 is preferably made of any one of TiN, Al, Cu, or an alloy thereof. As described above, the gate conductive film is preferably deposited using a sequential gas supply deposition method (SFD) or an atomic layer deposition method (ALD) in order to secure step coverage. Is preferred. As described above, since the gate electrode surrounds the vertical silicon pillar, the channel of the transistor formed by the gate electrode becomes a vertical channel.

Subsequently, a trench 27 for etching the substrate 21 through a BBL (Buried BitLine) mask process (not shown) to separate the buried bit line 25 is formed.

Subsequently, the interlayer insulating film 28 is deposited to gap fill the trench 27 and then etched back to expose some sidewalls of the gate electrode 26.

As shown in FIG. 4C, an impurity diffusion barrier 29 is formed on the entire surface. The impurity diffusion barrier 29 is a material that prevents deterioration of the gate insulating layer 24 due to diffusion of impurities during subsequent deposition of an adhesive layer. Preferably, the impurity diffusion barrier 29 includes a conductive material containing tantalum, and may include, for example, a tantalum nitride film (TaN) or a tantalum carbon quality film (TaCN).

As shown in FIG. 4D, the word line conductive layer 31 is used as a word line so as to gap-fill the active pillars on the adhesive layer 30 after depositing the adhesive layer 30 on the impurity diffusion barrier layer 29. Deposit. The word line conductive film 31 preferably uses a low resistance metallic film such as a tungsten film in order to minimize the resistance of the word line. The adhesive film 30 is a material for improving the adhesive property of the word line conductive film 31. For example, when the word line conductive film 31 is a tungsten film W, it is preferable that the adhesive film 30 uses a titanium nitride film TiN. The titanium nitride film used as the adhesive film 30 is deposited by using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and deposited by a sequential gas supply deposition method (SFD) to ensure step coverage. Chlorine contained in the titanium tetrachloride gas may be diffused into the gate insulating film 24 when the titanium nitride film is deposited. In the second embodiment, the diffusion of the chlorine may be prevented by forming the impurity diffusion preventing film 29 in advance.

As shown in FIG. 4E, the word line conductive layer 31, the adhesive layer 30, and the impurity diffusion barrier layer 29 are simultaneously etched back and left between the active pillars 22. As a result, a word line 31A connecting the neighboring gate electrodes 26 is formed. Although not shown, a damascene pattern may be formed in advance through an interlayer insulating layer deposition and a damascene process before the impurity diffusion barrier 29 is formed. Therefore, the word line 31A may have a damascene word line structure.

After the word line 31A is formed, an adhesive film 30A and an impurity diffusion barrier 29A are formed between the gate electrode 26 and the word line 31A. In particular, the adhesive film 30A and the gate are formed. An impurity diffusion barrier 29A is interposed between the electrodes 26.

After the word line 31A is formed, as shown in FIG. 4F, a word line insulating film 32 for insulating the word line 31A may be formed.

FIG. 5A is a plan view showing the structure of a semiconductor device according to a third embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 5A.

Referring to FIG. 5A, a gate insulating film 204 surrounds a sidewall of a vertical silicon pillar 202 used as a channel of a transistor, and surrounds the gate insulating film 204 on the gate insulating film 204. An annular gate electrode 205 is formed. A word line 212 is formed to interconnect neighboring annular gate electrodes, and the word line 212 is a damascene word line formed in a damascene manner.

Tungsten (W) is used as the word line material to minimize the resistance of the word line 212. An adhesive film 211 is interposed to improve adhesion between the word line 212 and the gate electrode 205, and a second impurity diffusion preventing film 210 is formed between the gate electrode 205 and the adhesive film 211. have. A first impurity diffusion preventing film 209 is formed between the gate electrode 205 and the gate insulating film 204.

Referring to FIG. 5B, a vertical silicon pillar 202 used as a channel of a transistor is formed on a substrate 201. The hard mask film 203 is formed on the vertical silicon column 202.

A gate insulating film 204 is formed on the surface of the substrate 201, the vertical silicon pillar 202, and the hard mask film 203, and the annular gate surrounding a part of the vertical silicon pillar 202 is formed on the gate insulating film 204. An electrode 205 is formed. The gate electrode 205 is deposited using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and is deposited by a sequential gas supply deposition method (SFD) to secure step coverage.

A buried bit line 206 is formed in the substrate 201 between the vertical silicon pillars 202 through ion implantation, and the buried bit line 206 is separated by the trench 207. An interlayer insulating film 208 is gap-filled in the trench, and the interlayer insulating film 208 also insulates the gate electrodes 205 from each other.

A word line 212 interconnecting neighboring gate electrodes 205 is formed in a damascene form. The word line 212 includes a tungsten film, and an adhesive film 211 is interposed between the gate electrode 205 and the word line 212 to improve adhesion between the tungsten film and the gate electrode 205.

According to the third embodiment described above, a second impurity diffusion preventing film 210 is inserted between the adhesive film 211 and the gate electrode 205, and the first impurity is interposed between the gate insulating film 204 and the gate electrode 205. An impurity diffusion prevention film 209 is inserted.

The second impurity diffusion preventing film 210 is a material which prevents deterioration of the gate insulating film 204 due to diffusion of impurities during deposition of the subsequent adhesive film 211, and the first impurity diffusion preventing film 209 is the gate electrode 205. The material prevents deterioration of the gate insulating film 204 due to diffusion of impurities during deposition. Preferably, the first and second impurity diffusion barrier layers 209 and 210 may include a conductive material containing tantalum, for example, a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN).

The adhesive film 211 is a material for improving the adhesive property of the word line 212. For example, when the word line 212 is a tungsten film W, it is preferable that the adhesive film 211 uses a titanium nitride film TiN. The titanium nitride film used as the adhesive film 211 is deposited by using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and deposited by a sequential gas supply deposition method (SFD) to ensure step coverage. Chlorine contained in the titanium tetrachloride gas may be diffused into the gate insulating film 204 when the titanium nitride film is deposited, but the third embodiment may prevent the diffusion of chlorine by forming the second impurity diffusion preventing film 210 in advance. In addition, the third embodiment can prevent the chlorine contained in the titanium tetrachloride gas from diffusing into the gate insulating film 204 when the titanium nitride film used as the gate electrode 205 is deposited by the first impurity diffusion preventing film 209. have.

6A through 6H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

As shown in FIG. 6A, a vertical silicon pillar 42 is formed on the substrate 41.

The vertical silicon column 42 is a pillar structure arranged in a matrix form and is an active region in which a channel of a transistor is formed. The vertical silicon column 42 has a neck-free straight structure without neck pillars, and having a neck-free structure provides a stable structure resistant to collapse. The vertical silicon column 42 is formed through an etching process using the hard mask layer pattern 43. Hereinafter, the vertical silicon pillar 42 will be abbreviated as 'active pillar 22'. The substrate 41 includes a silicon substrate. Since the substrate 41 is a silicon substrate, the etching process for forming the active pillar 42 may be performed by using Cl ₂ or HBr gas alone or by using a mixed gas of Cl ₂ and HBr gas. The hard mask layer pattern 43 may be formed of a silicon nitride layer (Si ₃ N ₄ ) or a silicon carbide layer (SiC). A buffer film such as a silicon oxide film may be inserted between the hard mask pattern pattern 43 and the active pillar 42.

Subsequently, the gate insulating film 44 is formed on the entire surface including the hard mask film pattern 43. The gate insulating film 44 may include a silicon oxide film, and the gate insulating film 44 may be formed to have a thickness of 50 kHz by a deposition process or an oxidation process.

Subsequently, the buried bit lines BBL 45 are formed through ion implantation of impurities in the substrate 41. The buried bit line 45 may be formed by ion implanting N-type impurities such as phosphorus (Ph) and arsenic (As).

As shown in FIG. 6B, a first impurity diffusion barrier 46 is formed on the entire surface including the gate insulating layer. The first impurity diffusion preventing film 46 is a material that prevents deterioration of the gate insulating film 44 due to diffusion of impurities during subsequent gate conductive film deposition. Preferably, the first impurity diffusion barrier 46 includes a conductive material containing tantalum. For example, the first impurity diffusion barrier 46 may include a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN).

Subsequently, a gate conductive film 47 to be used as a gate electrode is formed on the first impurity diffusion preventing film 46. The gate conductive film 47 is preferably made of any one of TiN, Al, Cu, or an alloy thereof. As described above, the gate conductive film 47 is preferably deposited using a sequential gas supply deposition method (SFD) or an atomic layer deposition method (ALD) in order to secure step coverage. It is preferable that it is 50-300 Hz. The titanium nitride film used as the gate conductive film 47 is deposited by using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and is deposited by a sequential gas supply deposition method (SFD) to ensure step coverage. Chlorine contained in the titanium tetrachloride gas may be diffused into the gate insulating layer 44 when the titanium nitride film is deposited. In the fourth embodiment, the diffusion of chlorine can be prevented by forming the first impurity diffusion preventing film 46 in advance.

As illustrated in FIG. 6C, the gate conductive film is etched back to form an annular gate electrode 47A surrounding the sidewall of the active pillar 42. At this time, when the gate conductive film is etched back, the first impurity diffusion preventing film 46 is also etched back. Since the gate electrode 47A is formed to surround the active pillar 42, the channel of the transistor formed by the gate electrode 47A becomes a vertical channel.

Looking at the result after forming the gate electrode 47A, a first impurity diffusion barrier 46A is interposed between the gate electrode 47A and the gate insulating film 44.

As shown in FIG. 6D, the substrate 41 is etched through a buried bit line (BBL) mask process to form a trench 48 that separates the buried bit line 45.

Subsequently, an interlayer insulating film 49 is deposited to gap fill the trench 48 and then etched back to expose some sidewalls of the gate electrode 47A.

As shown in FIG. 6E, a second impurity diffusion barrier 50 is formed on the entire surface. The second impurity diffusion preventing film 50 is a material that prevents deterioration of the gate insulating film 44 due to diffusion of impurities during subsequent deposition of the adhesive film. Preferably, the second impurity diffusion barrier 50 includes a conductive material containing tantalum, for example, a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN).

As shown in FIG. 6F, a word line conductive film is used as a word line so as to gap-fill the active pillars on the adhesive film 51 after depositing the adhesive film 51 on the second impurity diffusion prevention film 50 ( 52). The word line conductive film 52 preferably uses a low resistance metallic film such as a tungsten film in order to minimize the resistance of the word line. The adhesive film 51 is a material for improving the adhesive property of the word line conductive film 52. For example, when the word line conductive film 52 is a tungsten film W, it is preferable that the adhesive film 51 uses a titanium nitride film TiN. The titanium nitride film used as the adhesive film is deposited by using titanium tetrachloride gas (TiCl ₄ ) as a source gas, and deposited by sequential gas supply deposition (SFD) to ensure step coverage. Chlorine contained in the titanium tetrachloride gas may be diffused into the gate insulating film 44 during the deposition of the titanium nitride film. However, the fourth embodiment may prevent the diffusion of chlorine by forming the second impurity diffusion preventing film 50 in advance.

As shown in FIG. 6G, the word line conductive film 52, the adhesive film 51, and the second impurity diffusion preventing film 50 are simultaneously etched back and left between the active pillars 42. As a result, a word line 52A is formed to interconnect neighboring gate electrodes 47A. Although not shown, a damascene pattern may be formed in advance through an interlayer insulating film deposition and a damascene process before forming the second impurity diffusion barrier. Accordingly, the word line 52A may have a damascene word line structure.

After the word line 52A is formed, an adhesive film 51A and a second impurity diffusion barrier 50A are formed between the gate electrode 47A and the word line 52A, in particular, the adhesive film 51A. The second impurity diffusion barrier 50A is interposed between the gate electrode 47A and the gate electrode 47A.

As shown in FIG. 6H, after the word line 52A is formed, a word line insulating layer 53 may be formed to insulate the word line.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a plan view showing the main part of a semiconductor device having a vertical channel transistor according to the prior art;

2 is a cross-sectional view taken along line AA ′ of FIG. 1.

3A is a plan view showing the structure of a semiconductor device according to the first embodiment of the present invention.

3B is a cross-sectional view taken along the line BB ′ of FIG. 3A.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

5A is a plan view showing the structure of a semiconductor device according to the first embodiment of the present invention.

5B is a cross-sectional view taken along line BB ′ of FIG. 5A.

6A to 6H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 active pillar

23: hard mask film 24: gate insulating film

25: buried bit line 26: gate electrode

29A: impurity diffusion prevention film 30A: adhesive film

31A: Wordline

Claims (26)

A substrate having a plurality of active pillars; An annular vertical gate electrode surrounding each of the active pillars; A gate insulating layer interposed between the gate electrode and the active pillar; A word line interconnecting the adjacent gate electrodes; An adhesive film interposed between the word line and the gate electrode; And A first impurity diffusion barrier layer interposed between the adhesive layer and the gate electrode A semiconductor device comprising a. The method of claim 1, A second impurity diffusion prevention layer interposed between the gate electrode and the gate insulating film A semiconductor device further comprising. The method of claim 2, And the first and second impurity diffusion preventing films are conductive materials containing tantalum. The method of claim 1, The first and second impurity diffusion barrier layers include a tantalum nitride layer (TaN) or a tantalum carbonitride layer (TaCN). The method according to any one of claims 1 to 4, The word line includes a tungsten film (W) and the adhesive film includes a titanium nitride film (TiN). The method of claim 1, And the gate electrode comprises a metallic film. The method of claim 6, The metallic film includes a titanium nitride film. Forming a plurality of active pillars on the substrate; Forming a gate insulating film on a surface of the substrate including the active pillar; Forming an annular gate electrode surrounding each of the active pillars on the gate insulating layer; Forming an impurity diffusion barrier on the entire surface including the gate electrode; Forming an adhesive film on the impurity diffusion barrier; And Forming a word line on the adhesive layer to interconnect the adjacent gate electrodes A semiconductor device manufacturing method comprising a. The method of claim 8, Forming the word line, Depositing a conductive film used as the word line on the entire surface including the adhesive film; Simultaneously etching back the conductive film, the adhesive film and the impurity diffusion preventing film A semiconductor device manufacturing method comprising a. The method of claim 8, And the word line comprises a tungsten film. The method of claim 8, The impurity diffusion preventing film includes a tantalum nitride film or a tantalum nitride nitride film. The method of claim 8, The adhesive film includes a titanium nitride film, and the impurity diffusion preventing film comprises a conductive material containing tantalum. The method of claim 12, The titanium nitride film is deposited using a sequential gas supply deposition method using titanium tetrachloride gas (TiCl ₄ ). The method according to any one of claims 8 to 13, And the gate electrode comprises a metallic film. The method of claim 14, And the metallic film comprises a titanium nitride film. The method of claim 15, The titanium nitride film is deposited using a sequential gas supply deposition method using titanium tetrachloride gas (TiCl ₄ ). Forming a plurality of active pillars on the substrate; Forming a gate insulating film on a surface of the substrate including the active pillar; Sequentially forming a first impurity diffusion prevention film and a gate conductive film on the gate insulating film; Selectively etching the gate conductive layer to form an annular gate electrode surrounding each of the active pillars; Forming a second impurity diffusion barrier on the entire surface including the gate electrode; Forming an adhesive film on the second impurity diffusion preventing film; And Forming a word line on the adhesive layer to interconnect the adjacent gate electrodes A semiconductor device manufacturing method comprising a. The method of claim 17, Forming the word line, Depositing a conductive film used as the word line on the entire surface including the adhesive film; Simultaneously etching back the conductive film, the adhesive film, and the second impurity diffusion preventing film. A semiconductor device manufacturing method comprising a. The method of claim 17, And the word line comprises a tungsten film. The method of claim 17, The second impurity diffusion preventing film includes a tantalum nitride film or a tantalum carbonitride film. The method of claim 17, The adhesive film includes a titanium nitride film, and the second impurity diffusion prevention film comprises a conductive material containing tantalum. The method of claim 21, The titanium nitride film is deposited using a sequential gas supply deposition method using titanium tetrachloride gas (TiCl ₄ ). The method according to any one of claims 17 to 22, The forming of the gate electrode may include etching back the gate conductive film and the first impurity diffusion preventing film simultaneously. 24. The method of claim 23, The gate electrode includes a titanium nitride film, and the first impurity diffusion prevention film comprises a conductive material containing tantalum. The method of claim 24, The second impurity diffusion preventing film includes a tantalum nitride film or a tantalum carbonitride film. The method of claim 24, The titanium nitride film is deposited using a sequential gas supply deposition method using titanium tetrachloride gas (TiCl ₄ ).

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