KR20100037351A - Stacked semiconductor package having pad to pad bonding structure and wire bonding method of the same - Google Patents

Stacked semiconductor package having pad to pad bonding structure and wire bonding method of the same Download PDF

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Publication number
KR20100037351A
KR20100037351A KR1020080096641A KR20080096641A KR20100037351A KR 20100037351 A KR20100037351 A KR 20100037351A KR 1020080096641 A KR1020080096641 A KR 1020080096641A KR 20080096641 A KR20080096641 A KR 20080096641A KR 20100037351 A KR20100037351 A KR 20100037351A
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South Korea
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bonding
pad
wire
pads
capillary
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KR1020080096641A
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Korean (ko)
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정정태
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주식회사 하이닉스반도체
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Priority to KR1020080096641A priority Critical patent/KR20100037351A/en
Publication of KR20100037351A publication Critical patent/KR20100037351A/en

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Abstract

PURPOSE: A stacked semiconductor package including a pad to pad bonding structure and a wire bonding method of the same are provided to stably maintain a connection between a bonding pad and the pad of a wiring substrate by using a flat wire. CONSTITUTION: A semiconductor chip is stacked on a wiring substrate(100) and includes bonding pads(220, 320, 420). A flat wire(500) maintains the connection between the bonding pads and the pads of the wiring substrate. The flat wire is a single wire. The cross section of the flat wire has a rectangular shape. The width of the flat wire which is bonded to the bonding pad is smaller than or equal to the width of the bonding pads.

Description

패드 투 패드 본딩 구조를 갖는 적층 반도체 패키지 및 그 와이어 본딩 방법{Stacked semiconductor package having pad to pad bonding structure and wire bonding method of the same}Stacked semiconductor package having pad to pad bonding structure and wire bonding method of the same}

본 발명은 적층 구조의 반도체 패키지에 관한 것으로서, 보다 상세하게는 기판의 패드 및 그 기판에 적층된 칩들의 본딩 패드들을 플랫 와이어를 이용하여 패드 투 패드 방식으로 와이어 본딩한 적층 반도체 패키지 및 그 와이어 본딩 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a laminated structure, and more particularly, to a laminated semiconductor package and a wire bonding, wherein pads of a substrate and bonding pads of chips stacked on the substrate are wire-bonded in a pad-to-pad manner using a flat wire. It is about a method.

현재의 전자제품 시장은 휴대용으로 급격히 그 수요를 늘려 가고 있으며 이를 만족하기 위해서는 이들 시스템에 실장되는 부품들의 경박단소화가 필수적이다. The current electronics market is rapidly increasing the demand for portable, and in order to satisfy this, it is necessary to reduce the light and small size of the components mounted in these systems.

경박단소화를 위해서는, 실장 부품인 반도체 패키지의 개별 크기를 줄이는 기술, 다수개의 개별 반도체 칩들을 하나의 칩(one chip)으로 형성하는 시스템 온 칩(System On Chip; SOC) 기술, 다수개의 개별 반도체 칩들을 하나의 패키지로 집적하는 SIP(System In Package) 기술들이 필요하다.For light and small size reduction, technology to reduce the individual size of the semiconductor package as a mounting component, System On Chip (SOC) technology to form a plurality of individual semiconductor chips into one chip, and a plurality of individual semiconductors There is a need for System In Package (SIP) technologies that integrate chips into a single package.

SIP 기술의 경우, 복수개의 반도체 칩을 수평 또는 수직으로 하나의 패키지 안에 실장하는 기술로써, 종래의 멀티 칩 모듈(Multi-Chip Module; MCM) 기술의 연 장선 상에 있다. 이때, 기존 MCM의 경우에는 수평적 실장이 주된 방향이었으나 SIP의 경우에는 복수개의 반도체 칩을 3차원으로 적층하는 기술이 주로 적용된다.In the SIP technology, a plurality of semiconductor chips are mounted horizontally or vertically in one package, and are on an extension line of a conventional multi-chip module (MCM) technology. In the case of the conventional MCM, horizontal mounting was the main direction, but in the case of SIP, a technique of stacking a plurality of semiconductor chips in three dimensions is mainly applied.

도 1은 종래의 적층 반도체 패키지에서 와이어 본딩된 모습을 보여주는 도면이다.1 is a view illustrating a wire bonded state in a conventional multilayer semiconductor package.

패키지 내에 두 개 이상의 반도체 칩을 적층함에 있어서, 상부에 적층되는 제 2 칩(40)이 하부의 제 1 칩보다 작은 경우에는 제 1 칩(20) 위에 제 2 칩(40)을 바로 적층한다. 그리고 본딩 와이어(30, 50)을 이용하여 제 1 칩(20)의 본딩 패드(22) 및 제 2 칩(40)의 본딩 패드(42)를 각각 배선 기판(10)의 패드(12)와 연결하는 와이어 본딩이 행해진다. 즉, 종래의 적층 구조에서의 와이어 본딩의 경우, 여러개의 본딩 패드(22, 42)가 각각 서로 다른 본딩 와이어(30, 50)를 사용하여 하나의 패드(12)와 연결되는 형태로 본딩이 이루어진다.In stacking two or more semiconductor chips in a package, when the second chip 40 stacked above is smaller than the first chip below, the second chip 40 is directly stacked on the first chip 20. The bonding pads 22 of the first chip 20 and the bonding pads 42 of the second chip 40 are connected to the pads 12 of the wiring board 10 using the bonding wires 30 and 50, respectively. Wire bonding is performed. That is, in the case of wire bonding in a conventional laminated structure, the bonding is performed in a manner that a plurality of bonding pads 22 and 42 are connected to one pad 12 using different bonding wires 30 and 50, respectively. .

그런데, 이와 같이 하나의 패드(12)에 여러개의 본딩 와이어(30, 50)가 본딩되는 경우, 적층되는 칩의 수가 늘어날수록 본딩 와이어의 수도 늘어나게 되어 패키지의 제조 단가가 상승하는 문제가 있다. 또한, 본딩 와이어의 수가 늘어나게 되면 루프 높이(loop height)를 조절하는 어려움과 더불어 와이어 본딩 후 몰드 공정을 진행시 와이어 스윕(sweep)으로 인해 인접한 와이어와의 쇼트(short) 문제가 발생될 가능성이 있다.However, when a plurality of bonding wires 30 and 50 are bonded to one pad 12 as described above, the number of bonding wires increases as the number of chips stacked increases, thereby increasing the manufacturing cost of the package. In addition, when the number of bonding wires increases, there is a possibility of short circuit with adjacent wires due to the wire sweep during the mold process after the wire bonding as well as the difficulty of adjusting the loop height. .

본 발명은 다층으로 적층된 구조의 반도체 패키지에서 적층된 각 칩의 본딩 패드들과 배선 기판의 패드 사이의 본딩 방식을 개선하여 제조 단가를 줄이고 제조가 용이하도록 하고자 한다.The present invention is to reduce the manufacturing cost and to facilitate manufacturing by improving the bonding method between the bonding pads of each chip and the pad of the wiring board in the stacked semiconductor package.

본 발명의 적층 반도체 패키지는 패드를 갖는 배선 기판, 상기 배선 기판상에 적층되며 본딩 패드를 갖는 하나 이상의 반도체 칩 및 상기 본딩 패드들과 상기 패드를 연속적으로 연결시켜 주며 그 단면이 사각 형상으로 형성된 플랫 와이어를 포함한다.The laminated semiconductor package according to the present invention includes a wiring board having a pad, at least one semiconductor chip stacked on the wiring board, and having a bonding pad and the bonding pads and the pad continuously connected to each other. It includes a wire.

본 발명의 적층 반도체 패키지에서 상기 플랫 와이어는 최상층에 적층된 상기 반도체 칩의 상기 본딩 패드부터 상기 패드까지 동일 라인 상에 있는 상기 본딩 패드들과 상기 패드를 연속적으로 연결시켜 주는 하나의 와이어이며, 상기 본딩패드와 접합되는 면의 폭이 높이 보다 큰 직사각 형상을 가질 수 있다.In the multilayer semiconductor package of the present invention, the flat wire is one wire that continuously connects the pads and the pads on the same line from the bonding pads to the pads of the semiconductor chip stacked on the uppermost layer. The width of the surface bonded to the bonding pad may have a rectangular shape larger than the height.

그리고, 상기 플랫 와이어는 상기 본딩패드와 접합되는 면의 폭이 상기 본딩패드의 폭보다 좁거나 같게 형성될 수 있으며, 상기 본딩 패드들 및 상기 패드의 상부면을 피복하면서 상기 본딩 패드들 및 상기 패드를 연속적으로 연결시켜준다. 이때, 상기 플랫 와이어는 상기 적층된 반도체 칩의 상면 및 측면에 밀착되게 형성될 수 있다.The flat wire may be formed to have a width of a surface bonded to the bonding pads to be smaller than or equal to a width of the bonding pads, and to cover the bonding pads and the upper surfaces of the pads. Connect consecutively. In this case, the flat wire may be formed to be in close contact with the upper surface and the side of the stacked semiconductor chip.

본 발명의 제 1 실시예에 따른 적층 반도체 패키지의 와이어 본딩 방법은 제 1 칩 상의 제 1 본딩 패드에 본딩 와이어를 접합시키는 단계, 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 제 1 본딩 패드를 피복하는 단계, 상기 캐필러리를 하강시켜 상기 제 1 칩의 하부에 있는 제 2 칩 상의 제 2 본딩 패드에 상기 본딩 와이어를 접합시키는 단계, 상기 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 제 2 본딩 패드를 피복하는 단계 및 상기 캐필러리를 하강시켜 상기 제 2 칩의 하부에 있는 배선 기판의 패드에 상기 본딩 와이어를 접합시키는 단계를 포함한다.In the wire bonding method of the multilayer semiconductor package according to the first embodiment of the present invention, bonding the bonding wire to the first bonding pad on the first chip, horizontally moving the capillary to connect the first bonding pad to the bonding wire. Coating, lowering the capillary to bond the bonding wire to a second bonding pad on the second chip below the first chip, horizontally moving the capillary to the bonding wire; Covering the bonding pads and lowering the capillary to bond the bonding wires to the pads of the wiring board under the second chip.

본 발명의 와이어 본딩 방법은 상기 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 패드의 일부를 피복하는 단계를 및/또는 상기 제 1 본딩 패드 및 상기 제 2 본딩 패드 상부에 피복된 상기 본딩 와이어를 상기 캐필러리로 압착하는 단계를 더 포함할 수 있다.The wire bonding method of the present invention includes horizontally moving the capillary to cover a portion of the pad with the bonding wire and / or to cover the bonding wire coated on the first bonding pad and the second bonding pad. The method may further include pressing the capillary.

본 발명의 적층 반도체 패키지의 와이어 본딩 방법에서 상기 캐필러리가 하강하는 위치는 상기 본딩 패드의 상부면 내측 말단부인 것이 바람직하다.In the wire bonding method of the laminated semiconductor package of the present invention, the position where the capillary descends is preferably the inner end portion of the upper surface of the bonding pad.

본 발명의 제 2 실시예에 따른 적층 반도체 패키지의 와이어 본딩 방법은 배선 기판의 패드에 본딩 와이어를 접합시키는 단계, 캐필러리를 상승 및 수평이동시켜 상기 본딩 와이어로 상기 배선 기판의 상부에 있는 제 1 칩 상의 제 1 본딩 패드를 피복하는 단계 및 상기 캐필러리를 상승 및 수평이동시켜 상기 본딩 와이어로 상기 제 1 칩의 상부에 있는 제 2 칩 상의 제 2 본딩 패드를 피복하는 단계를 포함한다.The wire bonding method of the laminated semiconductor package according to the second embodiment of the present invention comprises the steps of bonding the bonding wire to the pad of the wiring board, by raising and horizontally moving the capillary, the bonding wire to the upper portion of the wiring board; Coating a first bonding pad on a first chip and raising and horizontally moving the capillary to coat a second bonding pad on a second chip on top of the first chip with the bonding wire.

본 발명의 적층 반도체 패키지의 와이어 본딩 방법은 상기 배선 기판의 패드에 접합된 본딩 와이어를 수평이동시켜 상기 패드의 일부를 피복하는 단계 및/또는 상기 제 1 본딩 패드 및 상기 제 2 본딩 패드 상부에 피복된 상기 본딩 와이어를 상기 캐필러리로 압착하는 단계를 더 포함한다.The wire bonding method of the laminated semiconductor package of the present invention includes horizontally moving a bonding wire bonded to a pad of the wiring board to cover a portion of the pad and / or to cover the first bonding pad and the second bonding pad. The method may further include compressing the bonded wire into the capillary.

본 발명은 다층으로 적층된 구조의 반도체 패키지에서 적층된 각 칩의 본딩 패드들과 배선 기판의 패드 사이의 본딩 방식을 개선하여 제조 단가를 줄이고 제조가 용이하도록 할 수 있다.The present invention can reduce the manufacturing cost and facilitate manufacturing by improving the bonding method between the bonding pads of each chip and the pad of the wiring board in the stacked semiconductor package.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2는 본 발명의 제 1 실시예에 따라 와이어 본딩된 반도체 패키지의 모습을 보여주는 사시도이다.2 is a perspective view illustrating a wire bonded semiconductor package according to a first embodiment of the present invention.

이하의 설명에서는 설명의 편의를 위해 3개의 칩이 적층된 반도체 패키지를 실시예로 설명하고 있으나 이에 한정되지는 않는다.In the following description, for convenience of description, a semiconductor package in which three chips are stacked is described as an embodiment, but is not limited thereto.

본 발명의 반도체 패키지는 에지 영역에 복수의 본딩 패드들을 갖는 서로 다른 크기의 복수의 칩들(200 ∼ 400)이 배선 기판(100) 상에 순차적으로 적층되어 있다. 이때, 상부에 적층된 칩은 그 하부 칩보다 작은 크기를 가지며 하부 칩의 본딩 패드들이 노출되도록 적층된다.In the semiconductor package of the present invention, a plurality of chips 200 to 400 of different sizes having a plurality of bonding pads in an edge region are sequentially stacked on the wiring board 100. In this case, the chips stacked on the upper portion have a smaller size than the lower chips and are stacked such that the bonding pads of the lower chips are exposed.

즉, 제 1 칩(200) 상에 적층된 제 2 칩(300)은 제 1 칩(200)의 본딩 패드들(220)을 노출시킬 수 있는 크기를 가지며, 제 2 칩(300) 상에 적층된 제 3 칩(400)은 제 2 칩(300)의 본딩 패드들(320)을 노출시킬 수 있는 크기를 갖는다.That is, the second chip 300 stacked on the first chip 200 has a size that can expose the bonding pads 220 of the first chip 200, and is stacked on the second chip 300. The third chip 400 is sized to expose the bonding pads 320 of the second chip 300.

그리고 배선 기판(100)의 각 패드들(120) 및 각 패드(120)에 공통 연결되는 적층된 칩들(200 ∼ 400)의 본딩 패드들(220 ∼ 420)은 하나의 본딩 와이어(500)에 의해 전기적으로 연결된다. 즉, 본 발명에서는 도 1과 같이 적층된 칩들의 각 본딩 패드들(22, 42)와 패드(12)를 루프 형태로 각각 연결하지 않고, 각 패드(120) 및 이와 와이어 본딩 될 본딩 패드들(해당 패드와 상하로 동일 라인 상에 있는 본딩 패드들)(220 ∼ 420)을 하나의 와이어(500)로 연속적으로 연결시킨다.The pads 120 and the bonding pads 220 to 420 of the stacked chips 200 to 400 commonly connected to the pads 120 of the wiring board 100 are connected by one bonding wire 500. Electrically connected. That is, in the present invention, the bonding pads 22 and 42 and the pads 12 of the chips stacked as shown in FIG. 1 are not connected to each other in a loop form, but the pads 120 and the bonding pads to be wire bonded thereto ( Bonding pads 220 to 420 on the same line up and down with the corresponding pad are continuously connected to one wire 500.

특히, 본 실시예에서 사용된 본딩 와이어(500)는 종래와 같이 그 단면이 원 형상으로 이루어진 가는 선모양의 와이어가 아니라 도 3에서와 같이 단면이 직사각 형상으로 이루어진 두께가 얇은 벨트 형상[이하, 플랫 와이어(flat wire)라 함]을 갖는다.In particular, the bonding wire 500 used in the present embodiment is not a thin wire-shaped wire whose cross section is circular as in the prior art, but a thin belt shape having a thin cross section as shown in FIG. 3 [hereinafter, Flat wire.

도 2에서는 플랫 와이어(500)가 본딩 패드들(220 ∼ 420)의 상부면 전체를 피복하면서 계단식으로 연속적으로 형성된 모습을 보여주고 있으나, 상부면의 일부만이 피복되도록 형성될 수도 있다. 즉, 플랫 와이어(500)의 폭은 본딩 패드들(220 ∼ 420)의 폭과 같거나 본딩 패드들(220 ∼ 420)의 폭 보다 좁게 형성될 수 있다.In FIG. 2, the flat wire 500 covers the entire upper surfaces of the bonding pads 220 to 420 and is formed in a stepwise manner. However, only a part of the upper surface may be formed. That is, the width of the flat wire 500 may be formed to be equal to the width of the bonding pads 220 to 420 or smaller than the width of the bonding pads 220 to 420.

도 3에서와 같이 본딩 와이어가 편평한 플랫 와이어 형태로 형성되는 경우에는 와이어 본딩시 본딩 와이어를 안내하는 캐필러리(capillary)의 구조도 이에 맞게 변형되어야 한다.When the bonding wire is formed in a flat flat wire shape as shown in FIG. 3, the structure of a capillary that guides the bonding wire during wire bonding should also be modified accordingly.

도 4는 본 발명에 따른 플랫 와이어(500)를 사용할 수 있도록 구성된 캐필러리(capillary)의 구조를 보여주는 도면이다.4 is a view showing the structure of a capillary (capillary) configured to use the flat wire 500 according to the present invention.

도 4에서와 같이, 캐필러리(600)의 노즐은 플랫 와이어(500)가 통과하여 토출될 수 있도록 플랫 와이어(500)의 단면과 같은(또는 조금 큰) 크기의 직사각 형상을 갖도록 형성되며, 캐필러리(600) 내부의 관통구도 역시 플랫 와이어(500)의 단면과 같은 직사각 형상을 갖도록 형성된다.As shown in FIG. 4, the nozzle of the capillary 600 is formed to have a rectangular shape having the same size as (or slightly larger than) the cross section of the flat wire 500 so that the flat wire 500 can be discharged through the flat wire 500. The through hole inside the capillary 600 is also formed to have a rectangular shape such as a cross section of the flat wire 500.

도 5a 및 도 5b는 본 발명의 플랫 와이어(500)를 이용하여 본딩 패드들(220 ∼ 420)과 패드(120)를 패드 투 패드(pad to pad) 방식으로 본딩한 모습을 보여주는 도면이다.5A and 5B illustrate bonding of the bonding pads 220 to 420 and the pad 120 in a pad to pad manner using the flat wire 500 of the present invention.

도 5a를 참조하면, 먼저 와이어 스풀(미도시)에 권선된 플랫 와이어(500)가 디버터(미도시)에 의해 일정한 장력이 유지되면서 캐필러리(600)에 연결된다.Referring to FIG. 5A, first, a flat wire 500 wound on a wire spool (not shown) is connected to the capillary 600 while maintaining a constant tension by a diverter (not shown).

다음에, 히터블럭(미도시)를 이용하여 본딩 패드들(220 ∼ 420)에 열을 가하면서 캐필러리(600)를 강하시켜 플랫 와이어(500)를 본딩 패드(420) 상부면의 내측 말단부(도면에서 본딩 패드의 왼쪽 말단부)에 접합시킨 후 캐필러리(600)를 칩(400)의 외측 방향(도면에서 오른쪽 방향)으로 칩(400)의 말단까지(바람직하게는 본딩 패드(320) 상부면의 내측 말단부 상부까지) 수평이동시켜 본딩 패드(420)를 플랫 와이어(500)로 피복시킨다.Next, the capillary 600 is lowered while applying heat to the bonding pads 220 to 420 using a heater block (not shown), thereby flattening the flat wire 500 to the inner end of the upper surface of the bonding pad 420. After bonding to the (left end of the bonding pad in the drawing), the capillary 600 to the end of the chip 400 in the outward direction of the chip 400 (preferably in the drawing) (preferably the bonding pad 320) Horizontally) to cover the bonding pads 420 with the flat wire 500.

다음에, 다시 캐필러리(600)를 강하시켜 플랫 와이어(500)를 칩(300)의 상부면(바람직하게는 본딩 패드(320) 상부면의 내측 말단부)에 접합시킨 후 캐필러리(600)를 칩(300)의 외측 방향으로 칩(300)의 말단까지(바람직하게는 본딩 패드(220) 상부면의 내측 말단부 상부까지) 수평이동시켜 본딩 패드(320)를 플랫 와이어(500)로 피복시킨다. 이때, 캐필러리(600)를 강하시켜 플랫 와이어(500)를 칩(300)의 상부면에 접합시킬 때 플랫 와이어(500)가 칩(400)의 측면에 밀착되게 형성되도록 할 수 있다.Next, the capillary 600 is lowered again to bond the flat wire 500 to the upper surface of the chip 300 (preferably the inner end of the upper surface of the bonding pad 320), and then the capillary 600. ) Is horizontally moved in the outward direction of the chip 300 to the end of the chip 300 (preferably to the upper end of the inner end of the upper surface of the bonding pad 220) to cover the bonding pad 320 with the flat wire 500. Let's do it. At this time, when the capillary 600 is lowered to bond the flat wire 500 to the upper surface of the chip 300, the flat wire 500 may be formed to be in close contact with the side surface of the chip 400.

다음에, 다시 캐필러리(600)를 강하시켜 플랫 와이어(500)를 칩(200)의 상부면(바람직하게는 본딩 패드(220) 상부면의 내측 말단부)에 접합시킨 후 캐필러리(600)를 칩(200)의 외측 방향으로 칩(200)의 말단까지(바람직하게는 패드(120) 상부면의 내측 말단부 상부까지) 수평이동시켜 본딩 패드(220)를 플랫 와이어(500)로 피복시킨다. 이때도 캐필러리(600)를 강하시켜 플랫 와이어(500)를 칩(200)의 상부면에 접합시킬 때 플랫 와이어(500)가 칩(300)의 측면에 밀착되게 형성되도록 할 수 있다.Next, the capillary 600 is lowered again to bond the flat wire 500 to the upper surface of the chip 200 (preferably the inner end of the upper surface of the bonding pad 220), and then the capillary 600. ) Is horizontally moved to the end of the chip 200 in the outward direction of the chip 200 (preferably to the top of the inner end portion of the upper surface of the pad 120) to cover the bonding pad 220 with the flat wire 500. . In this case, when the capillary 600 is lowered to bond the flat wire 500 to the upper surface of the chip 200, the flat wire 500 may be formed to be in close contact with the side surface of the chip 300.

다음에, 다시 캐필러리(600)를 강하시켜 플랫 와이어(500)를 배선 기판(100)의 상부면(바람직하게는 패드(120) 상부면의 내측 말단부)에 접합시킨 후 캐필러리(600)를 배선 기판(100)의 외측 방향으로 일정 거리 만큼 수평이동시켜 패드(120)의 상부면 전체 또는 일부를 플랫 와이어(500)로 피복시킨다. 이때도, 캐필러리(600)를 강하시켜 플랫 와이어(500)를 기판(100)의 상부면에 접합시킬 때 플랫 와이어(500)가 칩(200)의 측면에 밀착되게 형성되도록 할 수 있다.Next, the capillary 600 is lowered again to bond the flat wire 500 to the upper surface of the wiring board 100 (preferably the inner end of the upper surface of the pad 120), and then the capillary 600. ) Is horizontally moved by a predetermined distance in the outward direction of the wiring board 100 to cover the whole or part of the upper surface of the pad 120 with the flat wire 500. In this case, when the capillary 600 is lowered to bond the flat wire 500 to the upper surface of the substrate 100, the flat wire 500 may be formed to be in close contact with the side surface of the chip 200.

다음에, 플랫 와이어(500)를 와이어 클램프(미도시)로 클램핑하면서 당겨 올리고 절단함으로써 본딩 패드들(220 ∼ 420)과 패드(120)이 하나의 와이어에 의해 공통 연결된다.Next, the bonding pads 220 to 420 and the pad 120 are commonly connected by one wire by pulling up and cutting the flat wire 500 while clamping it with a wire clamp (not shown).

다음에, 도 5b에서와 같이 캐필러리(600)를 다시 본딩 패드(420) 상부로 이동시킨 후 플랫 와이어(500)를 클램핑한 상태에서 캐필러리(600)만을 하강시켜 캐 필러리(600)로 본딩 패드(420)에 피복된 플랫 와이어(500)를 눌러줌으로써 플랫 와이어(500)가 본딩 패드(420)에 보다 안정적으로 압착될 수 있도록 해준다. 이때, 압착 횟수 또는 압착 위치는 다양하게 변화될 수 있다.Next, as shown in FIG. 5B, the capillary 600 is moved to the upper side of the bonding pad 420 again, and only the capillary 600 is lowered while the flat wire 500 is clamped to lower the capillary 600. By pressing the flat wire 500 coated on the bonding pad 420, the flat wire 500 can be more stably pressed onto the bonding pad 420. At this time, the number of times or the pressing position may be variously changed.

본딩 패드(420)에 대한 압착이 완료되면, 나머지 본딩 패드들(320, 220) 및 패드(120)에 대해서도 같은 방법으로 순차적으로 압착을 수행함으로써 본 발명에 따른 와이어 본딩을 완료된다.When the pressing of the bonding pads 420 is completed, the bonding of the remaining bonding pads 320, 220 and the pad 120 is sequentially performed in the same manner to complete wire bonding according to the present invention.

본 실시예에서는 최상층의 본딩 패드(420)에서부터 배선기판(100)의 패드(120)까지 위에서부터 아래로 순차적으로 플랫 와이어(500)를 연결하는 경우를 나타내고 있으나, 반대로 패드(120)에서부터 최상층의 본딩 패드(420)까지 아래에서 위로 순차적으로 플랫 와이어(500)를 연결할 수도 있다. 즉, 캐필러리를 수평이동 및 하강시키는 과정 대신에 수평이동 및 상승시키는 과정을 통해 아래에서부터 위로의 와이어 연결을 수행할 수 있다.In the present exemplary embodiment, the flat wire 500 is sequentially connected from the topmost bonding pad 420 to the pad 120 of the wiring board 100 from top to bottom. The flat wire 500 may be sequentially connected from the bottom to the bonding pad 420. That is, instead of horizontally moving and lowering the capillary, the wire connection from bottom to top may be performed by horizontally moving and raising the capillary.

도 6은 본 발명의 제 2 실시예에 따라 와이어 본딩된 반도체 패키지의 모습을 보여주는 사시도이다.6 is a perspective view illustrating a wire bonded semiconductor package according to a second embodiment of the present invention.

본 실시예는 상술한 제 1 실시예와 비교하여 본딩에 사용된 와이어의 형태에서 차이가 있다.This embodiment differs in the form of wire used for bonding as compared to the first embodiment described above.

즉, 본 실시예에서는 패드(120)와 본딩 패드들(220 ∼ 420)을 하나의 와이어로 공통 연결하는 것은 제 1 실시예에서와 동일하나 플랫 와이어(500)를 본딩 와이어로 사용하지 않고 종래와 같이 단면이 원 형상으로 이루어진 선형 와이어를 본딩 와이어로 사용한다. 따라서 이러한 경우에는 캐필러리도 종래의 것을 그대로 사용 할 수 있다.That is, in this embodiment, the common connection between the pad 120 and the bonding pads 220 to 420 with one wire is the same as in the first embodiment, but the flat wire 500 is not used as the bonding wire. Likewise, a linear wire having a circular cross section is used as a bonding wire. Therefore, in this case, a capillary can also use a conventional thing as it is.

이러한 선형 와이어를 이용한 패드 투 패드 방식의 본딩 방법은 상술한 도 5a 및 도 5b에서와 같은 방법으로 수행될 수 있다. 다만, 선형 와이어의 굵기가 너무 가늘면 와이어를 압착하는 과정에서 선형 와이어가 끊어지면서 정상적으로 접착이 이루어지지 않을 수 있으므로 그러한 끊어짐이 발생되지 않도록 선형 와이어의 굵기 및 압착 압력을 적절히 조절하는 것이 바람직하다.The pad-to-pad bonding method using the linear wire may be performed in the same manner as in FIGS. 5A and 5B. However, if the thickness of the linear wire is too thin, since the linear wire may be disconnected normally in the process of compressing the wire, it is preferable to appropriately adjust the thickness and the pressing pressure of the linear wire so that such breakage does not occur.

또한, 상술한 실시예들에서는 본딩 와이어로 플랫 와이어와 선형 와이어를 사용하는 경우만을 설명하였으나 이외에 다양한 형태의 와이어를 사용할 수도 있다. 예컨대, 단면이 타원 형상인 와이어 또는 단면이 정사각 형상인 와이어가 사용될 수도 있다.In addition, in the above-described embodiments, only the case of using the flat wire and the linear wire as the bonding wire has been described, but various types of wires may be used. For example, an elliptic cross section or a square cross section may be used.

아울러 본 발명의 바람직한 실시 예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

도 1은 종래의 적층 반도체 패키지에서 와이어 본딩된 모습을 보여주는 도면.1 is a view showing a wire bonded state in a conventional laminated semiconductor package.

도 2는 본 발명의 제 1 실시예에 따라 와이어 본딩된 반도체 패키지의 모습을 보여주는 사시도.2 is a perspective view showing a state of a wire bonded semiconductor package according to the first embodiment of the present invention.

도 3은 본 발명에 따른 플랫 와이어의 형태를 보여주는 도면.3 shows the shape of a flat wire according to the invention.

도 4는 본 발명에 따른 플랫 와이어를 사용할 수 있도록 구성된 캐필러리의 구조를 보여주는 도면.Figure 4 shows the structure of a capillary configured to be able to use a flat wire according to the present invention.

도 5a 및 도 5b는 본 발명의 플랫 와이어를 이용하여 본딩 패드들과 패드를 패드 투 패드 방식으로 본딩하는 모습을 보여주는 도면.5A and 5B are views illustrating bonding pads and pads in a pad-to-pad manner by using the flat wire of the present invention.

도 6은 본 발명의 제 2 실시예에 따라 와이어 본딩된 반도체 패키지의 모습을 보여주는 사시도.6 is a perspective view showing a state of a wire bonded semiconductor package according to the second embodiment of the present invention.

Claims (13)

패드를 갖는 배선 기판;A wiring board having a pad; 상기 배선 기판상에 적층되며 본딩 패드를 갖는 하나 이상의 반도체 칩; 및One or more semiconductor chips stacked on the wiring substrate and having bonding pads; And 상기 본딩 패드들과 상기 패드를 연속적으로 연결시켜 주며 그 단면이 사각 형상으로 형성된 플랫 와이어를 포함하는 적층 반도체 패키지.And a flat wire connecting the bonding pads to the pads continuously and having a square cross section. 제 1항에 있어서, 상기 플랫 와이어는The method of claim 1, wherein the flat wire 최상층에 적층된 상기 반도체 칩의 상기 본딩 패드부터 상기 패드까지 동일 라인 상에 있는 상기 본딩 패드들과 상기 패드를 연속적으로 연결시켜 주는 하나의 와이어인 것을 특징으로 하는 적층 반도체 패키지.And a wire connecting the bonding pads on the same line and the pad from the bonding pad to the pad of the semiconductor chip stacked on the uppermost layer. 제 1항에 있어서, 상기 플랫 와이어는The method of claim 1, wherein the flat wire 상기 본딩패드와 접합되는 면의 폭이 높이 보다 큰 직사각 형상인 것을 특징으로 하는 적층 반도체 패키지.Laminated semiconductor package, characterized in that the width of the surface bonded to the bonding pad is larger than the rectangular shape. 제 3항에 있어서, 상기 플랫 와이어는The method of claim 3, wherein the flat wire 상기 본딩패드와 접합되는 면의 폭이 상기 본딩패드의 폭보다 좁거나 같은 것을 특징으로 하는 적층 반도체 패키지.The width of the surface to be bonded to the bonding pad is smaller than or equal to the width of the bonding pad laminated semiconductor package. 제 1항에 있어서, 상기 플랫 와이어는The method of claim 1, wherein the flat wire 상기 본딩 패드들 및 상기 패드의 상부면을 피복하면서 상기 본딩 패드들 및 상기 패드를 연속적으로 연결시키는 것을 특징으로 하는 적층 반도체 패키지.And the bonding pads and the pads are continuously connected to each other while covering the bonding pads and the upper surfaces of the pads. 제 1항에 있어서, 상기 플랫 와이어는The method of claim 1, wherein the flat wire 상기 적층된 반도체 칩의 상면 및 측면에 밀착되게 형성되어 있는 것을 특징으로 하는 적층 반도체 패키지.The laminated semiconductor package, characterized in that formed in close contact with the upper and side surfaces of the stacked semiconductor chip. 제 1 칩 상의 제 1 본딩 패드에 본딩 와이어를 접합시키는 단계;Bonding the bonding wires to a first bonding pad on the first chip; 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 제 1 본딩 패드를 피복하는 단계;Horizontally moving a capillary to cover said first bonding pad with said bonding wire; 상기 캐필러리를 하강시켜 상기 제 1 칩의 하부에 있는 제 2 칩 상의 제 2 본딩 패드에 상기 본딩 와이어를 접합시키는 단계;Lowering the capillary to bond the bonding wires to a second bonding pad on a second chip below the first chip; 상기 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 제 2 본딩 패드를 피복하는 단계; 및Horizontally moving the capillary to cover the second bonding pad with the bonding wire; And 상기 캐필러리를 하강시켜 상기 제 2 칩의 하부에 있는 배선 기판의 패드에 상기 본딩 와이어를 접합시키는 단계를 포함하는 적층 반도체 패키지의 와이어 본딩 방법.Lowering the capillary to bond the bonding wire to a pad of a wiring substrate under the second chip. 제 7항에 있어서,The method of claim 7, wherein 상기 캐필러리를 수평이동시켜 상기 본딩 와이어로 상기 패드의 일부를 피복하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지의 와이어 본딩 방법.Horizontally moving the capillary to cover a portion of the pad with the bonding wire. 제 7항 또는 제 8항에 있어서,The method according to claim 7 or 8, 상기 제 1 본딩 패드 및 상기 제 2 본딩 패드 상부에 피복된 상기 본딩 와이어를 상기 캐필러리로 압착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지의 와이어 본딩 방법.And compressing the bonding wires coated on the first bonding pads and the second bonding pads with the capillary. 제 7항에 있어서, 상기 캐필러리가 하강하는 위치는8. The position of claim 7, wherein the capillary is lowered 상기 본딩 패드의 상부면 내측 말단부인 것을 특징으로 하는 적층 반도체 패키지의 와이어 본딩 방법.Wire bonding method of a laminated semiconductor package, characterized in that the inner end portion of the upper surface of the bonding pad. 배선 기판의 패드에 본딩 와이어를 접합시키는 단계;Bonding the bonding wires to the pads of the wiring board; 캐필러리를 상승 및 수평이동시켜 상기 본딩 와이어로 상기 배선 기판의 상부에 있는 제 1 칩 상의 제 1 본딩 패드를 피복하는 단계; 및Raising and horizontally moving the capillary to coat the first bonding pad on the first chip on the wiring substrate with the bonding wire; And 상기 캐필러리를 상승 및 수평이동시켜 상기 본딩 와이어로 상기 제 1 칩의 상부에 있는 제 2 칩 상의 제 2 본딩 패드를 피복하는 단계를 포함하는 적층 반도체 패키지의 와이어 본딩 방법.Lifting and capturing the capillary to coat the second bonding pad on the second chip on top of the first chip with the bonding wire. 제 11항에 있어서,The method of claim 11, 상기 배선 기판의 패드에 접합된 본딩 와이어를 수평이동시켜 상기 패드의 적어도 일부를 피복하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지의 와이어 본딩 방법.And horizontally moving the bonding wires bonded to the pads of the wiring board to cover at least a part of the pads. 제 11항 또는 제 12항에 있어서,The method of claim 11 or 12, 상기 제 1 본딩 패드 및 상기 제 2 본딩 패드 상부에 피복된 상기 본딩 와이어를 상기 캐필러리로 압착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지의 와이어 본딩 방법.And compressing the bonding wires coated on the first bonding pads and the second bonding pads with the capillary.
KR1020080096641A 2008-10-01 2008-10-01 Stacked semiconductor package having pad to pad bonding structure and wire bonding method of the same KR20100037351A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2525403A1 (en) * 2011-05-18 2012-11-21 SanDisk Semiconductor (Shanghai) Co., Ltd. Waterfall wire bonding
US8890333B2 (en) 2012-07-06 2014-11-18 Samsung Electronics Co., Ltd. Apparatus for stacked semiconductor chips
US10147706B2 (en) 2016-10-24 2018-12-04 Samsung Electronics Co., Ltd. Multi-chip package and method of manufacturing the same
FR3090435A1 (en) * 2018-12-19 2020-06-26 Stmicroelectronics (Grenoble 2) Sas Wire welding tool

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2525403A1 (en) * 2011-05-18 2012-11-21 SanDisk Semiconductor (Shanghai) Co., Ltd. Waterfall wire bonding
US8890333B2 (en) 2012-07-06 2014-11-18 Samsung Electronics Co., Ltd. Apparatus for stacked semiconductor chips
US9087883B2 (en) 2012-07-06 2015-07-21 Samsung Electronics Co., Ltd. Method and apparatus for stacked semiconductor chips
US10147706B2 (en) 2016-10-24 2018-12-04 Samsung Electronics Co., Ltd. Multi-chip package and method of manufacturing the same
US10679972B2 (en) 2016-10-24 2020-06-09 Samsung Electronics Co., Ltd. Method of manufacturing multi-chip package
FR3090435A1 (en) * 2018-12-19 2020-06-26 Stmicroelectronics (Grenoble 2) Sas Wire welding tool

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