KR20100036046A - Organic light emitting diodde desplay device - Google Patents

Abstract

PURPOSE: A damage of the electrical contact of the upper plate and lower plate are prevented by forming the elastic layer having the coefficient of elasticity which the organic light-emitting DIODE indicating device relatively highs within the TFT array of the lower plate. CONSTITUTION: An organic light-emitting diode device array comprises the anode electrode(ANO), and the organic compound layer and cathode electrode(CAT). The upper plate comprises the contact space covered with the cathode electrode. The TFT array comprises the cathode electrode formed on the contact space and electrically touched an plurality of TFTs. The elastic layer comprises one or greater among the inorganic material having the coefficient of elasticity of the organic compound and 0.19 ~ 0.5 having the coefficient of elasticity of 10 ~ 40.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODDE DESPLAY DEVICE}

The present invention relates to an organic light emitting diode display device.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

An active matrix type organic light emitting diode display (AMOLED) is an organic light emitting diode device (hereinafter referred to as "OLED") using a thin film transistor ("TFT"). Display the image by controlling the current flowing through the The structure of the organic light emitting diode display device has been developed in various directions.

In the organic light emitting diode display device, a portion where the upper plate and the lower plate contact each other may be damaged by an external impact. When the part where the upper plate and the lower plate are in contact is a portion that electrically connects the upper plate and the lower plate, current paths between the upper plate and the lower plate may be blocked due to breakage of the portion. Therefore, there is a demand for a method of preventing the electrical contact between the upper and lower plates from being damaged by an external impact in the organic light emitting diode display device.

Accordingly, an object of the present invention is to provide an organic light emitting diode display device capable of preventing the electrical contact portion of the upper plate and the lower plate is broken as the invention devised to solve the problems of the prior art.

In order to achieve the above object, an organic light emitting diode display device according to an embodiment of the present invention includes an organic light emitting diode device array including an anode electrode, an organic compound layer and a cathode electrode, and an upper plate including a contact spacer covered by the cathode electrode; And a TFT array including a plurality of TFTs in electrical contact with a cathode electrode formed on the contact spacer, an organic material having an elastic modulus of 10 (gpa) to 40 (gpa), and an elasticity of 0.19 (gpa) to 0.5 (gpa). And a bottom plate comprising an elastic layer comprising at least one of inorganics having a modulus.

The organic light emitting diode display device of the present invention forms an elastic layer having a relatively high modulus of elasticity in the TFT array of the lower plate, thereby preventing breakage of the electrical contact between the upper plate and the lower plate, and improving reliability.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 3.

1 shows a cross-sectional structure of one cell in an organic light emitting diode display device according to a first embodiment of the present invention. The equivalent circuit diagram of this organic light emitting diode display element is substantially the same as that in FIG. In FIG. 1, the storage capacitor CST, the high potential power supply pad, and the low potential power supply pad formed on the lower plate are omitted.

Referring to FIG. 1, an organic light emitting diode display according to a first exemplary embodiment of the present invention includes a top plate on which a passive OLED array is formed and a bottom plate on which a TFT array is formed.

The passive OLED array includes an auxiliary electrode MBUS, an anode electrode ANO, a buffer layer BUF, an organic light emitting diode device OLED, a cathode electrode CAT, a barrier BAR, and a contact spacer CSP. The auxiliary electrode MBUS is formed of a highly conductive metal on the upper transparent substrate SUBS1. The anode ANO is formed of indium tin oxide (ITO) on the upper transparent substrate SUBS1 to cover the auxiliary electrode MBUS. The anode electrode ANO is supplied with a high potential power voltage VDD through a contact spacer connected to a high potential power pad on a lower plate. A buffer layer BUF made of SiNx is formed on the anode ANO, and the cathode electrode CAT is formed on the organic compound layer of the organic light emitting diode OLED by aluminum. The organic light emitting diode device (OLED) is an electron injection layer (EIL), an electron transport layer (ETL), an emission layer (EML), a hole transport layer (HTL), and a hole injection Layer (Hole injection layer, HIL). The barrier BAR separates the organic light emitting diode OLED and the cathode electrode CAT between adjacent light emitting cells. The contact spacer CSP is formed on the buffer layer BUF by polyimide or photoresist. On the contact spacer CSP, an organic compound layer of the organic light emitting diode device OLED and a cathode electrode CAT are stacked.

The TFT array is connected to a plurality of data lines and a plurality of gate lines crossing each other, switch TFTs (SWTFT) and switch TFTs (SWTFT) formed at the intersections of the data lines and the gate lines, and contact pad upper and lower electrodes (CNTPU). , The driving TFTs DRTFT connected to the cathode electrode CAT of the upper plate through the CNTPL, and the storage capacitor CST connected between the gate electrode G2 and the low potential power supply VSS of the driving TFT DRTFT. ), And the like.

The gate line, the gate electrodes G1 and G2 of the TFTs SWTFT and DRTFT, and the gate pad lower electrode GPADL connected to the gate line are formed of a gate metal pattern. The data line crossing the gate line, the source and drain electrodes S1, S2, D1 and D2 of the TFTs SWTFT and DRTFT and the data pad lower electrode DPADL connected to the data line are formed of a data metal pattern.

An elastic layer ELST, a gate insulating layer GI, and active patterns ACT1 and ACT2 are formed between the gate metal pattern and the data metal pattern. The active patterns ACT1 and ACT2 include a semiconductor material to form channels of the TFTs SWTFT and DRTFT. The gate insulating layer GI insulates the gate metal pattern from the data metal pattern. The elastic layer ELST absorbs the shock transmitted from the upper or lower plate when the impact is applied from the outside to the upper or lower plate while the upper plate and the lower plate are bonded with the sealant so that the upper plate and the lower plate are in electrical contact with each other. The breakdown of the CSP, the cathode electrode CAT, and the contact electrodes CNTPL and CNTPU is prevented. The passivation layer PAS1 is formed on the data metal pattern.

The jumper metal pattern JUMP electrically connects the drain electrode D1 of the switch TFT SWTFT and the gate electrode G1 of the driving TFT DRTFT. To this end, the jumper metal pattern JUMP passes through the passivation layer PAS1 to the drain electrode D1 of the switch TFT SWTFT through a first contact hole exposing the drain electrode D1 of the switch TFT SWTFT. And a second contact hole through the passivation layer PAS1, the gate insulating layer GI, and the elastic layer ELST to expose the gate electrode G2 of the driving TFT DRTFT. It contacts the gate electrode G2.

The contact pad upper electrode CNTPU is in contact with the cathode electrode CAT of the upper plate, and the contact pad lower electrode CNTPL formed below is in contact with the drain electrode D2 of the driving TFT DRTFT formed on the lower plate. To this end, the contact pad lower electrode CNTPL passes through the passivation layer PAS1 and exposes the drain electrode D2 of the driving TFT DRTFT to expose the drain electrode D2 of the driving TFT DRTFT. Is in contact with.

The gate pad upper electrode GPADU passes through the passivation layer PAS1, the gate insulating layer GI, and the elastic layer ELST to pass through the fourth contact hole exposing the gate pad lower electrode GPADL. ) The data pad upper electrode DPADU is in contact with the data pad lower electrode DPADL through a fifth contact hole penetrating the passivation layer PAS1 and exposing the data pad lower electrode DPADL.

The elastic layer (ELST) is formed with a thickness (t1) of about 500 (Å) to 1000 (Å) to sufficiently absorb external shocks without significantly adding process water and cost, and 10 (gpa) to 40 ( gpa) may be formed of an organic material having an elastic modulus. The organic material may include a polymer compound such as polyimide, and the like, but is not limited thereto and may include one or more organic materials satisfying the elastic modulus.

3 illustrates a cross-sectional structure of one cell in the organic light emitting diode display device according to the second embodiment of the present invention. The equivalent circuit diagram of this organic light emitting diode display element is substantially the same as that in FIG. In FIG. 2, the storage capacitor CST, the high potential power supply pad, and the low potential power supply pad formed on the lower plate are omitted.

Referring to FIG. 3, the organic light emitting diode display according to the first embodiment of the present invention includes a top plate on which a passive OLED array is formed and a bottom plate on which a TFT array is formed. Since the top plate is substantially the same as the above-described embodiment, a detailed description thereof will be omitted.

The TFT array is connected to a plurality of data lines and a plurality of gate lines crossing each other, switch TFTs (SWTFT) and switch TFTs (SWTFT) formed at the intersections of the data lines and the gate lines, and contact pad upper and lower electrodes (CNTPU). , The driving TFTs DRTFT connected to the cathode electrode CAT of the upper plate through the CNTPL, and the storage capacitor CST connected between the gate electrode G2 and the low potential power supply VSS of the driving TFT DRTFT. ), And the like.

The gate line, the gate electrodes G1 and G2 of the TFTs SWTFT and DRTFT, and the gate pad lower electrode GPADL connected to the gate line are formed of a gate metal pattern. The data line crossing the gate line, the source and drain electrodes S1, S2, D1 and D2 of the TFTs SWTFT and DRTFT and the data pad lower electrode DPADL connected to the data line are formed of a data metal pattern.

The first and second elastic layers ELST1 and ELST2, the gate insulating layer GI, and the active patterns ACT1 and ACT2 are formed between the gate metal pattern and the data metal pattern. The active patterns ACT1 and ACT2 include a semiconductor material to form channels of the TFTs SWTFT and DRTFT. The gate insulating layer GI insulates the gate metal pattern from the data metal pattern. The first and second elastic layers ELST1 and ELST2 absorb the shock transmitted from the upper plate or the lower plate when the impact is applied to the upper plate or the lower plate from the outside while the upper plate and the lower plate are bonded with the sealant. The contact spacers CSP, the cathode electrodes CAT, and the contact electrodes CNTPL and CNTPU that are in electrical contact with each other are prevented. The passivation layer PAS1 is formed on the data metal pattern.

The jumper metal pattern JUMP electrically connects the drain electrode D1 of the switch TFT SWTFT and the gate electrode G1 of the driving TFT DRTFT. To this end, the jumper metal pattern JUMP passes through the passivation layer PAS1 to the drain electrode D1 of the switch TFT SWTFT through a first contact hole exposing the drain electrode D1 of the switch TFT SWTFT. The first contacting layer is formed through the passivation layer PAS1, the gate insulating layer GI, the first elastic layer ELST1, and the second elastic layer ELST2 to expose the gate electrode G2 of the driving TFT DRTFT. The gate electrode G2 of the driving TFT DRTFT is contacted through two contact holes.

The contact pad upper electrode CNTPU is in contact with the cathode electrode CAT of the upper plate, and the contact pad lower electrode CNTPL formed below is in contact with the drain electrode D2 of the driving TFT DRTFT formed on the lower plate. To this end, the contact pad lower electrode CNTPL passes through the passivation layer PAS1 and exposes the drain electrode D2 of the driving TFT DRTFT to expose the drain electrode D2 of the driving TFT DRTFT. Is in contact with.

The gate pad upper electrode GPADU passes through the passivation layer PAS1, the gate insulating layer GI, the first elastic layer ELST1, and the second elastic layer ELST2 to expose the gate pad lower electrode GPADL. 4 contacts the gate pad lower electrode GPADL through a contact hole. The data pad upper electrode DPADU is in contact with the data pad lower electrode DPADL through a fifth contact hole penetrating the passivation layer PAS1 and exposing the data pad lower electrode DPADL.

The first and second elastic layers ELST1 and ELST2 should be capable of sufficiently absorbing external shocks without significantly adding process water and process costs. To this end, the thickness t2 of the first and second elastic layers ELST1 and ELST2 is preferably about 500 (mm) to about 1000 (mm). The first elastic layer ELST1 is formed of an organic material, and the second elastic layer ELST2 is formed of an inorganic material. The organic material applicable to the first elastic layer ELST1 may include a polymer compound such as polyimide, and the like, but is not limited thereto, and may include one or more organic materials satisfying an elastic modulus of about 10 (gpa) to about 40 (gpa). It may include. Examples of the inorganic material applicable to the second elastic layer ELST2 may include molybdenum (Mo) and the like, and the present invention is not limited thereto, and may be selected as any organic material satisfying an elastic modulus of about 0.19 (gpa) to 0.5 (gpa). Can be. On the other hand, when the second elastic layer ELST2 is formed of a conductive metal, an unwanted short may be generated between the metal patterns in the TFT array. In order to prevent such a short circuit problem, the second elastic layer ELST2 may be partially patterned without being formed entirely on the TFT array. For example, in FIG. 3, the second elastic layer ELST2 is not formed around the metal patterns so as not to contact the jumper metal pattern JUMP and the gate pad upper electrode GPADU.

As described above, the organic light emitting diode display device of the present invention forms an elastic layer having a relatively high modulus of elasticity in the TFT array so that an impact transmitted through the upper or lower plate in the state where the upper and lower plates are bonded is absorbed by the elastic layer. Therefore, it is possible to prevent breakage of the electrical contact between the upper and lower plates and to increase reliability.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram illustrating one cell of the organic light emitting diode display device of FIG. 1.

3 is a cross-sectional view illustrating an organic light emitting diode display device according to a second exemplary embodiment of the present invention.

Claims (6)

An organic light emitting diode device array including an anode electrode, an organic compound layer, and a cathode electrode, and an upper plate including a contact spacer covered by the cathode electrode; And A TFT array including a plurality of TFTs in electrical contact with a cathode electrode formed on the contact spacer, an organic material having an elastic modulus of 10 (gpa) to 40 (gpa), and an elastic modulus of 0.19 (gpa) to 0.5 (gpa) An organic light emitting diode display device comprising: a lower plate including an elastic layer including at least one of inorganic materials having a structure. The method of claim 1, The thickness of the elastic layer is an organic light emitting diode display device, characterized in that 500 ~ 1000 (Å). The method of claim 2, The lower plate, A gate metal pattern including a gate line, a gate electrode of the TFT, and a gate pad lower electrode connected to the gate line; A data metal pattern including a data line crossing the gate line, a source and drain electrode of the TFT, and a data pad lower electrode connected to the data line; And An active pattern including a gate insulating layer and a semiconductor formed between the gate metal pattern and the data metal pattern; And the elastic layer comprises an organic material layer formed between the gate metal pattern and the gate insulating layer. The method of claim 3, wherein And the organic material layer is formed on the entire surface of the TFT array. The method of claim 2, The lower plate, A gate metal pattern including a gate line, a gate electrode of the TFT, and a gate pad lower electrode connected to the gate line; A data metal pattern including a data line crossing the gate line, a source and drain electrode of the TFT, and a data pad lower electrode connected to the data line; And An active pattern including a gate insulating layer and a semiconductor formed between the gate metal pattern and the data metal pattern; And the elastic layer comprises an organic material layer and an inorganic material layer formed between the gate metal pattern and the gate insulating layer. The method of claim 5, The organic material layer is formed on the front of the TFT array, And the inorganic layer is formed in a pattern partially removed in the TFT array.

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