KR20100033639A - Method of fabricating semiconductror device and flash memory device - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor device and a flash memory device using the same are provided to reduce over erase of a flash memory device by forming a structure combining a memory cell and a select transistor. CONSTITUTION: A nitride layer(202) is formed on a semiconductor substrate(100). A sacrifice vertical structure(SVS) is formed on the nitride film. A sacrificial spacer is formed on a side of the sacrifice vertical structure. The nitride film is first patterned using the sacrifice vertical structure and the sacrificial spacer as a mask. The sacrificial spacer is removed. Gate electrodes(310, 320) are formed on the side of the sacrifice vertical structure.

Description

TECHNICAL MANUFACTURING METHOD AND FLASH MEMORY DEVICE {METHOD OF FABRICATING SEMICONDUCTROR DEVICE AND FLASH MEMORY DEVICE}

The embodiment relates to a method of manufacturing a semiconductor device and a method of manufacturing a flash memory device.

As information processing technology develops, highly integrated flash memory devices have been developed. In particular, flash memory devices having a SONOS structure have been developed.

Such flash memory devices may include a select transistor to prevent over erase. However, the flash memory device further includes a select transistor, so that high integration is difficult.

The embodiment provides a method of manufacturing a semiconductor device that reduces variation in semiconductor devices and a flash memory device capable of high integration.

In another embodiment, a method of manufacturing a semiconductor device includes forming a nitride film on a semiconductor substrate; Forming a sacrificial vertical structure on the nitride film; Forming a sacrificial spacer on the side of the sacrificial vertical structure; First patterning the nitride layer using the sacrificial vertical structure and the sacrificial spacer as a mask; Removing the sacrificial spacers and forming a gate electrode on the side of the sacrificial vertical structure; And removing the sacrificial vertical structure, and second patterning the nitride layer using the gate electrode as a mask.

In addition, a flash memory device according to another embodiment includes a trap unit disposed on a semiconductor substrate and trapping charge; A channel region including a first channel region corresponding to the trap unit and a second channel region adjacent to the first channel region; Source and drain regions facing each other with the channel region therebetween; And a gate electrode disposed on the first channel region and the second channel region.

In the method of manufacturing a semiconductor device according to the embodiment, the nitride film is patterned using a sacrificial vertical structure and a sacrificial spacer. Since the sacrificial spacers are formed by the etch back process, the sacrificial spacers may be formed to be the same size in symmetry with each other.

Therefore, since the nitride film is patterned by using the sacrificial spacer as a mask, the nitride film can be divided and patterned into two parts having the same width.

Therefore, two semiconductor devices may be formed, each including a patterned nitride film, in which a deviation between the two semiconductor devices is reduced.

Therefore, the manufacturing method of the semiconductor device according to the embodiment reduces the deviation between the devices.

In addition, the flash memory device according to another embodiment includes a first channel region and a second channel region, and the gate electrode is disposed on the first channel region and the second channel region.

Therefore, the flash memory device according to another embodiment has a structure in which a memory cell and a select transistor are combined. Accordingly, the flash memory device according to another embodiment may reduce over erasure.

In addition, the flash memory device according to another embodiment may drive the select transistor and the memory cell using one gate electrode, and have an improved degree of integration.

In the description of the embodiment, each panel, part, chassis, sheet, plate, or substrate is formed on or under the "on" of each panel, part, chassis, sheet, plate, or substrate, and the like. When described as being "in" and "under" includes both those that are formed "directly" or "indirectly" through other components. In addition, the criteria for the top or bottom of each component will be described based on the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 to 7 are cross-sectional views illustrating processes of a method of manufacturing a flash memory device having a SONOS structure according to an embodiment.

Referring to FIG. 1, an isolation layer 110 is formed on a semiconductor substrate 100, and an active region is defined inside the isolation layer 110. Thereafter, a low concentration of n-type impurities is implanted into the active region to form an n-type well 120.

Referring to FIG. 2, after the n-type well 120 is formed, a tunnel oxide film 201, a nitride film 202, and a buffer layer 203 are formed on the semiconductor substrate 100.

The tunnel oxide film 201 is formed to a thickness of about 50 to 80 kPa by a thermal oxidation process, and the nitride film 202 is formed to a thickness of about 70 to 100 kPa by a CVD (chemical vapor deposition) process. Examples of the material used for the nitride film 202 include silicon nitride (SiNx) and the like.

The buffer layer 203 is formed on the nitride film 202, and examples of the material used as the buffer layer 203 include silicon oxide (SiOx).

In addition, a high K material such as aluminum oxide may be deposited between the tunnel oxide film 201 and the nitride film 202.

As a result, an ONO film 200a having an oxide film-nitride film-oxide film structure is formed on the semiconductor substrate 100. In this case, the ONO film 200a may be patterned by a mask process.

Thereafter, a sacrificial vertical structure SVS is formed on the buffer layer 203. Examples of the material used as the sacrificial vertical structure SVS include nitride or oxide.

The sacrificial vertical structure SVS may be formed to have a height of about 3000 to 4000 mm.

Referring to FIG. 3, after the sacrificial vertical structure SVS is formed, a silicon nitride layer is formed on the semiconductor substrate 100, and the silicon nitride layer is etched by an anisotropic etching process such as an etch back process.

Accordingly, first and second sacrificial spacers SS1 and SS2 are formed on side surfaces of the sacrificial vertical structure SVS. The first and second sacrificial spacers SS1 and SS2 are symmetrical with each other with the sacrificial vertical structure SVS interposed therebetween.

Since the first and second sacrificial spacers SS1 and SS2 are formed by an anisotropic etching process, the first and second sacrificial spacers SS1 and SS2 have substantially the same size. In more detail, bottom surfaces of the first and second sacrificial spacers SS1 and SS2 have the same width.

Thereafter, the ONO layer 200a is patterned using the first and second sacrificial spacers SS1 and SS2 and the sacrificial vertical structure SVS as a mask. That is, portions of the ONO layer 200a in which the first and second sacrificial spacers SS1 and SS2 and the sacrificial vertical structure SVS are not disposed are etched.

Referring to FIG. 4, the first and second sacrificial spacers SS1 and SS2 are removed. In this case, portions of the buffer layer 203 disposed under the first and second sacrificial spacers SS1 and SS2 are removed together.

Thereafter, an insulating film 204 is formed on the semiconductor substrate 100 by a CVD process. Examples of the material used for the insulating film 204 include silicon oxide and the like. The insulating layer 204 is also formed on the side and top of the sacrificial vertical structure SVS.

Referring to FIG. 5, a polysilicon layer is formed on the insulating film 204. The polysilicon layer is etched by an anisotropic etching process such as an etch back process, and first and second gate electrodes 310 and 320 are formed on side surfaces of the sacrificial vertical structure SVS.

The first and second gate electrodes 310 and 320 are disposed on the nitride film 202 and are disposed on the side surface of the nitride film 202. The first and second gate electrodes 310 and 320 are symmetrical to each other.

In addition, the first and second gate electrodes 310 and 320 have substantially the same size because they are formed by an anisotropic etching process.

Referring to FIG. 6, after the first and second gate electrodes 310 and 320 are formed, the sacrificial vertical structure SVS is removed.

Thereafter, the buffer layer 203, the nitride layer 202, and the tunnel oxide layer 201 are patterned using the first and second gate electrodes 310 and 320 as masks.

Accordingly, the first trap part 210 including the first tunnel oxide film 201a, the first charge trap layer 202a, and the first insulating film 204a is formed on the semiconductor substrate 100. At the same time, a second trap portion 220 including a second tunnel oxide film 201b, a second charge trap layer 202b, and a second insulating film 204b is formed.

Thereafter, low concentrations of p-type impurities are implanted into the sides of the first and second gate electrodes 310 and 320 to form LDD regions 410 and 420, and the first and second gate electrodes 310 are formed. , A high concentration of p-type impurities are implanted in the region between the first and second regions 320 to form the source region 510.

Referring to FIG. 7, after the source region 510 is formed, spacers 331 and 332 are formed on side surfaces of the first and second gate electrodes 310 and 320. In this case, the spacers 331 and 332 are disposed on side surfaces of the first and second charge trap layers 202a and 202b to insulate side surfaces of the first and second charge trap layers 202a and 202b. .

Thereafter, high concentrations of p-type impurities are implanted into the sides of the first and second gate electrodes 310 and 320 to form drain regions 521 and 522.

Afterwards, silicide layers 610, 620, 630, 640, and 650 are formed on the first and second gate electrodes 310 and 320, the source region 510, and the drain regions 521 and 522. Is formed.

As a result, a flash memory device including first and second memory cells FL1 and FL2 symmetric with each other and having a SONOS structure is formed.

The first memory cell FL1 includes the first gate electrode 310 and the first trap part 210.

The first trap part 210 includes a first tunnel oxide film 201a, the first charge trap layer 202a, and a first insulating film 204a. The first tunnel oxide layer 201a is interposed between the first charge trap layer 202a and the semiconductor substrate 100, and the first insulating layer 204a is formed of the first gate electrode 310 and the first gate. It is interposed between the charge trap layers 202a. That is, the first trap unit 210 has an ONO structure.

The second memory cell FL2 includes the second gate electrode 320 and the second trap part 220.

The second trap part 220 includes a second tunnel oxide film 201b, the second charge trap layer 202b, and a second insulating film 204b. The second tunnel oxide layer 201b is interposed between the second charge trap layer 202b and the semiconductor substrate 100, and the second insulating layer 204b includes the second gate electrode 320 and the second layer. It is interposed between the charge trap layers 202b. Similarly, the second trap part 220 has an ONO structure.

The first and second charge trap layers 202a and 202b may trap and retain charge. In more detail, the first and second charge trap layers 202a and 202b may trap and retain hot electrons or hot holes.

The first gate electrode 310 and the second gate electrode 320 have substantially the same size.

In addition, the width W1 of the first charge trap layer 202a is substantially the same as the width of the first spacer, and similarly, the width W2 of the second charge trap layer 202b is the second spacer. Is substantially equal to the width of.

Therefore, the width of the first charge trap layer 202a is substantially the same as the width of the second charge trap layer 202b.

Since the sizes of the first and second gate electrodes 310 and 320 are the same and the sizes of the first and second charge trap layers 202b are the same, the first memory cell FL1 and The second memory cell FL2 has substantially the same characteristics.

Therefore, the flash memory device of the SONOS structure according to the embodiment can reduce the deviation between the memory cells.

In particular, the flash memory device of the SONOS structure according to the embodiment can reduce the variation between the memory cells due to the variation in the width of the charge trap layers.

In addition, the first memory cell FL1 has a channel region CH that is divided into a first channel region CH1 and a second channel region CH2. The channel region CH is formed between the source region 510 and the drain region 521.

The first channel region CH1 corresponds to the first trap unit 210, and the second channel region CH2 is adjacent to the first channel region CH1.

In more detail, the first trap unit 210 is disposed on the first channel region CH1, and the first trap unit 210 is not disposed on the second channel region CH2. That is, the first trap part 210 is disposed only on the first channel region CH1.

That is, the first channel region CH1 and the second channel region CH2 are divided by the first trap unit 210.

The first gate electrode 310 is disposed on the first channel region CH1 and the second channel region CH2. That is, the first gate electrode 310 is disposed on the first channel region CH1, in more detail, on the first trap unit 210, and on the second channel region CH2.

In addition, the first gate electrode 310 covers the side surface of the first trap part 210. That is, the side surface of the first charge trap layer 202a is covered.

The second memory cell FL2 also has the same structure as the first memory cell FL1.

Since the first memory cell FL1 includes the first channel region CH1 and the second channel region CH2, one transistor and one memory cell are combined.

Therefore, the flash memory device according to the embodiment may implement an improved degree of integration.

That is, the first channel region CH1 and the second channel region CH2 may be controlled by the first gate electrode 310.

Accordingly, since the first memory cell FL1 and the second memory cell FL2 have a select transistor function, the flash memory device according to the embodiment may reduce overerase.

Although the above has been described with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above unless they depart from the essential characteristics of the present embodiments. It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 to 7 are cross-sectional views illustrating processes of a method of manufacturing a flash memory device having a SONOS structure according to an embodiment.

Claims (10)

Forming a nitride film on the semiconductor substrate; Forming a sacrificial vertical structure on the nitride film; Forming a sacrificial spacer on the side of the sacrificial vertical structure; First patterning the nitride layer using the sacrificial vertical structure and the sacrificial spacer as a mask; Removing the sacrificial spacers and forming a gate electrode on the side of the sacrificial vertical structure; And Removing the sacrificial vertical structure and second patterning the nitride layer using the gate electrode as a mask. The method of claim 1, wherein in the forming of the gate electrode, And the gate electrode covers the first patterned nitride film. The method of claim 1, wherein forming the sacrificial spacers Forming a sacrificial spacer material layer covering the sacrificial vertical structure; And And anisotropically etching the sacrificial spacer material layer. The method of claim 1, wherein the forming of the nitride film, Forming a first oxide film on the semiconductor substrate; Forming the nitride film on the first oxide film; And Forming a second oxide film on the nitride film. The method of claim 4, wherein in the step of removing the sacrificial spacer, And a portion of the first oxide film and the second oxide film are removed. The method of claim 1, further comprising forming an insulating film on the semiconductor substrate and the nitride film after removing the sacrificial spacers. A trap unit disposed on the semiconductor substrate and configured to trap electric charges; A channel region including a first channel region corresponding to the trap unit and a second channel region adjacent to the first channel region; A source region and a drain region facing each other with the channel region therebetween; And And a gate electrode disposed on the first channel region and the second channel region. The flash memory device of claim 7, wherein the trap part has an ONO structure. The flash memory device of claim 7, wherein the trap part is disposed only on the first channel region. The flash memory device of claim 7, wherein the gate electrode covers a side surface of the trap part.

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