KR20100033333A - Semiconductor device and forming method of the same - Google Patents

Abstract

PURPOSE: An N type capping film and a semiconductor device and a method of formation thereof are provided to reduce flat band voltage. The threshold voltage of the metal gate electrode can be low made. CONSTITUTION: A first well domain(106) is arranged in a semiconductor substrate(100). A first gate electrode(140) is arranged on the first well domain. A first N type capping pattern(110), and a first P-type the capping pattern(130) and a first gate insulation pattern(120) are allowed in between the first well domain and the first gate electrode. The first N type capping pattern comprises at least one of laO, gdO, dyO, srO, baO and ErO. The first P-type capping pattern comprises an aluminum oxide film and an aluminum metal oxide layer.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device. More specifically, it relates to a MOS semiconductor device.

Gate structures of MOS transistors with a minimum line width of 45nm or less are being actively researched. The gate structure may be a stacked structure of a high dielectric film / metal gate electrode or a stacked structure of a high dielectric film / polysilicon gate electrode. The stacked structure of the high dielectric film / metal gate electrode may lower the threshold voltage (Vth) than the stacked structure of the high dielectric film / polysilicon gate electrode. However, for high performance transistor operation, the threshold voltage of the stacked structure of the high dielectric film and the metal gate electrode should be lowered.

One technical problem to be solved by the present invention is to provide a semiconductor device capable of adjusting the threshold voltage using a plurality of keping patterns.

One technical problem to be solved by the present invention is to provide a method of forming a semiconductor device capable of adjusting the threshold voltage using a plurality of keping patterns.

In an embodiment, a semiconductor device may include a semiconductor substrate, a first well region disposed on the semiconductor substrate, a first gate electrode disposed on the first well region, and the first well region and the first gate. And a first N-type keping pattern, a first P-type keping pattern, and a first gate insulation pattern interposed between the electrodes.

In one embodiment of the present invention, the first N-type keping pattern may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO.

In one embodiment of the present invention, the first P-type kepping pattern may include at least one of an aluminum oxide film and an aluminum metal oxide film.

In one embodiment of the present invention, the first gate insulating pattern is a silicon oxide film, silicon oxynitride film, hafnium oxide film, hafnium silicon oxide film, zirconium oxide film, zirconium silicon oxide film, hafnium oxynitride film, hafnium silicon oxynitride film, zirconium oxynitride film, It may include at least one of a zirconium silicon oxynitride film and a titanium oxide film.

In one embodiment of the present invention, the first gate electrode may include at least one of TaC, TaN, TaCN, and TiN.

In example embodiments, the first gate insulation pattern may include a first upper gate insulation pattern and a first lower gate insulation pattern.

In an exemplary embodiment, a second well region disposed on the semiconductor substrate, a second gate electrode disposed on the second well region, and interposed between the second well region and the second gate electrode. And a second P-type kepping pattern and a second gate insulation pattern, wherein the first gate insulation pattern and the second gate insulation pattern are made of the same material, and the first gate electrode and the second gate electrode are made of the same material. It may be a substance.

In example embodiments, the first well region may be a P-type impurity region, and the second well region may be an N-type impurity region.

The semiconductor device may further include semiconductor fins protruding from the semiconductor substrate, wherein the first well region may be disposed on the semiconductor fin, and the first gate insulation pattern may cross the first well region. have.

A method of forming a semiconductor device according to an embodiment of the present invention includes forming a device isolation film by forming a trench in a semiconductor substrate, forming a first well region on the semiconductor substrate, and forming the semiconductor substrate on which the device isolation film is formed. Forming a first N-type capping layer on the first N-type capping layer, forming a first gate insulating layer on the first gate insulating layer, and forming a first P-type capping layer on the first gate insulating layer Forming a first gate conductive layer on the P-type keping pattern, and forming a first gate electrode, a first P-type keping pattern, a first gate insulation pattern, and a first N-type keping pattern The 1 N-type keping pattern may reduce the flat band voltage, and the first P-type keping pattern may increase the flat band voltage.

A method of forming a semiconductor device according to an embodiment of the present invention includes forming a device isolation film by forming a trench in a semiconductor substrate, forming a first well region and a second well region on the semiconductor substrate, and forming the first well region and the first well region. Forming a first gate structure on the well region, and a second gate structure on the second well region, wherein the first gate structure comprises a first N-type keping pattern, a first gate insulating pattern, a first P; And a first gate electrode, wherein the second gate structure includes a second gate insulating pattern, a second P-type kepping pattern, and a second gate electrode, wherein the first P-type keping pattern and the The second P-type kepping pattern may be made of the same material, and the first gate electrode and the second gate electrode may be formed of the same material.

In an exemplary embodiment, the forming of the first gate structure on the first well region and the second gate structure on the second well region may include forming an N-type capping layer on the first well region. Forming a gate insulating film on the first well region and the second well region, forming a P-type capping film on the entire gate insulating film, forming a gate conductive film on the P-type capping film, And patterning a material stacked on the first well region and the second well region to form a first gate structure and a second gate structure.

In example embodiments, forming a first gate structure on the first well region and a second gate structure on the second well region may be performed on the first well region and the second well region. Forming a lower gate insulating film, forming an N-type capping film on the lower gate of the first well region, forming an upper gate insulating film on the first well region and the second well region, and forming the upper gate insulating film. Forming a P-type capping layer on the entire gate insulating film, forming a gate conductive layer on the P-type capping layer, and patterning a material stacked in the first well region and the second well region to form a first gate structure And forming a second gate structure.

In an exemplary embodiment, the forming of the first gate structure on the first well region and the second gate structure on the second well region may include forming an N-type capping layer on the first well region. Forming a lower gate insulating film on the second well region, nitriding the N-type capping film and the lower gate insulating film, and forming an upper gate insulating film on the entire surface of the N-type capping film and the lower gate insulating film Forming a P-type capping layer on the entire upper gate insulating layer, forming a gate conductive layer on the P-type capping layer, and patterning a material stacked on the first well region and the second well region Thereby forming a first gate structure and a second gate structure.

In an exemplary embodiment, the forming of the first gate structure on the first well region and the second gate structure on the second well region may include forming an N-type capping layer on the first well region. Forming a gate insulating film on the N-type keping film and the second well region, forming a P-type keping film on the entire surface of the N-type keping film and the gate insulating film, and forming a gate on the P-type keping film The method may include forming a conductive layer and patterning a material stacked on the first well region and the second well region to form a first gate structure and a second gate structure.

In one embodiment of the present invention, the first N-type keping pattern may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO.

In one embodiment of the present invention, the first P-type kepping pattern may include at least one of an aluminum oxide film and an aluminum metal oxide film.

In an embodiment, the first gate insulation pattern and the second gate insulation pattern may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, and a hafnium silicon film. It may include at least one of an oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film.

In the semiconductor device according to the exemplary embodiment, the threshold voltage may be adjusted by stacking the first N-type keping pattern and the first P-type keping pattern. In addition, the process of forming the semiconductor element is simple.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

FIG. 1 is a diagram illustrating a flat band voltage according to a structure (NMOS capacitor) of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a gate structure may be disposed on a semiconductor substrate of the NMOS capacitor. The gate structure may include a gate insulating layer and a gate electrode. The gate electrode may be TaC, and the gate insulating layer may have a HfSiON, HfSiON / LaO, HfSiON / AlO, and HfSiON / LaO / AlO stack structure. According to the structure of the gate insulating film, the flat band voltage and the effective oxide thickness (EOT) of the capacitor were measured. The flat band voltage of the HiSiON structure (control structure) was -0.64 V, the flat band voltage of the HfSiON / LaO structure (LaO capped) was -1.184 V, and the flat band voltage of the HfSiON / AlO structure (AlO capped) was -0.35 V The flat band voltage of the HfSiON / LaO / AlO structure (LaO / AlO capped) was -0.91 V. In this case, the thicknesses of the HfSiON were all the same, and the physical thicknesses of LaO and AlO were 1 nm. However, the EOT of HfSiON / LaO / AlO structure hardly increased as compared to the EOT of HfSiON / AlO structure. Therefore, when the LaO-based material and AlO-based material are properly combined, a desired threshold voltage can be obtained. The LaO-based material may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The LaO based material may be an N-type kepping material. In addition, the AlO-based material may include at least one of an aluminum oxide film and an aluminum metal oxide film. The ALO based material may be a P-type kepping material.

The threshold voltage of the semiconductor device may depend on the thickness of the gate insulating layer and the ion implantation concentration of the semiconductor substrate. According to the embodiment of the present invention, the threshold voltage of the semiconductor device can be changed with little change in the EOT by the combination of the gate insulating film, the N-type kepping film, and the P-type kepping film. The N-type capping layer may be a material that reduces the flat band voltage, and the P-type capping layer may be a material that increases the flat band voltage. The N-type capping layer may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The p-type capping film may include at least one of an aluminum oxide film and an aluminum metal oxide film.

2A and 2B are cross-sectional views illustrating semiconductor devices in accordance with example embodiments of the inventive concept.

Referring to FIG. 2A, the semiconductor device may include a semiconductor substrate 100, a first well region 106 disposed on the semiconductor substrate 100, and a first gate electrode disposed on the first well region 106. 140, and a first N-type kepping pattern 110, a first P-type kepping pattern 130, and a first gate insulation interposed between the first well region 106 and the first gate electrode 140. Pattern 120. The first N-type keping pattern 110 may reduce the flat band voltage, and the first P-type kepping pattern 130 may increase the flat band voltage. The semiconductor device may operate as a capacitor or a transistor. The first N-type keping pattern 110, the first gate insulation pattern 120, and the first P-type keping pattern 130 may be sequentially stacked.

The semiconductor substrate 100 may be a silicon substrate or an SOI substrate. The first well region 106 may be a P well or an N well. The first gate electrode 140 may include at least one of TaC, TaN, TaCN, and TiN. The first gate electrode 140 may have a multilayer structure. The first gate electrode 140 may include at least one of a metal film, a metal silicide, a metal oxide film, a metal nitride film, and a doped polysilicon.

The first N-type keping pattern 110 may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The first N-type keping pattern 110 may reduce the flat band voltage of the semiconductor device. The thickness of the first N-type keping pattern 110 may be 0.1 nm to 10 nm.

The first P-type kepping pattern 130 may include at least one of an aluminum oxide layer and an aluminum metal oxide layer. The first P-type kepping pattern 130 may increase the flat band voltage of the semiconductor device. The thickness of the first P-type kepping pattern 130 may be 0.1 nm to 10 nm. The thickness of the first N-type kepping pattern 110 and the first P-type keping pattern 130 may be smaller than the thickness of the gate insulating pattern 120.

The first gate insulating pattern 120 may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, And a titanium oxide film. The first gate insulating pattern 120 may be a high dielectric material having a higher dielectric constant than that of the silicon oxide layer.

According to a modified embodiment of the present invention, the first P-type kepping pattern 110 and the first N-type keping pattern 130 may be alternately stacked.

According to a modified embodiment of the present invention, the first gate insulating pattern 120, the first N-type keping pattern 110, and the first P-type keping pattern 130 may be sequentially stacked.

According to the modified embodiment of the present invention, the order in which the first gate insulation pattern 120, the first N-type keping pattern 110, and the first P-type keping pattern 130 are stacked may be changed. have.

According to a modified embodiment of the present invention, the first gate insulating pattern 120 may include a first lower gate insulating pattern and a first upper gate insulating pattern. The first lower gate insulating pattern and the upper gate insulating pattern may be different materials. In addition, the first lower gate insulating pattern and the upper gate insulating pattern may not be sequentially stacked on each other.

3 is a perspective view illustrating a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 3, the semiconductor device may include a semiconductor substrate 100, a first well region 106 disposed on the semiconductor substrate 100, and a first gate electrode disposed on the first well region 106. 140, and a first N-type kepping pattern 110, a first P-type kepping pattern 130, and a first gate insulation interposed between the first well region 106 and the first gate electrode 140. Pattern 120 is included. The first N-type keping pattern 110 may reduce the flat band voltage, and the first P-type kepping pattern 130 may increase the flat band voltage. The semiconductor device may operate as a transistor. The first gate insulating pattern 120, the first N-type keping pattern 110, and the first P-type keping pattern 130 may be sequentially stacked.

The trench 103 may be formed in the semiconductor substrate to define the active region 102. The trench 103 may be filled by the device isolation layer 104. The device isolation layer 104 may be formed by a shallow trench isolation process. The upper surface of the active region 102 and the upper surface of the device isolation layer 104 may be substantially the same height.

An ion implantation process may be performed on the semiconductor substrate 100 on which the device isolation layer 104 is formed. The ion implantation process may form the first well region 106. The lower surface of the first well region 106 may be lower than the lower surface of the device isolation layer 104. The first well region 106 may be a P well or an N well. The gate structure 200 may be disposed on the first well region 106. The gate structure 200 may include a first gate insulating pattern 120, a first N-type keping pattern 110, a first P-type keping pattern 120, and a first gate electrode 140 that are sequentially stacked. Can be. A spacer insulating layer 190 may be disposed on sidewalls of the gate structure 200. Source / drain 107 may be disposed in the active region 102 at both sides of the gate structure 200.

4 to 6 are perspective views illustrating semiconductor devices according to exemplary embodiments of the present invention.

Referring to FIG. 4, the semiconductor device may include a semiconductor substrate 100, a first well region 106n disposed on the semiconductor substrate 100, and a first gate structure disposed on the first well region 106n. 200n), a second well region 106p disposed on the semiconductor substrate 100, and a second gate structure 200p disposed on the second well region 106p. The first gate structure 200n may include a first gate electrode 140n, a first N-type keping pattern 110n interposed between the first well region 106n and the first gate electrode 140n, and a first gate structure 200n. It may include a P-type kepping pattern 130n and a first gate insulating pattern 120n. The first gate insulating pattern 120n may include a first lower gate insulating pattern 122n and a first upper gate insulating pattern 124n. The first N-type keping pattern 110n may reduce the flat band voltage, and the first P-type kepping pattern 130n may increase the flat band voltage.

The second gate structure 200p is interposed between the second gate electrode 140p disposed on the second well region 106p, the second well region 106p, and the second gate electrode 140p. The second P-type kepping pattern 130p and the second gate insulating pattern 120p may be included. The first gate electrode 140n and the second gate electrode 140p may be the same material. The second gate insulating pattern 120p may include a second lower gate insulating pattern 122p and a second upper gate insulating pattern 124p.

An isolation layer 104 is disposed on the semiconductor substrate 100. The device isolation layer 104 may be formed by a shallow trench device isolation process. An active region is defined by the device isolation film 104. The device isolation layer may electrically separate the active regions from each other. A first gate structure 200n and a second gate structure 200p may be disposed on the semiconductor substrate. The first well region 106n may be doped with a P-type impurity. The second well region 106p may be doped with N-type impurities. An NMOS may be disposed in the first well region 106n, and a PMOS may be disposed in the second well region 106p.

The NMOS may include the first well region 106n and the first gate structure 200n. The PMOS may include the second well region 106p and the second gate structure 106p.

The first N-type keping pattern 110n may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The first P-type kepping pattern 130n and the second P-type keping pattern 130p may include at least one of an aluminum oxide layer and an aluminum metal oxide layer. The first P-type kepping pattern 130n and the second P-type keping pattern 130p may be made of the same material.

The first lower gate insulating pattern 122n, the first upper gate insulating pattern 124n, the second lower gate insulating pattern 122p, and the second upper gate insulating pattern 124p may be formed of a silicon oxide layer and a silicon oxide layer. And at least one of a nitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. The first lower gate insulating pattern 122n and the second lower gate insulating pattern 122p may be made of the same material. The first upper gate insulating pattern 124n and the second upper gate insulating pattern 124p may be the same material.

The first gate electrode 140n and the second gate electrode 140p may include at least one of TaC, TaN, TaCN, and TiN. The first and second gate electrodes 140n and 140p may have a multilayer structure. The first and second gate electrodes 140n and 140p may include at least one of a metal film, a metal silicide, a metal oxide film, a metal nitride film, and a doped polysilicon. The first gate electrode 140n and the second gate electrode 140p may be the same material.

According to a modified embodiment of the present invention, the first lower gate insulating pattern 122n and the second lower gate insulating pattern 122p may be removed.

The gate structure of the MOS transistor of 45 nm or less can be a high dielectric film / metal gate electrode. The gate structure of the high dielectric film / metal gate electrode can lower the threshold voltage compared to the high dielectric / polysilicon structure. However, in order to be practical, the threshold voltage of the gate structure of the high dielectric film / metal gate electrode must be lowered.

In the case of CMOS using dual metal gates, it is difficult to obtain an optimal metal gate material for NMOS and PMOS. In addition, the dual metal gate process may cause damage to the high dielectric film. In the case of a CMOS using a single metal gate and a single capping layer, the keping layer may be applied only to the PMOS. Therefore, an optimal NMOS metal gate material must be ensured and the high dielectric film can be damaged during the PMOS formation process.

In the case of a CMOS using one metal gate and two keping layers, a process complexity of depositing and removing different keping layers on NMOS and PMOS may be required. In addition, high-k dielectric films may be damaged in NMOS and PMOS processes. Accordingly, the semiconductor device according to an embodiment of the present invention overcomes the above-mentioned problems and provides a method of using an N-type capping film having a threshold voltage reduction effect superior to that of a P-type capping film.

Referring to FIG. 5, the semiconductor device may include a semiconductor substrate 100, a first well region 106n disposed on the semiconductor substrate 100, and a first gate structure disposed on the first well region 106n. 200n), a second well region 106p disposed on the semiconductor substrate 100, and a second gate structure 200p disposed on the first well region 106p.

The first gate structure 200n includes a first N-type keping pattern 110n, a first gate insulation pattern 120n, and a first P-type keping pattern 130n sequentially stacked on the first well region 106n. , And the first gate electrode 140n.

The second gate structure 200p may include a second lower gate insulating pattern 122p, a second upper gate insulating pattern 124p, and a second P-type keping pattern 130p sequentially stacked on the second well region 106p. ), And the second gate electrode 140p. The second gate insulating pattern 120p may include the second lower gate insulating pattern 122p and the second upper gate insulating pattern 124p.

The first gate electrode 140n and the second gate electrode 140p may be the same material. The first gate insulating pattern 120n and the second upper gate insulating pattern 124p may be the same material. The first P-type kepping pattern 130n and the second P-type keping pattern 130p may be made of the same material.

The first N-type keping pattern 110n may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The first P-type kepping pattern 130n and the second P-type keping pattern 130p may include at least one of an aluminum oxide layer and an aluminum metal oxide layer.

The first gate insulating pattern 120n, the second lower gate insulating pattern 122p, and the second upper gate insulating pattern 124p may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, And a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film.

Referring to FIG. 6, the semiconductor device may include a semiconductor substrate 100, a first well region 106n disposed on the semiconductor substrate 100, and a first gate structure disposed on the first well region 106n. 200n), a second well region 106p disposed on the semiconductor substrate 100, and a second gate structure 200p disposed on the second well region 106p.

The first gate structure 200n includes a first N-type keping pattern 110n, a first gate insulation pattern 120n, and a first P-type keping pattern 130n sequentially stacked on the first well region 106n. , And the first gate electrode 140n.

The second gate structure 200p may include a second gate insulating pattern 120p, a second P-type kepping pattern 130p, and a second gate electrode 140p that are sequentially stacked on the second well region 106p. It may include. The first gate electrode 140n and the second gate electrode 140p may be the same material. The first gate insulation pattern 120n and the second gate insulation pattern 120p may be the same material. The thickness of the first gate insulating pattern 120n and the thickness of the second gate insulating pattern 120p may be different from each other. The first P-type kepping pattern 130n and the second P-type keping pattern 130p may be made of the same material.

7A to 7E are perspective views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 7A, the trench 103 is formed on the semiconductor substrate 100 to define the active region 102. The device isolation layer 104 may fill the trench 103. The upper surface of the device isolation layer 104 may be substantially the same height as the upper surface of the active region 102. The isolation layer 104 may be performed by a shallow trench isolation process. After formation of the device isolation layer 104, a first well region 106n and a second well region 106p may be formed in the semiconductor substrate 100. The first well region 106n and the second well region 106p may be performed by an ion implantation process. The first well region 106n may be a P well, and the second well region 106p may be an N well. According to a modified embodiment of the present invention, the formation of the first well region 106n and the second well region 106p may be performed before the device isolation layer 104 is formed.

Referring to FIG. 7B, a lower gate insulating layer 122 may be formed on the entire surface of the semiconductor substrate 100. The lower gate insulating layer 122 may be at least one of a silicon oxide film, a silicon oxynitride film, and a high dielectric film. The lower gate insulating layer 122 may be formed by chemical vapor deposition, thermal oxidation, or atomic layer deposition. In the case of a thermal oxide layer, the lower gate insulating layer 122 may not grow on the device isolation layer 104.

An N-type capping layer 112 may be formed on the lower gate insulating layer 122. Subsequently, the N-type capping layer 112 on the second well region 106p may be selectively etched. The selective etching may be wet etching or dry etching. The N-type capping layer 112 may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The N-type capping layer 112 may reduce the flat band voltage of the semiconductor device.

According to a modified embodiment of the present invention, the N-type capping layer 112 may be formed only in the first well region 106n without forming the lower gate insulating layer 122.

Referring to FIG. 7C, an upper gate insulating layer 124 may be formed on the entire surface of the semiconductor substrate 100. The upper gate insulating layer 124 may be formed by chemical vapor deposition or atomic layer deposition. The upper gate insulating layer 124 may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. It may include at least one of.

Referring to FIG. 7D, a P-type capping layer 132 may be formed on the entire surface of the semiconductor substrate 100. The P-type capping layer 132 may include at least one of an aluminum oxide layer and an aluminum metal oxide layer. The P-type capping layer 132 may be formed by chemical vapor deposition or atomic layer deposition. The P-type capping layer 132 may increase the flat band voltage of the semiconductor device.

Referring to FIG. 7E, a gate conductive layer 142 may be formed on the entire surface of the semiconductor substrate 100. The gate conductive layer 142 may be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The gate conductive layer 142 may include at least one of TaC, TaN, TaCN, and TiN. The gate conductive layer 142 may have a multilayer structure. The gate conductive layer 142 may include at least one of a metal layer, a metal oxide layer, a metal nitride layer, and a doped polysilicon.

Referring to FIG. 4 again, the gate conductive layer 142 and the material stacked thereon may be patterned to form the first gate structure 200n and the second gate structure 200p.

The first gate structure 200n may include a first lower gate insulating pattern 122n, a first N-type keping pattern 110n, and a first upper gate insulating pattern 124n sequentially stacked on the first well region 106n. ), A first P-type kepping pattern 130n, and a first gate electrode 140n.

The second gate structure 200p may include a second lower gate insulating pattern 122p, a second upper gate insulating pattern 124p, and a second P-type keping pattern 130p sequentially stacked on the second well region 106p. ), And the second gate electrode 140p.

Spacer insulating layers may be disposed on side surfaces of the first gate structure 200n and the second gate structure 200p. Source / drain (not shown) may be formed in active regions on both sides of the first gate structure 200n. Source / drain may be formed in active regions on both sides of the second gate structure 200p. The conductivity type of the source / drain may be opposite to that of the first well region or the second well region.

8A to 8F are perspective views illustrating a method of forming a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 8A, a trench 103 is formed on the semiconductor substrate 100 to define an active region. The device isolation layer 104 may fill the trench 103. The upper surface of the device isolation layer 103 may be substantially the same height as the upper surface of the active region. The isolation layer 103 may be performed by a shallow trench isolation process. After formation of the device isolation layer 104, a first well region 106n and a second well region 106p may be formed in the semiconductor substrate 100. The first well region 106n and the second well region 106p may be performed by an ion implantation process. The first well region 106n may be a P well, and the second well region 106p may be an N well. According to a modified embodiment of the present invention, the first well region 106n and the second well region 106 may be formed before the device isolation layer 104 is formed. An N-type capping layer 112 may be formed on the entire surface of the semiconductor substrate 100. The N-type capping layer 112 may be patterned to etch the N-type capping layer 112 on the second well region 106p. The etching may be wet etching or dry etching.

Referring to FIG. 8B, the lower gate insulating layer 123 may be selectively formed on the second well region 106p. The lower gate insulating layer 123 may be a silicon oxide layer or a silicon oxynitride layer. The lower gate insulating layer 123 may be formed by a thermal oxidation process, a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method.

Referring to FIG. 8C, a nitride process may be performed on the entire surface of the semiconductor substrate on which the N-type capping layer 112 and the lower gate insulating layer 123 are formed. The nitriding process may be performed using a plasma containing nitrogen. The nitriding process may improve an interface property between the semiconductor substrate 100 and the N-type capping layer 112 and an interface property between the semiconductor substrate 100 and the lower gate insulating layer 123. . The nitriding process can suppress an increase in the effective oxide film thickness (EOT).

Referring to FIG. 8D, an upper gate insulating layer 125 may be formed on the N-type capping layer 112 and the lower gate insulating layer 123. The upper gate insulating layer 125 may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. It may include at least one of. The upper gate insulating layer 125 may be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

Referring to FIG. 8E, a P-type capping layer 132 may be formed on the entire surface of the semiconductor substrate 100. The P-type capping layer 132 may include at least one of an aluminum oxide layer and an aluminum metal oxide layer.

Referring to FIG. 8F, a gate conductive layer 142 may be formed on the entire surface of the semiconductor substrate 100. The gate conductive layer 142 may include at least one of TaC, TaN, TaCN, and TiN. The gate conductive layer 142 may have a multilayer structure. The gate conductive layer 142 may include at least one of a metal layer, a metal oxide layer, a metal nitride layer, and a doped polysilicon.

Referring to FIG. 5 again, the gate conductive layer 142 and the material stacked thereon may be patterned to form the first gate structure 200n and the second gate structure 200p.

The first gate structure 200n includes a first N-type keping pattern 110n, a first gate insulation pattern 120n, and a first P-type keping pattern 130n sequentially stacked on the first well region 106n. , And the first gate electrode 140n.

The second gate structure 200p may include a second lower gate insulating pattern 122p, a second upper gate insulating pattern 124p, and a second P-type keping pattern 130p sequentially stacked on the second well region 106p. ), And the second gate electrode 140p.

9A to 9D are perspective views illustrating a method of forming a semiconductor device in accordance with still another embodiment of the present invention.

Referring to FIG. 9A, a trench 103 is formed on the semiconductor substrate 100 to define an active region. The device isolation layer 104 may fill the trench 103. The upper surface of the device isolation layer 104 may be substantially the same height as the upper surface of the active region. The isolation layer 104 may be performed by a shallow trench isolation process. After formation of the device isolation layer 104, a first well region 106n and a second well region 106p may be formed in the semiconductor substrate 100. The first well region 106n and the second well region 106p may be performed by an ion implantation process. The first well region 106n may be a P well, and the second well region 106p may be an N well.

An N-type capping layer 112 may be formed on the entire surface of the semiconductor substrate 100. The N-type capping layer 112 may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The N-type capping layer 112 may reduce the flat band voltage of the semiconductor device. The N-type capping layer 112 may be patterned to etch the N-type capping layer 112 on the second well region 106p. The etching may be wet etching or dry etching.

Referring to FIG. 9B, a gate insulating layer 126 may be formed over the semiconductor substrate 100. The gate insulating layer 126 may be formed on the N-type capping layer pattern 112 and the second well region 106p. The gate insulating layer 126 may be formed by chemical vapor deposition or atomic layer deposition. The gate insulating film 126 is formed of a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. It may include at least one. The thickness of the gate insulating layer 126 on the N-type capping layer pattern 112 may be smaller than the thickness of the gate insulating layer 126 on the second well region 106p.

Referring to FIG. 9C, a P-type capping layer 132 may be formed on the gate insulating layer 126. The P-type capping film 132 may include at least one of an aluminum oxide film and an aluminum metal oxide film.

Referring to FIG. 9D, a gate conductive layer 142 may be formed on the P-type capping layer 132. The gate conductive layer 142 may include at least one of TaC, TaN, TaCN, and TiN. The gate conductive layer 142 may have a multilayer structure. The gate conductive layer 142 may include at least one of a metal layer, a metal oxide layer, a metal nitride layer, and a doped polysilicon.

6, the first gate structure 200n and the second gate structure 200p may be formed by patterning the gate conductive layer 142 and the material stacked under the gate conductive layer 142.

The first gate structure 200n includes a first N-type keping pattern 110n, a first gate insulation pattern 120n, and a first P-type keping pattern 130n sequentially stacked on the first well region 106n. , And the first gate electrode 140n.

The second gate structure 200p may include a second gate insulating pattern 120p, a second P-type kepping pattern 130p, and a second gate electrode 140p that are sequentially stacked on the second well region 106p. It may include.

10 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 10, a semiconductor fin 350 extending vertically from the semiconductor substrate 360 is disposed on the semiconductor substrate 300. A gate electrode 340 is disposed across the upper portion of the semiconductor fin 300. The gate electrode 340 may pass through both sidewalls and an upper surface of the semiconductor fin 350. A gate insulating pattern 320, an N-type kepping pattern 310, and a P-type keping pattern 330 may be disposed between the gate electrode 340 and the semiconductor fin 350. An upper region of the semiconductor fin 350 may be a first well region 306. The first well region 306 may be doped with N-type or P-type impurities. The semiconductor fin 350 on both sides of the gate electrode 340 may be a source / drain.

The gate insulating pattern 320 may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. It may include at least one of. The N-type keping pattern 310 may include at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The P-type keping pattern 330 may include at least one of an aluminum oxide layer and an aluminum metal oxide layer. The gate electrode 340 may include at least one of TaC, TaN, TaCN, and TiN.

11 is a block diagram illustrating an electronic system having a semiconductor device according to example embodiments.

Referring to FIG. 11, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 are coupled to each other through a bus 1350. The semiconductor device may be included in the memory device 1330. The bus 1350 corresponds to a path through which data travels. The controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1320 may include at least one selected from a keypad, a keyboard, a display device, and the like. The memory device 1330 is a device for storing data. The memory device 1330 may store data and / or instructions executed by the controller 1310. The memory device 1330 may include at least one selected from the semiconductor devices disclosed in the above embodiments. The electronic system 3100 may further include an interface 1340 for transmitting data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired / wireless transceiver.

The electronic system 1300 may be implemented as a mobile system, a personal computer, an industrial computer, or a system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card. , A digital music system or an information transmission / reception system. If the electronic system 1300 is a device capable of performing wireless communication, the electronic system 1300 may be used in a communication interface protocol such as a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000, etc. Can be.

Next, a memory card according to embodiments of the present invention will be described in detail with reference to the drawings.

12 is a block diagram illustrating a memory card having a semiconductor device according to example embodiments.

Referring to FIG. 12, the memory card 1400 includes a nonvolatile memory device 1410 and a memory controller 1420. The semiconductor device may be included in the nonvolatile memory device or the memory controller 1420. The nonvolatile memory device 1410 may store data or read stored data. The nonvolatile memory device 1410 includes at least one of the nonvolatile memory devices disclosed in the embodiments. The memory controller 1420 controls the nonvolatile memory device 1410 to read stored data or to store data in response to a read / write request of a host.

FIG. 1 is a diagram illustrating a flat band voltage according to a structure (NMOS capacitor) of a semiconductor device according to an embodiment of the present invention.

2A and 2B are cross-sectional views illustrating semiconductor devices in accordance with example embodiments of the inventive concept.

3 is a perspective view illustrating a semiconductor device in accordance with another embodiment of the present invention.

4 to 6 are perspective views illustrating a semiconductor device in accordance with embodiments of the present invention.

7A to 7E are perspective views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

8A to 8F are perspective views illustrating a method of forming a semiconductor device in accordance with another embodiment of the present invention.

9A to 9D are perspective views illustrating a method of forming a semiconductor device in accordance with still another embodiment of the present invention.

10 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention.

11 is a block diagram illustrating an electronic system having a semiconductor device according to example embodiments.

12 is a block diagram illustrating a memory card having a semiconductor device according to example embodiments.

Claims (18)

Semiconductor substrates; A first well region disposed in the semiconductor substrate; A first gate electrode on the first well region; And The semiconductor device includes a first N-type kepping pattern, a first P-type kepping pattern, and a first gate insulating pattern interposed between the first well region and the first gate electrode. According to claim 1, The first N-type keping pattern includes at least one of LaO, GdO, DyO, SrO, BaO, and ErO. According to claim 1, The first P-type keping pattern includes at least one of an aluminum oxide film and an aluminum metal oxide film. According to claim 1, The first gate insulating pattern may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, a zirconium silicon oxynitride film, and a titanium oxide film. A semiconductor device comprising at least one of. According to claim 1, The first gate electrode includes at least one of TaC, TaN, TaCN, and TiN. According to claim 1, The first gate insulating pattern may include a first upper gate insulating pattern and a first lower gate insulating pattern. According to claim 1, A second well region disposed on the semiconductor substrate; A second gate electrode disposed on the second well region; And And a second P-type kepping pattern and a second gate insulating pattern interposed between the second well region and the second gate electrode, wherein the first gate insulating pattern and the second gate insulating pattern are made of the same material. And the first gate electrode and the second gate electrode are made of the same material. The method of claim 7, wherein And the first well region is a P-type impurity region, and the second well region is an N-type impurity region. According to claim 1, Further comprising a semiconductor pin protruding from the semiconductor substrate, And the first well region is disposed in the semiconductor fin, and the first gate insulating pattern crosses the first well region. Forming a device isolation film by forming a trench in the semiconductor substrate; Forming a first well region on the semiconductor substrate; Forming a first N-type capping layer on the semiconductor substrate on which the device isolation layer is formed; Forming a first gate insulating film on the first N-type capping film; Forming a first P-type capping film on the first gate insulating film; Forming a first gate conductive layer on the first P-type keping pattern; And Forming a first gate electrode, a first P-type keping pattern, a first gate insulation pattern, and a first N-type keping pattern. Forming a device isolation film by forming a trench in the semiconductor substrate; Forming a first well region and a second well region in the semiconductor substrate; And Forming a first gate structure on the first well region, and a second gate structure on the second well region, The first gate structure includes a first N-type keping pattern, a first gate insulating pattern, a first P-type keping pattern, and a first gate electrode, and the second gate structure includes a second gate insulating pattern and a second P And a second gate electrode, wherein the first P-type kepping pattern and the second P-type keping pattern are made of the same material, and the first gate electrode and the second gate electrode are formed of the same material. A method of forming a semiconductor device, characterized in that. The method of claim 11, Forming a first gate structure on the first well region and a second gate structure on the second well region may include: Forming an N-type capping film on the first well region; Forming a gate insulating film on the first well region and the second well region; Forming a P-type capping film on the entire gate insulating film; Forming a gate conductive film on the P-type capping film; And And forming a first gate structure and a second gate structure by patterning the materials stacked in the first well region and the second well region. The method of claim 11, Forming a first gate structure on the first well region and a second gate structure on the second well region may include: Forming a lower gate insulating layer on the first well region and the second well region; Forming an N-type capping layer on the lower gate of the first well region; Forming an upper gate insulating layer on the first well region and the second well region; Forming a P-type capping film on the entire upper gate insulating film; Forming a gate conductive film on the P-type capping film; And And forming a first gate structure and a second gate structure by patterning the materials stacked in the first well region and the second well region. The method of claim 11, Forming a first gate structure on the first well region and a second gate structure on the second well region may include: Forming an N-type capping film on the first well region; Forming a lower gate insulating layer on the second well region; Nitriding the N-type capping layer and the lower gate insulating layer; Forming an upper gate insulating film on an entire surface of the N-type kepping layer and the lower gate insulating film; Forming a P-type capping film on the entire upper gate insulating film; Forming a gate conductive film on the P-type capping film; And And forming a first gate structure and a second gate structure by patterning the materials stacked in the first well region and the second well region. The method of claim 11, Forming a first gate structure on the first well region and a second gate structure on the second well region may include: Forming an N-type capping film on the first well region; Forming a gate insulating film on the N-type capping film and the second well region; Forming a P-type capping layer on the N-type capping layer and the gate insulating layer; Forming a gate conductive film on the P-type capping film; And And forming a first gate structure and a second gate structure by patterning the materials stacked in the first well region and the second well region. The method of claim 11, The first N-type keping pattern includes at least one of LaO, GdO, DyO, SrO, BaO, and ErO. The method of claim 11, wherein The first P-type keping pattern includes at least one of an aluminum oxide film and an aluminum metal oxide film. The method of claim 11, wherein The first gate insulating pattern and the second gate insulating pattern may include a silicon oxide film, a silicon oxynitride film, a hafnium oxide film, a hafnium silicon oxide film, a zirconium oxide film, a zirconium silicon oxide film, a hafnium oxynitride film, a hafnium silicon oxynitride film, a zirconium oxynitride film, and a zirconium silicon. A method of forming a semiconductor device, comprising at least one of an oxynitride film and a titanium oxide film.

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