KR20100030500A - Semiconductor package and method of fabricating the same - Google Patents

Semiconductor package and method of fabricating the same Download PDF

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Publication number
KR20100030500A
KR20100030500A KR1020080089472A KR20080089472A KR20100030500A KR 20100030500 A KR20100030500 A KR 20100030500A KR 1020080089472 A KR1020080089472 A KR 1020080089472A KR 20080089472 A KR20080089472 A KR 20080089472A KR 20100030500 A KR20100030500 A KR 20100030500A
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KR
South Korea
Prior art keywords
film
stress
layer
semiconductor package
wafer
Prior art date
Application number
KR1020080089472A
Other languages
Korean (ko)
Inventor
박명근
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080089472A priority Critical patent/KR20100030500A/en
Publication of KR20100030500A publication Critical patent/KR20100030500A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to protect a wafer from chipping by performing a sawing process to the wafer after a stress buffer layer is formed on the scribe line part of the wafer. CONSTITUTION: A semiconductor chip(102) includes an upper surface(103) and a lower surface(105). Bonding pads(108) and a scribe region(106) is arranged on the upper surface. A protective layer includes openings to expose the bonding pads and the scribe region. A first stress buffer layer(101a) covers the edge of the protective layer and the exposed scribe region. A second stress buffer layer(101b) covers the edge of the lower surface.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that can improve the overall yield by preventing cracking of the wafer during sawing.

The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables these product design goals is package assembly technology.

This package assembly technology is a technique for securing an operation reliability of a semiconductor chip by protecting the semiconductor chip on which an integrated circuit is formed through an wafer assembly process from an external environment and being easily mounted on a substrate.

Existing packages are manufactured by cutting a wafer into separate semiconductor chips and then repackaging the individual semiconductor chips.

However, the packaging process itself includes many unit processes, that is, processes such as chip attaching, wire bonding, molding, trimming and forming, and thus, recently assembled in separate semiconductor chips. Without this progress, a technique called a wafer level package (Wafer Level Package), which is manufactured through a redistribution operation in a wafer state, the formation of a ball-type external connection terminal, and an operation of separating individual semiconductor chips, has been proposed.

However, although not shown and described in detail, in the conventional wafer level package described above, the scribe portion is sawed to individualize the wafer to the semiconductor chip level, and the stress and wafers generated in the scribe portion when the scribe portion is sawed Due to its brittle nature, chipping such as cracking occurs in the wafer.

The cracking of the wafer becomes more severe when a step of the polyimide-isodeoloquinazolinedione (PIQ) material covering the semiconductor chip and a metal or a polymer remain on the semiconductor chip. As a result, the thickness of the wafer is getting thinner, and the cracking phenomenon of the wafer is intensified.

On the other hand, in order to prevent the cracking of the wafer as described above, a method of individualizing the wafer to the semiconductor chip level without using the blade (Blade) method as in the prior art has been proposed, in this case, the cost required to introduce the equipment is very expensive In addition, there is currently no way to solve the problem of the recycling of the equipment currently in use, there are various constraints related to the manufacturing cost.

The present invention provides a semiconductor package and a method of manufacturing the same that can prevent the wafer from breaking when the wafer is sawed.

In addition, the present invention provides a semiconductor package and a method of manufacturing the same, which can prevent the phenomenon of cracking the wafer and also prevent an increase in manufacturing cost.

A semiconductor package according to the present invention includes a semiconductor chip having an upper surface and a lower surface corresponding to the upper surface, and having a bonding pad and a scribe area on the upper surface; A protective film having an opening exposing the bonding pad and the scribe area; A first stress mitigating layer covering an edge of the passivation layer and the exposed scribe area; And a second stress mitigating layer covering an edge of the bottom surface.

The protective film includes a PIQ (Polyimide-Isoindolo Quinazolinedione) film or a Pix film.

The first stress mitigating layer includes a first insulating layer, and the second stress mitigating layer includes a second insulating layer.

Each of the first and second insulating layers may include one of an epoxy or under-fill material.

The first stress mitigating film and the second stress mitigating film each include an insulating tape.

The semiconductor device further includes an encapsulation member surrounding a side surface of the semiconductor chip exposed by the first stress mitigating layer, a bottom surface of the semiconductor chip exposed by the second stress mitigating layer, and side surfaces of the first and second stress mitigating layers. .

In addition, a method of manufacturing a semiconductor package according to the present invention may include: preparing a wafer including a plurality of semiconductor chips having bonding pads disposed on an upper surface thereof and partitioned by a scribe line; Forming a passivation layer on the wafer, the passivation layer having an opening exposing the bonding pads and the scribe line; Forming a first preliminary stress relief layer covering an upper edge of the passivation layer and the scribe line on the upper surface; And forming a second preliminary stress relief layer covering the scribe line on a lower surface corresponding to the upper surface.

The protective film is formed of a PIQ (Polyimide-Isoindolo Quinazolinedione) film or a Pix film.

The first preliminary stress relaxation film is formed of a first insulating film, and the second preliminary stress relaxation film is formed of a second insulating film.

The first and second insulating layers may be formed of any one of an epoxy or an under-fill material, respectively.

The first stress mitigating film and the second stress mitigating film are each characterized in that they are insulating tapes.

After the forming of the second preliminary stress relief layer, forming each of the semiconductor chips along the scribe line to form first and second stress relaxation films on the upper and lower surfaces of the semiconductor chip, respectively; It further includes.

In the forming of the first stress mitigating layer and the second stress mitigating layer, the individualization of each of the semiconductor chips may include attaching a carrier substrate to a lower surface of the wafer.

The carrier substrate is characterized in that the receiving groove for receiving the second stress relief film is formed in close contact with the wafer.

After forming the first stress relaxation film and the second stress relaxation film, the side surface of the semiconductor chip exposed by the first stress relaxation film, the lower surface of the semiconductor chip exposed by the second stress relaxation film and the And forming an encapsulation member surrounding side surfaces of the first and second stress relaxation films.

According to an embodiment of the present invention, a stress relaxation film is formed on a portion of a scribe line when a semiconductor package is formed, and then a wafer is sawed by the stress relaxation film, thereby causing stress on the scribe portion and a breakable property of the wafer. The cracking phenomenon in the wafer can be prevented.

Therefore, the present invention can improve the yield of the entire package.

In addition, since the present invention can prevent cracking of the wafer only by the stress relaxation film formed on the scribe line portion, it is not necessary to introduce additional equipment for individualizing the wafer to the semiconductor chip level without using the blade method. Various constraints related to the manufacturing cost of the package can be overcome.

Hereinafter, a semiconductor package and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and the general knowledge in the art. Those skilled in the art can implement the present invention in various other forms without departing from the technical spirit of the present invention.

In detail, FIG. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a perspective view illustrating the semiconductor package according to an embodiment of the present invention. .

As shown in FIGS. 1 and 2, a semiconductor package according to an embodiment of the present invention may include a semiconductor chip 102, a protective film 110, a first stress mitigating film 101a, and a second stress mitigating film 101b. Include.

The semiconductor chip 102 has an upper surface 103 and a lower surface 105 corresponding to the upper surface 103, and includes a bonding pad 108 and a scribe region 106 provided on the upper surface 103.

The passivation layer 110 is disposed at the center of the upper surface 103 and has openings exposing the bonding pads 108 and the scribe region 106, and the passivation layer 110 may be, for example, a polyimide-isodeoloquinazinodione (PIQ) film or Contains a Pix film.

The first stress mitigating layer 101a covers the edge of the passivation layer 110 and the top surface 103 of the semiconductor chip 102 exposed by the passivation layer 110, that is, the exposed scribe region 106.

The second stress relaxation film 101b covers the edge of the bottom surface 105 of the semiconductor chip 102 corresponding to the first stress relaxation film 101a provided on the upper surface 103.

Here, the first stress relief film 101a and the second stress relief film 101b each include a first insulation film and a second insulation film, and each of the first insulation film and the second insulation film may be, for example, epoxy or epoxy. Under-fill material.

In addition, the first stress mitigating film 101a and the second stress mitigating film 101b may each include an insulating tape, for example.

In addition, the semiconductor package 100 is formed by the outer side surface 107 and the second stress relaxation film 101b of the semiconductor chip 102 exposed by the first stress relaxation film 101a as shown in FIG. 3. The semiconductor device 102 further includes an encapsulation member 118 provided to protect the lower surface 105 of the exposed semiconductor chip 102 and the side surfaces of the first and second stress relaxation films 101a and 101b.

The encapsulation member 118 includes, for example, an epoxy molding compound (EMC).

4A through 4E are cross-sectional views illustrating processes for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a wafer 150, which is divided into a scribe line 106 and includes a plurality of semiconductor chips 102 having a bonding pad 108 on an upper surface 103, is provided.

Each of the semiconductor chips 102 has an upper surface 103 on which a bonding pad 108 is formed, and a lower surface 105 facing the upper surface 103.

Referring to FIG. 4B, a passivation layer 110 having openings exposing the bonding pads 108 and the scribe line 106 is formed on an upper surface of the wafer 150 including the semiconductor chips 102.

Here, the protective film 110 is formed of, for example, a polyimide-isodeoloquinazolinedione (PIQ) film or a Pix film.

Referring to FIG. 4C, a first preliminary stress relief layer 112a is formed on the wafer 150 to cover the top edge of the passivation layer 110 and the scribe line 106 of the top surface 103 of the semiconductor chip 102.

Then, for example, the first preliminary stress mitigating layer 112a and the second preliminary stress mitigating layer covering the scribe line 106 of the lower surface 105 corresponding to the upper surface 103 of the semiconductor chip 102 ( 112b) is formed.

In this case, the first preliminary stress relief film 112a and the second preliminary stress relief film 112b are formed of a first insulating film and a second insulating film, respectively, and the first and second insulating films are, for example, epoxy. Or an under-fill material.

In addition, the first preliminary stress relaxation film 112a and the second preliminary stress relaxation film 112b may be each formed of an insulating tape, for example.

4D and 4E, each of the semiconductor chips 102 along the scribe line 106 may be individualized, and the first stress mitigating film 101a may be formed on the upper and lower surfaces 103 and 105 of the semiconductor chip 102, respectively. And a second stress mitigating film 101b is formed.

In this case, the individualization of the semiconductor chips 102 along the scribe line 106 of the wafer 150 is performed by attaching the carrier substrate 114 to the bottom surface of the wafer 105.

The carrier substrate 114 is formed such that an accommodating groove (not shown) accommodating the second preliminary stress relief layer 112b is formed to be in close contact with the wafer 150.

The reason for using the carrier substrate 114 is that the first stress relaxation film 101a and the second stress relaxation film formed on the upper surface 103 and the lower surface 105 of the semiconductor chip 102 when the wafer 150 is sawed. This is to minimize the height difference between the semiconductor chips 102 due to 101b).

On the other hand, although not shown, after each semiconductor chip along the scribe line to form a first stress relief film and a second stress relief film respectively on the upper and lower surfaces of the semiconductor chip, the semiconductor chip exposed by the first stress relief film Side surfaces of the semiconductor chip exposed by the second stress mitigating layer, side surfaces of the semiconductor chip exposed by the second stress mitigating layer, and side surfaces of the semiconductor chip exposed by the second stress mitigating layer, An encapsulation member may be further formed to surround side surfaces of the first and second stress relief layers.

The encapsulation member may be formed of, for example, an epoxy molding compound (EMC).

As described above, according to the present invention, the stress relaxation film is formed on the scribe line portion as described above, and then the wafer is sawed, so that the stress generated in the scribe portion and the breakable property of the wafer when the wafer is sawed by the stress relaxation film The cracking phenomenon in the wafer can be prevented.

Therefore, the present invention can improve the yield of the entire package.

In addition, since the present invention can prevent cracking of the wafer only by the stress relaxation film formed on the scribe line portion as described above, it is not necessary to introduce additional equipment for individualizing wafers at the level of semiconductor chips rather than blades. In addition, several constraints related to the manufacturing cost of the entire package can be overcome.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2 is a perspective view illustrating a semiconductor package according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention.

4A to 4E are cross-sectional views illustrating processes for manufacturing a semiconductor package according to an embodiment of the present invention.

Claims (15)

A semiconductor chip having an upper surface and a lower surface corresponding to the upper surface, and having a bonding pad and a scribe region on the upper surface; A protective film having an opening exposing the bonding pad and the scribe area; A first stress mitigating layer covering an edge of the passivation layer and the exposed scribe area; And A second stress mitigating layer covering an edge of the bottom surface; A semiconductor package comprising a. The method of claim 1, The protective film is a semiconductor package, characterized in that it comprises a PIQ (Polyimide-Isoindolo Quinazolinedione) film or Pix film. The method of claim 1, And the first stress mitigating layer comprises a first insulating layer and the second stress mitigating layer comprises a second insulating layer. The method of claim 3, wherein And the first and second insulating layers each comprise one of an epoxy and an under-fill material. The method of claim 1, And the first stress mitigating layer and the second stress mitigating layer each comprise an insulating tape. The method of claim 1, And an encapsulation member surrounding a side surface of the semiconductor chip exposed by the first stress mitigating layer, a bottom surface of the semiconductor chip exposed by the second stress mitigating layer, and side surfaces of the first and second stress mitigating layers. A semiconductor package, characterized in that. Providing a wafer including a plurality of semiconductor chips defined by a scribe line and having bonding pads disposed on an upper surface thereof; Forming a passivation layer on the wafer, the passivation layer having an opening exposing the bonding pads and the scribe line; Forming a first preliminary stress relief layer covering an upper edge of the passivation layer and the scribe line on the upper surface; And Forming a second preliminary stress relief layer covering the scribe line on a lower surface corresponding to the upper surface; Method of manufacturing a semiconductor package comprising a. The method of claim 7, wherein The protective film is a manufacturing method of a semiconductor package, characterized in that formed of a PIQ (Polyimide-Isoindolo Quinazolinedione) film or Pix film. The method of claim 7, wherein The first preliminary stress relaxation film is formed of a first insulating film, and the second preliminary stress relaxation film is formed of a second insulating film. The method of claim 9, The first and the second insulating film is a semiconductor package manufacturing method, characterized in that formed of any one of an epoxy (Epoxy) or an under-fill (Under-Fill) material. The method of claim 7, wherein And the first stress mitigating film and the second stress mitigating film are insulating tapes, respectively. The method of claim 7, wherein After forming the second preliminary stress relief film, Individualizing the semiconductor chips along the scribe line to form first and second stress mitigating layers on the top and bottom surfaces of the semiconductor chip, respectively; The method of manufacturing a semiconductor package further comprising. The method of claim 12, In the forming of the first stress mitigating layer and the second stress mitigating layer, the individualization of each of the semiconductor chips may include: Attaching a carrier substrate to a bottom surface of the wafer; Method of manufacturing a semiconductor package comprising a. The method of claim 13, The carrier substrate is a manufacturing method of a semiconductor package, characterized in that the receiving groove for receiving the second stress relief film is formed in close contact with the wafer. The method of claim 12, After forming the first stress relaxation film and the second stress relaxation film, Forming an encapsulation member surrounding a side surface of the semiconductor chip exposed by the first stress mitigating layer, a bottom surface of the semiconductor chip exposed by the second stress mitigating layer, and side surfaces of the first and second stress mitigating layers. step; The method of manufacturing a semiconductor package further comprising.
KR1020080089472A 2008-09-10 2008-09-10 Semiconductor package and method of fabricating the same KR20100030500A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210002350A (en) * 2017-06-30 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device and method of manufacture
US11121050B2 (en) 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210002350A (en) * 2017-06-30 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device and method of manufacture
US11121050B2 (en) 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
US11201097B2 (en) 2017-06-30 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device

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