KR20100029947A - Test mode signal generation circuit and test apparatus using the same - Google Patents

Test mode signal generation circuit and test apparatus using the same Download PDF

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Publication number
KR20100029947A
KR20100029947A KR1020080088659A KR20080088659A KR20100029947A KR 20100029947 A KR20100029947 A KR 20100029947A KR 1020080088659 A KR1020080088659 A KR 1020080088659A KR 20080088659 A KR20080088659 A KR 20080088659A KR 20100029947 A KR20100029947 A KR 20100029947A
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KR
South Korea
Prior art keywords
signal
test
test mode
mode signal
enable
Prior art date
Application number
KR1020080088659A
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Korean (ko)
Inventor
나은성
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080088659A priority Critical patent/KR20100029947A/en
Publication of KR20100029947A publication Critical patent/KR20100029947A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A test mode signal generation circuit and a test device thereof are provided to reduce test time by enabling/disabling a test mode signal through a same test signal. CONSTITUTION: An enable unit(100) generates an enable signal enabling/disabling a test mode signal in response to a test signal. A test mode signal generating unit(200) executes a latch operation in response to the test signal. The test mode signal generating unit generates the test mode signal according to the enable signal. The enable unit generates the enable signal according to the test mode signal in the enable state of the test signal.

Description

Test mode signal generation circuit and test device using the same {Test mode Signal Generation Circuit and Test Apparatus using the same}

The present invention relates to a test mode signal generation circuit, and a test mode signal generation circuit and a test apparatus including the same that can increase the convenience of the test.

As semiconductor memory devices become more and more high-density, defect rates also increase rapidly. Therefore, a test is performed to verify a defect of the semiconductor memory device before the semiconductor memory device is produced and sold as a product. The test is performed by operating a plurality of test modes to reduce test time and to create and test various situations.

1 is a view showing a test mode signal generation circuit according to the prior art.

The test mode signal generation circuit according to the related art includes a PMOS transistor Pm, an NMOS transistor Nm, and a latch unit 10. The PMOS transistor Pm receives a signal RESETB in which the reset signal RESET is inverted through a gate, and an external voltage VDD is applied to a source terminal. The NMOS transistor Nm receives a test signal TEST as a gate, a source terminal is connected to a ground voltage terminal, and a drain terminal is connected to a drain terminal of the PMOS transistor Pm. The latch unit 10 includes an inverter chain connected to a drain terminal of the PMOS transistor Pm and the NMOS transistor Nm. The inverter chain consists of first and second inverters IV1, IV2.

The operation of the test mode signal generation circuit according to the prior art is as follows. First, when the reset signal RESET is initially applied to the gate of the PMOS transistor Pm, the latch unit 10 generates a test mode signal TM which is disabled to a low level. Thereafter, in order to enter the test mode, a test signal TEST, which is a high level pulse signal, is applied to the gate of the NMOS transistor Nm. Accordingly, the latch unit 10 may generate a test mode signal TM that is enabled high, and enter the test mode through the test mode signal TM. After that, the test is terminated and the reset signal RESET is applied to the gate of the PMOS transistor Pm again to exit the test mode. Thus, the test mode signal TM is disabled, and the test ends.

Conventionally, a plurality of test mode signal generation circuits as described above are provided to generate a plurality of test mode signals TM. 2 is an operation timing diagram of a test mode signal according to the prior art.

In FIG. 2, it can be seen that the first to third test signals TEST1, TEST2, and TEST3 are applied to enable the first to third test mode signals TM1, TM2, and TM3. The first to third test mode signals TM1, TM2, and TM3 are enabled to enter the respective test modes to perform a test. After that, the reset signal RESET is applied to terminate the test while disabling all of the first to third test mode signals TM1, TM2, and TM3.

As described above, in the prior art, while entering a plurality of test modes and performing a test, the test is terminated through one reset signal at the same time. In this case, in order to end a test mode in which sufficient tests have been performed, a problem arises that the test mode in which sufficient tests have not yet been performed must be terminated together.

Therefore, in order to perform a test that has not been sufficiently performed, it is necessary to enter the test mode again, which increases the test time and causes various problems in that various tests cannot be performed individually.

In order to solve the above problems, an object of the present invention is to provide a test mode signal generation circuit and a generation method that can enable and disable each test mode signal individually.

According to an exemplary embodiment of the present invention, a test mode signal generation circuit may include an enable unit configured to generate an enable signal for enabling or disabling a test mode signal in response to a test signal; And a test mode signal generator configured to perform a latch operation in response to the test signal and to receive the enable signal and generate the test mode signal. It includes.

In addition, the test mode signal generation method according to an embodiment of the present invention comprises the first step of enabling the test mode signal by applying a test signal; And disabling the test mode signal by applying the test signal again. It includes.

In addition, the test apparatus according to an embodiment of the present invention may enable the first test mode signal when the first test signal is applied, and disable the first test mode signal when the first test signal is applied again. 1 test mode signal generation circuit; And a second test mode signal generation circuit for enabling the second test mode signal when a second test signal is applied and disabling the first test mode signal when the second test signal is applied again. It includes.

According to the present invention, it is possible to enable or disable the test mode signal by using the same test signal, thereby reducing the test time and the various test modes can be sufficiently performed individually.

3 is a circuit diagram illustrating a test mode signal generation circuit according to an exemplary embodiment of the present invention. As shown in FIG. 3, the test mode signal generation circuit according to the embodiment of the present invention includes an enable unit 100 and a test mode signal generator 200.

The enable unit 100 receives the test mode signal TM in response to the test signal TEST and generates the enable signal EN. The enable unit 100 generates the enable signal EN which is disabled only when the test signal TEST is enabled. The test signal TEST is a pulse signal that may be input to enter the test mode. The test mode signal TM is a signal that maintains an enabled state while a test is performed. That is, when the test mode signal TM is enabled, the test mode is entered and the test is performed. When the test mode signal TM is disabled, the test is terminated.

The test mode signal generator 200 receives the enable signal EN in response to the test signal TEST and generates a test mode signal TM. When the test signal TEST is enabled, the test mode signal generator 200 receives the enable signal EN to generate the test mode signal TM, and the test signal TEST is displayed. When enabled, the latch operation is performed to generate the test mode signal TM.

The test mode signal generation circuit according to the embodiment of the present invention may further include a reset unit 300. The reset unit 300 initially receives the reset signal RESET to initialize the test mode signal TM to the disabled state. The reset signal RESET is a pulse signal that can be input externally to initialize the test mode signal TM to a disabled state.

A detailed configuration of a test mode signal generation circuit according to an embodiment of the present invention will be described with reference to FIG. 3.

The enable unit 100 includes a first inverter IV1 and an enable switching unit 110. The first inverter IV1 receives the test mode signal TM and inverts it. The enable switching unit 110 determines whether to turn on in response to the test signal TEST. In the embodiment of the present invention, the enable switching unit 110 may be configured as a first tri-state inverter (TIV1) that is determined to be turned on by the test signal (TEST). For example, the enable switching unit 110 is turned off when the test signal TEST is disabled, and is turned on when the test signal TEST is enabled to invert the output of the first inverter IV1. The enable signal EN can be generated.

The test mode signal generator 200 includes a second inverter IV2 and a latch control unit 210. The latch controller 210 determines whether to turn on in response to the test signal TEST. In an exemplary embodiment of the present invention, the latch control unit 210 may be configured as a second tree state inverter TIV2 whose turn on is determined by the test signal TEST. For example, the latch control unit 210 may be turned off when the test signal TEST is enabled, and may be turned on when the test signal TEST is disabled. The second inverter IV2 inverts the enable signal or inverts the output of the second tree state inverter TIV2 to generate the test mode signal TM. That is, when the test signal TEST is enabled, the second inverter IV2 inverts the enable signal EN to turn off the test signal signal TM because the second tree state inverter TIV2 is turned off. Create On the other hand, when the test signal TEST is disabled, since the second tree state inverter TIV2 is turned on, the second inverter IV2 and the second tree state inverter TIV2 perform a latch operation. The test mode signal TM is generated.

The reset unit 300 may be configured as a MOS transistor. The MOS transistor receives a reset signal RESET to a gate and an external voltage VDD to one of a source terminal and a drain terminal, and the other terminal is an output terminal of the first tree state inverter and the second inverter. Is connected to the input of. 3 illustrates an example in which the reset unit includes a PMOS transistor Pm.

4 is an operation timing diagram of a test mode signal generation circuit according to an embodiment of the present invention. The operation of the test mode signal generation circuit according to the embodiment of the present invention will be described with reference to FIG. 4.

When the reset signal RESET is initially enabled, the PMOS transistor Pm receiving the signal RESETB in which the reset signal RESET is inverted is turned on. A high level pulse signal corresponding to an external voltage VDD is applied to the second inverter IV2 through the turned on PMOS transistor Pm, and the second inverter IV2 is a pulse signal of the high level. Inverts to generate a test mode signal TM that is disabled to low.

Thereafter, the test signal TEST is enabled to enable the test mode signal TM so that the test can be performed. When the test signal TEST is enabled high, the first tree state inverter TIV1 constituting the enable switching unit 110 is turned on and the second tree state constituting the latch control unit 210 is turned on. Inverter TIV2 is turned off. At this time, the enable unit 100 receives the test mode signal TM which is fed back and generates the low level enable signal EN. That is, the first inverter IV1 inverts the test mode signal TM at a low level, and the first tree state inverter TIV1 turned on inverts the output of the first inverter IV1 to low level. To generate an enable signal (EN).

When the test signal TEST is enabled, since the second tree state inverter TIV2 constituting the latch control unit 210 is turned off, the test mode signal generator 200 generates the low level enable signal. (EN) is inverted to generate the test mode signal TM of a high level.

Since the test signal TEST is a high level pulse signal, soon after the test mode signal TM is enabled, the first tree state inverter TIV1 is turned off and the second tree state inverter TIV2 is turned off. Is turned on. Accordingly, the test mode signal generator 200 performs a latch operation to maintain the test mode signal TM in a high enabled state. That is, the test mode signal is input by the second tree state inverter TIV2 inverting the output (the test mode signal TM) of the high level second inverter IV2 and inputting it to the second inverter IV2 again. (TM) is the enabled state.

After that, when the test is terminated, the test signal TEST is once again enabled. When the test signal TEST is enabled again, the first tree state inverter TIV1 is turned on and the second tree state inverter TIV2 is turned off. Since the enable unit 100 receives the test mode signal TM that is enabled high, the enable unit 100 generates an enable signal EN that is enabled high. The second inverter IV2 of the test mode signal generator 200 inverts the enable signal EN to generate a test mode signal TM that is disabled low. Thereafter, the first tree state inverter TIV1 is turned off and the second tree state inverter TIV2 is turned on, so that the test mode signal generator 200 performs a latch operation and the test mode signal TM ) Remains disabled.

The present invention may enable and maintain a test mode signal by applying a test signal, and may disable the test mode signal by applying the same test signal once again.

For example, a plurality of test mode signal generation circuits may be provided in a semiconductor memory device. When the test is performed using the three test modes, the semiconductor memory device may include the three test mode signal generation circuits. First to third test signals are input to each test mode signal generation circuit, and generate first to third test mode signals, respectively.

5 is an operation timing diagram of a test mode signal when an embodiment of the present invention is applied.

As shown in FIG. 5, when the first test signal TEST1 is first applied, the first test mode signal TM1 is enabled, and then second and third test signals TEST2 and TEST3 are sequentially applied. The two test mode signal TM2 and the third test mode signal TM3 are enabled. Thereafter, the second test signal, the first test signal, and the third test signal TEST2, TEST1, and TEST3 are applied again to the second test mode signal TM2, the first test mode signal TM1, and the third test. The mode signal TM3 is in turn disabled.

That is, in the prior art, the test signals TTM1, TEST2, and TEST3 are identical to the test signals TEST1, TEST2, and TEST3, whereas the test mode signals TM1, TM2, and TM3 are terminated by applying the reset signal RESET. It can be seen that the mode signals TM1, TM2, TM3 can be disabled at a desired timing. In addition, the test mode signal TM may be collectively disabled by applying the reset signal RESET.

Although the semiconductor memory device has been described above by way of example, the present invention is not limited thereto. The test mode signal generation circuit according to the present invention can be used not only in the semiconductor memory device but also in all electronic fields for performing a test using the test mode.

Test mode signal generation method according to an embodiment of the present invention is as follows. In the test mode signal generation method according to an exemplary embodiment of the present invention, the test mode signal is generated by first applying the test signal TEST to enable the test mode signal TM and again applying the same test signal TEST to the test mode signal. And a second step of disabling (TM).

The method of generating a test mode signal according to an embodiment of the present invention may further include initializing the test mode signal TM to a disabled state by applying a reset signal RESET before the first step. The method may further include disabling the test mode signal TM by applying a reset signal RESET before the step 2 is performed.

In addition, the test mode signal generation method according to an embodiment of the present invention may further comprise the step of latching the enable state of the test mode signal (TM) before the start of the second step after the first step ends.

By enabling and disabling each test mode at an individual timing with only each test signal without using the reset signal collectively, various tests can be performed sufficiently and test time can be shortened. The present invention can be understood as follows.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a test mode signal generation circuit according to the prior art;

2 is an operation timing diagram of a test mode signal applying the prior art;

3 is a circuit diagram of a test mode signal generation circuit according to an embodiment of the present invention;

4 is an operation timing diagram of a test mode signal generation circuit according to an embodiment of the present invention;

5 is an operation timing diagram of a test mode signal to which the present invention is applied.

<Description of the symbols for the main parts of the drawings>

100: enable unit 110: enable switching unit

200: test mode signal generation unit 210: latch control unit

300: reset unit

Claims (29)

An enable unit configured to generate an enable signal for enabling or disabling the test mode signal in response to the test signal; And A test mode signal generator configured to perform a latch operation in response to the test signal, and generate the test mode signal by receiving the enable signal; Test mode signal generation circuit comprising a. The method of claim 1, And the enable unit is configured to receive the test mode signal and generate the enable signal when the test signal is enabled. The method according to claim 1 or 2, The enable unit includes an inverter for inverting the test mode signal; And An enable switching unit to determine whether to turn on by the test signal, and to generate the enable signal by inverting the output of the inverter; Test mode signal generation circuit, characterized in that consisting of. The method of claim 3, wherein And the enable switching unit comprises a tri-state inverter, which is turned on when the test signal is enabled and turned off when the test signal is disabled. The method of claim 1, And the test mode signal generator generates the test mode signal by inverting the enable signal when the test signal is enabled. The method of claim 1, And the test mode signal generator is configured to maintain a level of the test mode signal by performing a latch operation when the test signal is disabled. The method according to any one of claims 1, 5 or 6, The test mode signal generator may include an inverter for inverting the enable signal; And A latch control unit determining whether to turn on by the test signal and inverting an output of the inverter; Test mode signal generation circuit, characterized in that consisting of. The method of claim 7, wherein And the latch control unit comprises a tri-state inverter which is turned off when the test signal is enabled and is turned on when the test signal is disabled. The method of claim 1, And a reset unit configured to receive a reset signal and to disable the test mode signal. In the method for generating a test mode signal for determining whether to enter the test mode in response to the test signal, A first step of applying the test signal to enable the test mode signal; And Disabling the test mode signal by applying the test signal again; Test mode signal generation method comprising a. The method of claim 10, And before the first step, applying a reset signal to initialize the test mode signal to a disabled state. The method of claim 10, And before the second step is performed, disabling the test mode signal by applying a reset signal. The method of claim 10, And latching a state in which the test mode signal is enabled after the end of the first step and before the second step is performed. A first test mode signal generation circuit for enabling the first test mode signal when a first test signal is applied and disabling the first test mode signal when the first test signal is applied again; And A second test mode signal generation circuit for enabling the second test mode signal when a second test signal is applied, and disabling the first test mode signal when the second test signal is applied again; Test device comprising a. The method of claim 14, The first test mode signal generation circuit, A first enable unit configured to generate a first enable signal to enable or disable the first test mode signal in response to the first test signal; And A first test mode signal generator configured to perform a latch operation in response to the first test signal, and receive the first enable signal and generate the first test mode signal; Test apparatus, characterized in that consisting of. The method of claim 15, And the first enable unit is configured to receive the first test mode signal and generate the first enable signal when the first test mode signal is enabled. The method according to claim 15 or 16, The first enable unit includes an inverter for inverting the first test mode signal; And A first enable switching unit configured to determine whether to turn on by the first test signal, and to invert the output of the inverter to generate the first enable signal; Test apparatus, characterized in that consisting of. The method of claim 15, The first test mode signal generator, in response to the first test signal is enabled, inverting the first enable signal, wherein the test device according to claim 1 generates a first test mode signal. The method of claim 15, And the first test mode signal generator is configured to maintain a level of the first test mode signal by performing a latch operation when the first test signal is disabled. The method of claim 15, The first test mode signal generator may include an inverter for inverting the first enable signal; And A latch control unit determining whether to turn on by the first test signal and inverting an output of the inverter; Test apparatus, characterized in that consisting of. The method of claim 15, And a reset unit configured to receive a reset signal and to disable the first test mode signal. The method of claim 14, The second test mode signal generation circuit, A second enable unit configured to generate a second enable signal to enable or disable the second test mode signal in response to the second test signal; And A second test mode signal generator configured to perform a latch operation in response to the second test signal, and receive the second enable signal and generate the second test mode signal; Test apparatus, characterized in that consisting of. The method of claim 22, And the second enable unit is configured to receive the second test mode signal and generate the second enable signal when the second test mode signal is enabled. The method of claim 22 or 23, The second enable unit includes an inverter for inverting the second test mode signal; And A second enable switching unit configured to determine whether to turn on by the second test signal, and to generate the second enable signal by inverting the output of the inverter; Test apparatus, characterized in that consisting of. The method of claim 22, The second test mode signal generator, when the second test signal is enabled, inverting the second enable signal to generate the second test mode signal. The method of claim 25, And the second test mode signal generator is configured to maintain a level of the second test mode signal by performing a latch operation when the second test signal is disabled. The method of claim 22, The second test mode signal generator may include an inverter for inverting the second enable signal; And A latch control unit determining whether to turn on by the second test signal and inverting an output of the inverter; Test apparatus, characterized in that consisting of. The method of claim 22, And a reset unit configured to receive a reset signal and to disable the second test mode signal. The method of claim 14, And a reset unit configured to receive a reset signal and to disable the first and second test mode signals collectively.
KR1020080088659A 2008-09-09 2008-09-09 Test mode signal generation circuit and test apparatus using the same KR20100029947A (en)

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