KR20100029483A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20100029483A
KR20100029483A KR1020080088289A KR20080088289A KR20100029483A KR 20100029483 A KR20100029483 A KR 20100029483A KR 1020080088289 A KR1020080088289 A KR 1020080088289A KR 20080088289 A KR20080088289 A KR 20080088289A KR 20100029483 A KR20100029483 A KR 20100029483A
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KR
South Korea
Prior art keywords
forming
gate
contact hole
pattern
active region
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KR1020080088289A
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Korean (ko)
Inventor
신승아
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주식회사 하이닉스반도체
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Priority to KR1020080088289A priority Critical patent/KR20100029483A/en
Publication of KR20100029483A publication Critical patent/KR20100029483A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A manufacturing method of a semiconductor device is provided to prevent a short failure between a gate and a landing plug by forming a contact hole for a landing plug connected to a bit line to expose only an active area. CONSTITUTION: An active region(33) passes through an element isolation layer by an element isolation layer(32). A gate(38) has saddle-fin type channel structure. An insulating layer filling a gap between the gate is formed. A contact hole(42) exposing an active region by selectively etching the insulating layer is formed. A landing plug filling the contact hole and is connected to the bit line is formed.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a manufacturing technique of a semiconductor device. In particular, a semiconductor device having a saddle-fin type channel has a shortness between a landing plug and a gate connected to a bit line. It relates to a method for manufacturing a semiconductor device that can prevent the occurrence of defects.

In order to prevent generation of short channel effects (SCE) and deterioration of refresh characteristics due to an increase in the degree of integration of semiconductor devices, semiconductor devices having saddle-fin type channels are introduced and applied.

FIG. 1A is a plan view illustrating a semiconductor device having a saddle fin channel according to the related art, and FIG. 1B is a cross-sectional view of the semiconductor device according to the line X-X ′ shown in FIG. 1A.

Referring to FIGS. 1A and 1B, a method of manufacturing a semiconductor device having a saddle fin channel according to the related art is selectively etched by selectively etching a substrate 11 having an active region 13 defined by an isolation layer 12. A saddle pin pattern 14 is formed to cross the region 13 and the device isolation layer 12 at the same time.

Next, after filling the saddle pin pattern 14 and partially forming the gate 18 protruding onto the substrate 11, the gate spacer 19 is formed on both side walls of the gate 18. The gate 18 includes a gate insulating film 15, a gate electrode 16, and a gate hard mask film 17.

Next, after forming the oxide film 20 filling the gate 18, the contact hole 21 selectively exposes the upper surface of the active region 13 on both sides of the gate 18 by selectively etching the oxide film 20. To form. Here, the first contact hole 21A exposing both edges of the active region 13 is a hole type, and the second contact hole 21B exposing the central portion of the active region 13 is an element isolation film. It is formed as a slit type to expose up to 12).

Next, the contact hole 21 is filled with a conductive film to form a landing plug 22. In this case, the first landing plug 22A buried in the first contact hole 21A serves to connect the lower electrode of the capacitor and the active region 13 and the second buried in the second contact hole 21B. The landing plug 22B connects the bit line and the active region 13.

However, in the related art, as the design rule of the semiconductor device decreases, the line width of the device isolation film 12 decreases and the depth thereof increases, so that the device isolation film 12 is a spin on dielectric (SOD) having excellent buried characteristics. Form. Since the spin-on insulating film contains a plurality of impurities such as carbon (C) in the film, it is easily damaged during the etching process and the cleaning process of the oxide film 20 for forming the contact hole 21. In addition, since the second contact hole 21B is formed as a slit type that exposes both the active region 13 and the device isolation layer 12, the second landing plug 22B connected to the bit line as shown in 'X' of FIG. 1B. ) And a short-circuit defect frequently occur between the gate 18 formed in the device isolation film 12, thereby lowering the characteristics and manufacturing yield of the semiconductor device.

2 is a scanning electron microscope (Scanning Electron Microscope, SEM) image showing a cross section along the line X-X` cut line shown in FIG.

As shown in FIG. 2, it can be seen that a short circuit defect occurs between the gate 18 formed in the device isolation layer 12 and the second landing plug 22B.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and in the semiconductor device having a saddle pin-shaped channel, a semiconductor device can be prevented from generating short-circuit defects between a landing plug and a gate connected to a bit line. The purpose is to provide a method.

In accordance with an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a gate having a saddle-shaped channel structure simultaneously crossing the device isolation layer and the active region on a substrate on which an active region is defined by an element isolation layer; Forming a; Forming an insulating film filling the gate; Selectively etching the insulating layer to form a contact hole exposing only the active region, and filling the contact hole and forming a landing plug connected to the bit line. The method may further include forming spacers on both sidewalls of the gate.

The forming of the contact hole may include forming a line type hard mask pattern orthogonal to the gate and intersecting the active region on the insulating layer above the device isolation region, and forming the hard mask pattern and the gate. And etching the insulating layer with an etch barrier.

The forming of the gate may include selectively recess etching the substrate to form a first saddle pin pattern formed in the active region and the device isolation region, and a bottom surface and a bottom of the active region under the first saddle pin pattern. The method may include forming a saddle pin pattern formed of a second saddle pin pattern exposing sidewalls, and forming a gate in which the saddle pin pattern is buried and a part of which protrudes over the substrate.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, which simultaneously crosses the device isolation layer and the active region on a defined substrate of an active region by an element isolation layer, and has a saddle fin channel structure. Forming a gate; Forming a first spacer on both sidewalls of the gate; Forming an insulating film filling the gate; Selectively etching the insulating layer to form a contact hole exposing only the active region; Forming a first plug partially filling the contact hole; Forming a second spacer on the exposed sidewalls of the contact hole and forming a second plug to fill the rest of the contact hole to form a landing plug formed of the first and second plugs and connected to the bit line; do.

The first and second spacers may be formed of the same material, and the first and second spacers may include a nitride film.

The forming of the gate may include selectively recess etching the substrate to form a first saddle pin pattern formed in the active region and the device isolation region, and a bottom surface and a bottom of the active region under the first saddle pin pattern. The method may include forming a saddle pin pattern formed of a second saddle pin pattern exposing sidewalls, and forming a gate in which the saddle pin pattern is buried and a part of which protrudes over the substrate.

The forming of the contact hole may include forming a line type hard mask pattern orthogonal to the gate and intersecting the active region on the insulating layer above the device isolation region, and forming the hard mask pattern and the gate. And etching the insulating layer with an etch barrier.

The method may further include forming a recess pattern by etching the device isolation layer exposing the hard mask pattern and the gate as an etch barrier, after forming the contact hole, to form a recess pattern. The depth of the recess pattern may be greater than the depth of the second saddle pin pattern.

The first plug may include an epitaxial layer, for example, a silicon epitaxial layer. For this purpose, the first plug may be formed using a selective epitaxial growth method.

SUMMARY OF THE INVENTION The present invention based on the above-described problem solving means, in manufacturing a semiconductor device having a saddle pin-shaped channel, by forming a contact hole for the landing plug connected to the bit line to expose only the active region, between the gate and the landing plug There is an effect that can be prevented from occurring short-circuit defects at source.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

The present invention described below provides a method of manufacturing a semiconductor device capable of preventing short circuit defects between a landing plug connected to a gate and a bit line in a semiconductor device having a saddle-fin type channel.

3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with an embodiment of the present invention. In each figure, a is a plan view, and b is a cross-sectional view taken along the line II ′, II-II ′, and III-III ′ of FIG.

As shown in FIGS. 3A and 3B, after forming a trench for device isolation on the substrate 31, for example, a silicon substrate, the device isolation film 32 is formed by filling the trench with an insulating film. The device isolation layer 32 may be formed of an oxide layer, and may be formed of a spin on dielectric (SOD) layer having excellent embedding characteristics.

Here, an area in which the device isolation layer 32 is formed on the substrate 31 is defined as an 'device isolation region', and an area in the substrate 31 where the device isolation layer 32 is not formed is defined as an 'active region 33'. .

Next, after forming a hard mask pattern (not shown) for forming the saddle pin pattern 34 on the substrate 31, the substrate 31 is recessed (using a hard mask pattern as an etch barrier). etching to form a saddle pin pattern 34 crossing the device isolation layer 32 and the active region 33 at the same time. That is, the saddle pin pattern 34 extending in the first direction is formed on the substrate 31.

The saddle pin pattern 34 is formed on the first saddle pin pattern 34A and the isolation layer 32 formed in the active region 33, and the bottom surface and the bottom of the active region 33 under the first saddle pin pattern 34A. The second saddle pin pattern 34B may expose the sidewalls. That is, the depth H2 of the second saddle pin pattern 34B is greater than the depth H1 of the first saddle pin pattern 34A based on the upper surface of the substrate 31. Here, the line width W1 of the first saddle pin pattern 34A and the line width W2 of the second saddle pin pattern 34B may be the same (W1 = W2), or one may be larger (W1> W2 or W1 <W2).

The recess process for forming the saddle pin pattern 34 may be performed by using a dry etch. For example, the first saddle pin pattern 34A is formed by simultaneously etching the substrate 31 and the device isolation layer 32 using an etching gas having the same etching rate with respect to the substrate 31 and the device isolation layer 32. After that, the saddle is formed through a series of processes in which the second saddle pin pattern 34B is formed on the device isolation layer 32 by using an etching gas having an etching rate that is faster than the etching rate on the substrate 31. The fin pattern 34 may be formed.

Next, the saddle pin pattern 34 is buried, and a portion of the saddle pin pattern 34 is formed to protrude over the substrate 31. The gate 38 may be formed as a line pattern crossing the device isolation layer 32 and the active region 33 at the same time. That is, the gate 38 extending in the first direction is formed.

The gate 38 may be formed as a stacked structure in which the gate insulating film 35, the gate electrode 36, and the gate hard mask film 37 are sequentially stacked. The gate insulating layer 35 may be formed to cover the surface of the substrate 31 of the active region 33, particularly the sidewall of the active region 33 exposed by the second saddle pin pattern 34B. The gate insulating film 35 may be formed of an oxide film, eg, a silicon oxide film (SiO 2 ), and the silicon oxide film may be formed using a thermal oxidation film. The gate electrode 36 may be formed to fill the saddle pin pattern 34 so that a part thereof protrudes over the substrate 31, and may be any one selected from the group consisting of a polysilicon film (poly Si), a metallic film, and a conductive organic film. Or they can be formed by the laminated film by which they were laminated. As the metallic film, tungsten film (W), aluminum film (Al), titanium nitride film (TiN), iridium oxide film (IrO 2 ), titanium silicide film (TiSi), tungsten silicide film (WSi), ITO (Indium Tin Oxide) , IZO (Indium Zinc Oxide) and the like can be used. As the conductive organic film, pentacene, tetracene, anthracene and the like can be used. The gate hard mask film 37 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride or a laminated film in which these are stacked. Oxides include silicon oxide (SiO 2 ), Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Tetra Ethyle Ortho Silicate (TEOS), Un-doped Silicate Glass (USG), Spin On Glass (SOG) Plasma oxide films (High Density Plasma, HDP), spin on dielectric (SOD) and the like can be used. A silicon nitride film (Si 3 N 4 ) may be used as the nitride film, and a silicon oxynitride film (SiON) may be used as the oxynitride film.

Next, first spacers 39 serving as gate spacers are formed on both side walls of the gate 38. The first spacer 39 serves to prevent a short from occurring between the landing plug to be formed through the subsequent process and the gate 38. Accordingly, the first spacer 39 may be formed of an insulating material, for example, a nitride film, and a silicon nitride film (Si 3 N 4 ) may be used as the nitride film.

In this case, the first spacer 39 may be formed thinner than the thickness of a conventional gate spacer in order to increase the contact area between the landing plug to be formed through the subsequent process and the substrate 31. For example, the first spacer 39 may be formed to have a thickness of about 50% of the thickness of the conventional case spacer.

The first spacer 39 deposits a silicon nitride film on the entire surface of the structure including the gate 38, and then performs a front etching process, for example, an etchback, to leave the silicon nitride film on both sidewalls of the gate 38. It can be formed through the process of.

As shown in Figs. 4A and 4B, an insulating film 40 filling the gap between the gates 38 is formed. The insulating film 40 can be formed of an oxide film.

Next, a line type hard mask pattern 41 orthogonal to the gate 38 and intersecting between the active regions 33 is formed on the insulating film 40 on the device isolation layer 32. That is, the hard mask pattern 41 extending in the second direction perpendicular to the first direction is formed on the insulating film 40 on the device isolation layer 32. The hard mask pattern 41 serves as an etch barrier along with the gate 38 in a subsequent contact hole forming process for the landing plug.

Next, the insulating layer 40 is etched using the hard mask pattern 41 and the gate 38 as an etch barrier to form a contact hole 42 exposing only the active region 33. Hereinafter, the reference numeral of the etched insulating film 40 is changed to '40A' and described.

Here, the contact hole 42 is for the landing plug to be formed through a subsequent process, the side wall of the contact hole 42 in the first direction is provided by the gate 38, the contact hole 42 in the second direction Both side walls are provided by the insulating film 40A.

The contact hole 42 may include a first contact hole 42A exposing both edges of the active region 33 and a second contact hole 42B exposing a central portion of the active region 33. Conventionally, the first contact hole 42A is formed in a hole type, and the second contact hole 42B is a slit type for simultaneously exposing the active region 33 and the device isolation layer 32. Formed.

However, in the present invention, the first contact hole 42A and the second contact hole 42B are both hole type using the gate 38 and the hard mask pattern 41 orthogonal to the gate 38. It is characterized by forming. That is, both the first and second contact holes 42A and 42B are formed to expose only the active region 33. Therefore, as the second contact hole 42B is formed in the slit type, a problem caused by exposing the device isolation layer 32 may be prevented at the source.

As shown in FIGS. 5A and 5B, the device isolation layer 32 exposing the hard mask pattern 41 and the gate 38 as an etch barrier is etched to a predetermined depth to recess the recess pattern in the device isolation layer 32. 44). An etching process for forming the recess pattern 44 may be performed using a dry etching method. In this case, as the dry etching method, a full dry etching method such as an etch back may be used. For example, when the etching back is performed using the oxide film etching gas, only the exposed device isolation layer 32 may be selectively etched (or recessed).

 The recess pattern 44 serves to prevent shorts from occurring between the gates 38 passing through the device isolation layer 32. For reference, as the contact hole 42 is formed using the gate 38 and the hard mask pattern 41 orthogonal to the gate 38, the exposed device isolation layer 32 may be damaged during subsequent processes. As a result, a short may occur between the gates 38 passing through the device isolation layer 32.

The recess pattern 44 may have a depth H3 of the recess pattern 44 based on the upper surface of the substrate 31 to effectively prevent a short from occurring between the gates 38 passing through the device isolation layer 32. It is preferable to form a depth deeper than the depth H2 of the second saddle pin pattern 34B formed on the device isolation layer 32 (H3> H2). This is because most of the short-circuit defects are caused by the loss of the device isolation layer 32 under the gate 38 in which the first spacer 39 is not formed, thereby reducing the depth H3 of the recess pattern 44 to the second saddle pin. This is to remove the above-mentioned cause by forming deeper than the depth H2 of the pattern 34B.

Next, a cleaning process for removing the natural oxide film formed on the surface of the active region 33 exposed by the by-products and contact holes 42 generated in the process of forming the contact hole 42 and the recess pattern 44 Is carried out.

On the other hand, in the process of the above-described process, all the hard mask pattern 41 is lost and removed.

Next, a first plug 43 for partially filling the contact hole 42 is formed on the active region 33 having the surface exposed. In this case, the first plug 43 may be formed by using selective epitaxial growth (SEG) to selectively form only the active region 33 on which the surface is exposed. Therefore, the first plug 43 may be formed as an epitaxial layer. For example, the first plug 43 may be formed of an epitaxial silicon layer.

Here, the first plug 43 acts as a landing plug.

Next, the first plug 43 is doped with impurities to improve conductivity. In this case, the impurity doping process may be performed by in-situ doping while forming the first plug 43. In addition, the impurity doping process may be performed by ex-situ doping using an impurity ion implantation process after forming the first plug 43. Here, it is preferable to use an impurity having the same conductivity type as that of the junction region, for example, the source and drain regions (not shown). For example, boron (B), which is a P-type impurity, or phosphorus (P), which is an N-type impurity, may be used as the impurity.

As shown in FIGS. 6A and 6B, a second spacer is formed on the sidewall of the exposed structure. In detail, the second spacer 45 is formed on the exposed sidewall of the contact hole 42, the sidewall of the insulating layer 40A, and the sidewall of the recess pattern 44. The second spacer 45 serves to prevent short circuit defects between the landing plug and the gate 38 together with the first spacer, and may be formed of an insulating material. Therefore, the second spacer 45 may be formed of the same material as the first spacer 39, for example, a nitride film. As the nitride film, a silicon nitride film can be used.

Since the second spacers 45 formed on both sidewalls of the gate 38 serve to prevent a short between the landing plug and the gate 38 together with the first spacer 39, the thickness of the second spacers is typically It may be formed thinner than the thickness of the gate spacer. At this time, it is preferable to adjust the thicknesses of the first and second spacers 39 and 45 so that the sum of the thicknesses of the first spacer 39 and the second spacer 45 is generally the same as the thickness of the gate spacer.

The second spacers 45 formed on the sidewalls of the recess patterns 44 may prevent short defects from occurring between the gates 38 passing through the device isolation layer 32. At this time, since the depth H3 of the recess pattern 44 is deeper than the depth H2 of the second saddle pin pattern 34B d formed in the device isolation layer 32, short-circuit defects between adjacent gates 38 are more effective. This can be prevented from occurring.

Meanwhile, before forming the first plug 43, the second spacer 45 may be formed first, and then the first plug 43 may be formed. However, when the second spacer 45 is formed before the first plug 43, the contact area between the active region 33 and the first plug 43 may decrease due to the second spacer 45. have. When the contact area decreases, there is a possibility that the contact resistance therebetween increases. When the contact resistance increases therebetween, a problem occurs that the operation speed of the semiconductor device decreases. Therefore, in order to secure the contact area between them as much as possible, it is preferable to first form the first plug 43 and then form the second spacer 45.

As shown in FIGS. 7A and 7B, a second plug 46 filling the remaining contact hole 42 is formed. The second plug 46 may be formed of any one selected from the group consisting of a silicon film, a metallic film, and a conductive organic film or a laminated film in which these are stacked.

Through the above-described process, the landing plug 48 having the structure in which the first plug 43 and the second plug 46 are stacked may be formed. In this case, the landing plug 48 is embedded in the first contact hole 42A and is embedded in the first landing plug 48A and the second contact hole 42B to be connected to the capacitor lower electrode of the semiconductor device through the subsequent process, and the subsequent process. It may include a second landing plug 48B to be connected to the bit line through.

In the process of forming the second plug 46, the second plug 46 partially fills the recess pattern 44. However, due to the second spacer 45 formed on the sidewall of the recess pattern 44, it is possible to prevent the short from occurring between the gate 38 and the second plug 46 embedded in the recess pattern 44. have.

Next, the remaining recess pattern 33 is buried and an oxide film 47 covering the entire structure is formed.

Next, although not shown in the drawings, a plug connected to the second landing plug 48B may be formed through the oxide film 47, and a bit line connected to the plug may be formed on the oxide film 47.

As described above, according to the present invention, the contact hole 42, in particular, the second contact hole 42B is formed in a hole type exposing only the active region 33, so that short-circuit between the gate 38 and the landing plug 48 is poor. This can be prevented from occurring.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A is a plan view showing a semiconductor device having a saddled channel according to the prior art;

FIG. 1B is a cross sectional view taken along the line X-X 'of FIG. 1A; FIG.

Figure 2 is a scanning electron microscope (Scanning Electron Microscope, SEM) image showing a cross-section along the X-X` cut line shown in Figure 1a of the semiconductor device according to the prior art.

3 to 7 are process cross-sectional views illustrating a method of manufacturing a semiconductor device having a saddle fin channel according to an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 device isolation film

33: active area 34: saddle pin pattern

38: gate 39: first spacer

41: hard mask pattern 42: contact hole

43: first plug 44: recess pattern

45: second spacer 46: second plug

48: Landing plug

Claims (19)

Simultaneously forming a gate having a saddle-shaped channel structure across the device isolation layer and the active region on a substrate having an active region defined by the device isolation layer; Forming an insulating film filling the gate; Selectively etching the insulating layer to form a contact hole exposing only the active region; And  Filling the contact hole and forming a landing plug connected to the bit line Semiconductor device manufacturing method comprising a. The method of claim 1, And forming spacers on both sidewalls of the gate. The method of claim 2, And the spacer comprises a nitride film. The method of claim 1, Forming the contact hole, Forming a line type hard mask pattern orthogonal to the gate and intersecting between the active regions on the insulating layer above the device isolation region; And Etching the insulating layer using the hard mask pattern and the gate as an etch barrier Semiconductor device manufacturing method comprising a. The method of claim 1, Forming the gate, Selectively recess-etching the substrate to form a first saddle pin pattern formed in the active region and a second saddle pin formed in the isolation region and exposing a bottom surface and a bottom sidewall of the active region under the first saddle pin pattern; Forming a saddle pin pattern formed of a pattern; And Embedding the saddle pin pattern and forming a gate partially protruding from the substrate; Semiconductor device manufacturing method comprising a. The method of claim 1, And the device isolation film and the insulating film include an oxide film. The method of claim 1, The device isolation film comprises a spin-on insulating film. Simultaneously crossing the device isolation layer and the active region on a defined substrate of an active region by a device isolation layer, and forming a gate having a saddle fin channel structure; Forming a first spacer on both sidewalls of the gate; Forming an insulating film filling the gate; Selectively etching the insulating layer to form a contact hole exposing only the active region; Forming a first plug partially filling the contact hole; Forming a second spacer on the exposed sidewalls of the contact hole; And Forming a second plug to fill the rest of the contact hole, the landing plug comprising the first and second plugs and to be connected to the bit line; Semiconductor device manufacturing method comprising a. The method of claim 8, And the first and second spacers are formed of the same material. The method of claim 8, And the first and second spacers comprise a nitride film. The method of claim 8, Forming the gate, Selectively recess-etching the substrate to form a first saddle pin pattern formed in the active region and a second saddle pin formed in the isolation region and exposing a bottom surface and a bottom sidewall of the active region under the first saddle pin pattern; Forming a saddle pin pattern formed of a pattern; And Embedding the saddle pin pattern and forming a gate partially protruding from the substrate; Semiconductor device manufacturing method comprising a. The method of claim 11, Forming the contact hole, Forming a line type hard mask pattern orthogonal to the gate and intersecting between the active regions on the insulating layer above the device isolation region; And Etching the insulating layer using the hard mask pattern and the gate as an etch barrier Semiconductor device manufacturing method comprising a. The method of claim 8, After forming the contact hole, And recessing the device isolation layer exposing the hard mask pattern and the gate as an etch barrier to form a recess pattern. The method of claim 13, The depth of the recess pattern relative to the upper surface of the substrate is greater than the depth of the second saddle pin pattern. The method of claim 8, And the first plug comprises an epitaxial layer. The method of claim 15, And the epitaxial layer comprises a silicon epitaxial layer. The method of claim 15, And the first plug is formed using a selective epitaxial growth method. The method of claim 8, And the device isolation film and the insulating film include an oxide film. The method of claim 8, The device isolation film comprises a spin-on insulating film.
KR1020080088289A 2008-09-08 2008-09-08 Method for manufacturing semiconductor device KR20100029483A (en)

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